* [RFC 0/6] Versatile Express DT support
@ 2011-11-08 13:16 ` Pawel Moll
0 siblings, 0 replies; 16+ messages in thread
From: Pawel Moll @ 2011-11-08 13:16 UTC (permalink / raw)
To: linux-arm-kernel
Hi All,
This set of patches is a proposal of the Versatile Express DT support.
It's based on the initial idea Dave Martin and myself worked on some
time ago.
The DT-based support for tiles lives in separate files, the motherboard
code was modified as little as possible. The non-DT A9x4 core tile
support is (hopefully) unaffected. The general idea is that non-DT
portions will "evolutionary" disappear over time.
Few comments:
* This series depends on the "of/flattree: Early "find node by alias"
function" patch I posted some time ago:
http://article.gmane.org/gmane.linux.drivers.devicetree/9052
* The V2TILE_PERIPH_P2V() and V2M_PERIPH_P2V() that seem to replace
MMIO_P2V() will disappear one Nico's patches (the ones re-using
static mappings in ioremap()) are merged.
* The SMP callbacks change is just a temporary "hack" that
will go away once machine descriptions are aware of them
(eg. Marc Z.'s "SOC descriptor" patch series).
* I've ignored LCD devices for now - driver doesn't support DT
yet, but a colleague of mine is working on this.
* The v2p-ca5s.c and v2p-ca9.c are (obviously) very similar...
I have some ideas how to merge them, Marc Z. is working on TWD
bindings. Generally the idea is to create the static mapping
basing on a "MPCore private peripherals" device node.
* After rebasing on top of 3.2-rc1 I started to experience major
issues with smsc911x driver... The reason is unknown yet, I'm
trying to figure out what is going on right now.
All comments welcome. It's only RFC for now only, but my goal is to
get as much as possible ready in time for 3.3 merge window. Any
help in achieving this is more then appreciated :-)
Cheers!
Pawel
Pawel Moll (6):
ARM: vexpress: Get rid of MMIO_P2V
ARM: vexpress: Remove platform SMP functions from ct_desc
ARM: vexpress: Add DT support in v2m
ARM: vexpress: DT-based support for Coretile Express A9x4 (V2P-CA9)
ARM: vexpress: Initial RS1 memory map support
ARM: vexpress: DT-based support for Coretile Express A5x2 (V2P-CA5s)
arch/arm/boot/dts/vexpress-v2m-legacy.dtsi | 196 +++++++++++++++++++++
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 196 +++++++++++++++++++++
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 121 +++++++++++++
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 135 ++++++++++++++
arch/arm/include/asm/hardware/arm_timer.h | 5 +
arch/arm/mach-vexpress/Kconfig | 26 +++
arch/arm/mach-vexpress/Makefile | 2 +
arch/arm/mach-vexpress/Makefile.boot | 6 +-
arch/arm/mach-vexpress/core.h | 30 +++-
arch/arm/mach-vexpress/ct-ca9x4.c | 96 ++++-------
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +-
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 ++++-
arch/arm/mach-vexpress/include/mach/motherboard.h | 57 +++----
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 ++-
arch/arm/mach-vexpress/platsmp.c | 11 +-
arch/arm/mach-vexpress/v2m.c | 166 +++++++++++++++---
arch/arm/mach-vexpress/v2p-ca5s.c | 97 ++++++++++
arch/arm/mach-vexpress/v2p-ca9.c | 97 ++++++++++
18 files changed, 1163 insertions(+), 141 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2m-legacy.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
create mode 100644 arch/arm/mach-vexpress/v2p-ca5s.c
create mode 100644 arch/arm/mach-vexpress/v2p-ca9.c
^ permalink raw reply [flat|nested] 16+ messages in thread
* [RFC 0/6] Versatile Express DT support
@ 2011-11-08 13:16 ` Pawel Moll
0 siblings, 0 replies; 16+ messages in thread
From: Pawel Moll @ 2011-11-08 13:16 UTC (permalink / raw)
To: linux-arm-kernel, devicetree-discuss; +Cc: Pawel Moll
Hi All,
This set of patches is a proposal of the Versatile Express DT support.
It's based on the initial idea Dave Martin and myself worked on some
time ago.
The DT-based support for tiles lives in separate files, the motherboard
code was modified as little as possible. The non-DT A9x4 core tile
support is (hopefully) unaffected. The general idea is that non-DT
portions will "evolutionary" disappear over time.
Few comments:
* This series depends on the "of/flattree: Early "find node by alias"
function" patch I posted some time ago:
http://article.gmane.org/gmane.linux.drivers.devicetree/9052
* The V2TILE_PERIPH_P2V() and V2M_PERIPH_P2V() that seem to replace
MMIO_P2V() will disappear one Nico's patches (the ones re-using
static mappings in ioremap()) are merged.
* The SMP callbacks change is just a temporary "hack" that
will go away once machine descriptions are aware of them
(eg. Marc Z.'s "SOC descriptor" patch series).
* I've ignored LCD devices for now - driver doesn't support DT
yet, but a colleague of mine is working on this.
* The v2p-ca5s.c and v2p-ca9.c are (obviously) very similar...
I have some ideas how to merge them, Marc Z. is working on TWD
bindings. Generally the idea is to create the static mapping
basing on a "MPCore private peripherals" device node.
* After rebasing on top of 3.2-rc1 I started to experience major
issues with smsc911x driver... The reason is unknown yet, I'm
trying to figure out what is going on right now.
All comments welcome. It's only RFC for now only, but my goal is to
get as much as possible ready in time for 3.3 merge window. Any
help in achieving this is more then appreciated :-)
Cheers!
Pawel
Pawel Moll (6):
ARM: vexpress: Get rid of MMIO_P2V
ARM: vexpress: Remove platform SMP functions from ct_desc
ARM: vexpress: Add DT support in v2m
ARM: vexpress: DT-based support for Coretile Express A9x4 (V2P-CA9)
ARM: vexpress: Initial RS1 memory map support
ARM: vexpress: DT-based support for Coretile Express A5x2 (V2P-CA5s)
arch/arm/boot/dts/vexpress-v2m-legacy.dtsi | 196 +++++++++++++++++++++
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 196 +++++++++++++++++++++
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 121 +++++++++++++
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 135 ++++++++++++++
arch/arm/include/asm/hardware/arm_timer.h | 5 +
arch/arm/mach-vexpress/Kconfig | 26 +++
arch/arm/mach-vexpress/Makefile | 2 +
arch/arm/mach-vexpress/Makefile.boot | 6 +-
arch/arm/mach-vexpress/core.h | 30 +++-
arch/arm/mach-vexpress/ct-ca9x4.c | 96 ++++-------
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +-
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 ++++-
arch/arm/mach-vexpress/include/mach/motherboard.h | 57 +++----
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 ++-
arch/arm/mach-vexpress/platsmp.c | 11 +-
arch/arm/mach-vexpress/v2m.c | 166 +++++++++++++++---
arch/arm/mach-vexpress/v2p-ca5s.c | 97 ++++++++++
arch/arm/mach-vexpress/v2p-ca9.c | 97 ++++++++++
18 files changed, 1163 insertions(+), 141 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2m-legacy.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
create mode 100644 arch/arm/mach-vexpress/v2p-ca5s.c
create mode 100644 arch/arm/mach-vexpress/v2p-ca9.c
^ permalink raw reply [flat|nested] 16+ messages in thread
* [RFC 1/6] ARM: vexpress: Get rid of MMIO_P2V
[not found] ` <1320758169-22668-1-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
@ 2011-11-08 13:16 ` Pawel Moll
2011-11-08 13:16 ` [RFC 2/6] ARM: vexpress: Remove platform SMP functions from ct_desc Pawel Moll
` (4 subsequent siblings)
5 siblings, 0 replies; 16+ messages in thread
From: Pawel Moll @ 2011-11-08 13:16 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Pawel Moll
This patch gets rid of the MMIO_P2V and __MMPIO_P2V macros,
defining constant virtual base for motherboard and tile
peripherals instead.
Additionally, in preparation for the new motherboard memory
map, the motherboard peripherals are using base pointers
calculated in runtime, instead of compile-time calculated
values.
Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/include/asm/hardware/arm_timer.h | 5 ++
arch/arm/mach-vexpress/core.h | 10 +++-
arch/arm/mach-vexpress/ct-ca9x4.c | 52 ++++--------------
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 ++---
arch/arm/mach-vexpress/include/mach/motherboard.h | 53 +++++++++----------
arch/arm/mach-vexpress/platsmp.c | 4 +-
arch/arm/mach-vexpress/v2m.c | 58 +++++++++++++-------
7 files changed, 93 insertions(+), 102 deletions(-)
diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h
index c0f4e7b..d6030ff 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -9,7 +9,12 @@
*
* Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
* can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
*/
+#define TIMER_1_BASE 0x00
+#define TIMER_2_BASE 0x20
+
#define TIMER_LOAD 0x00 /* ACVR rw */
#define TIMER_VALUE 0x04 /* ACVR ro */
#define TIMER_CTRL 0x08 /* ACVR rw */
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f439715..711c9a0 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,6 +1,3 @@
-#define __MMIO_P2V(x) (((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000)
-#define MMIO_P2V(x) ((void __iomem *)__MMIO_P2V(x))
-
#define AMBA_DEVICE(name,busid,base,plat) \
struct amba_device name##_device = { \
.dev = { \
@@ -17,3 +14,10 @@ struct amba_device name##_device = { \
.irq = IRQ_##base, \
/* .dma = DMA_##base,*/ \
}
+
+#define V2M_PERIPH 0xf8000000
+#define V2M_PERIPH_P2V(offset) ((void __iomem *)(V2M_PERIPH | (offset)))
+
+#define V2TILE_PERIPH 0xf8200000
+#define V2TILE_PERIPH_P2V(offset) ((void __iomem *)(V2TILE_PERIPH | (offset)))
+
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 2b1e836..567a6aa 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -30,57 +30,26 @@
#include <plat/clcd.h>
-#define V2M_PA_CS7 0x10000000
-
static struct map_desc ct_ca9x4_io_desc[] __initdata = {
{
- .virtual = __MMIO_P2V(CT_CA9X4_MPIC),
- .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
- .length = SZ_16K,
- .type = MT_DEVICE,
- }, {
- .virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
- .pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = __MMIO_P2V(CT_CA9X4_L2CC),
- .pfn = __phys_to_pfn(CT_CA9X4_L2CC),
- .length = SZ_4K,
- .type = MT_DEVICE,
+ .virtual = V2TILE_PERIPH,
+ .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
},
};
static void __init ct_ca9x4_map_io(void)
{
-#ifdef CONFIG_LOCAL_TIMERS
- twd_base = MMIO_P2V(A9_MPCORE_TWD);
-#endif
iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}
static void __init ct_ca9x4_init_irq(void)
{
- gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
- MMIO_P2V(A9_MPCORE_GIC_CPU));
-}
-
-#if 0
-static void __init ct_ca9x4_timer_init(void)
-{
- writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
-
- sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
- sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
- "ct-timer0");
+ gic_init(0, 29, V2TILE_PERIPH_P2V(A9_MPCORE_GIC_DIST),
+ V2TILE_PERIPH_P2V(A9_MPCORE_GIC_CPU));
}
-static struct sys_timer ct_ca9x4_timer = {
- .init = ct_ca9x4_timer_init,
-};
-#endif
-
static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
@@ -193,6 +162,9 @@ static struct platform_device pmu_device = {
static void __init ct_ca9x4_init_early(void)
{
+#ifdef CONFIG_LOCAL_TIMERS
+ twd_base = V2TILE_PERIPH_P2V(A9_MPCORE_TWD);
+#endif
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
}
@@ -201,7 +173,7 @@ static void __init ct_ca9x4_init(void)
int i;
#ifdef CONFIG_CACHE_L2X0
- void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
+ void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
/* set RAM latencies to 1 cycle for this core tile. */
writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
@@ -219,7 +191,7 @@ static void __init ct_ca9x4_init(void)
#ifdef CONFIG_SMP
static void ct_ca9x4_init_cpu_map(void)
{
- int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
+ int i, ncores = scu_get_core_count(V2TILE_PERIPH_P2V(A9_MPCORE_SCU));
if (ncores > nr_cpu_ids) {
pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
@@ -235,7 +207,7 @@ static void ct_ca9x4_init_cpu_map(void)
static void ct_ca9x4_smp_enable(unsigned int max_cpus)
{
- scu_enable(MMIO_P2V(A9_MPCORE_SCU));
+ scu_enable(V2TILE_PERIPH_P2V(A9_MPCORE_SCU));
}
#endif
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
index a34d3d4..8f962fb 100644
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -22,14 +22,11 @@
#define CT_CA9X4_SYSWDT (0x1e007000)
#define CT_CA9X4_L2CC (0x1e00a000)
-#define CT_CA9X4_TIMER0 (CT_CA9X4_SP804_TIMER + 0x000)
-#define CT_CA9X4_TIMER1 (CT_CA9X4_SP804_TIMER + 0x020)
-
-#define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000)
-#define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100)
-#define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200)
-#define A9_MPCORE_TWD (CT_CA9X4_MPIC + 0x0600)
-#define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000)
+#define A9_MPCORE_SCU 0x0000
+#define A9_MPCORE_GIC_CPU 0x0100
+#define A9_MPCORE_GIT 0x0200
+#define A9_MPCORE_TWD 0x0600
+#define A9_MPCORE_GIC_DIST 0x1000
/*
* Interrupts. Those in {} are for AMBA devices
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index 0a3a375..da9ac29 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -39,34 +39,30 @@
#define V2M_CF (V2M_PA_CS7 + 0x0001a000)
#define V2M_CLCD (V2M_PA_CS7 + 0x0001f000)
-#define V2M_SYS_ID (V2M_SYSREGS + 0x000)
-#define V2M_SYS_SW (V2M_SYSREGS + 0x004)
-#define V2M_SYS_LED (V2M_SYSREGS + 0x008)
-#define V2M_SYS_100HZ (V2M_SYSREGS + 0x024)
-#define V2M_SYS_FLAGS (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSSET (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSCLR (V2M_SYSREGS + 0x034)
-#define V2M_SYS_NVFLAGS (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSSET (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSCLR (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_MCI (V2M_SYSREGS + 0x048)
-#define V2M_SYS_FLASH (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_CFGSW (V2M_SYSREGS + 0x058)
-#define V2M_SYS_24MHZ (V2M_SYSREGS + 0x05c)
-#define V2M_SYS_MISC (V2M_SYSREGS + 0x060)
-#define V2M_SYS_DMA (V2M_SYSREGS + 0x064)
-#define V2M_SYS_PROCID0 (V2M_SYSREGS + 0x084)
-#define V2M_SYS_PROCID1 (V2M_SYSREGS + 0x088)
-#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
-#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
-#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
-
-#define V2M_TIMER0 (V2M_TIMER01 + 0x000)
-#define V2M_TIMER1 (V2M_TIMER01 + 0x020)
-
-#define V2M_TIMER2 (V2M_TIMER23 + 0x000)
-#define V2M_TIMER3 (V2M_TIMER23 + 0x020)
-
+/*
+ * Offsets from SYSREGS base
+ */
+#define V2M_SYS_ID 0x000
+#define V2M_SYS_SW 0x004
+#define V2M_SYS_LED 0x008
+#define V2M_SYS_100HZ 0x024
+#define V2M_SYS_FLAGS 0x030
+#define V2M_SYS_FLAGSSET 0x030
+#define V2M_SYS_FLAGSCLR 0x034
+#define V2M_SYS_NVFLAGS 0x038
+#define V2M_SYS_NVFLAGSSET 0x038
+#define V2M_SYS_NVFLAGSCLR 0x03c
+#define V2M_SYS_MCI 0x048
+#define V2M_SYS_FLASH 0x03c
+#define V2M_SYS_CFGSW 0x058
+#define V2M_SYS_24MHZ 0x05c
+#define V2M_SYS_MISC 0x060
+#define V2M_SYS_DMA 0x064
+#define V2M_SYS_PROCID0 0x084
+#define V2M_SYS_PROCID1 0x088
+#define V2M_SYS_CFGDATA 0x0a0
+#define V2M_SYS_CFGCTRL 0x0a4
+#define V2M_SYS_CFGSTAT 0x0a8
/*
* Interrupts. Those in {} are for AMBA devices
@@ -117,6 +113,7 @@
int v2m_cfg_write(u32 devfn, u32 data);
int v2m_cfg_read(u32 devfn, u32 *data);
+void v2m_flags_set(u32 data);
/*
* Core tile IDs
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 2b5f7ac..e8be99d 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -45,7 +45,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
- writel(BSYM(virt_to_phys(versatile_secondary_startup)),
- MMIO_P2V(V2M_SYS_FLAGSSET));
+ v2m_flags_set(BSYM(virt_to_phys(versatile_secondary_startup)));
}
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 1fafc32..2f44425 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -39,28 +39,34 @@
static struct map_desc v2m_io_desc[] __initdata = {
{
- .virtual = __MMIO_P2V(V2M_PA_CS7),
+ .virtual = V2M_PERIPH,
.pfn = __phys_to_pfn(V2M_PA_CS7),
.length = SZ_128K,
.type = MT_DEVICE,
},
};
+static void __iomem *v2m_sysreg_base;
+static void __iomem *v2m_sysctl_base;
+static void __iomem *v2m_timer01_base;
+
+
+
static void __init v2m_timer_init(void)
{
u32 scctrl;
/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
- scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
+ scctrl = readl(v2m_sysctl_base + SCCTRL);
scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
- writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL));
+ writel(scctrl, v2m_sysctl_base + SCCTRL);
- writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
+ writel(0, v2m_timer01_base + TIMER_1_BASE + TIMER_CTRL);
+ writel(0, v2m_timer01_base + TIMER_2_BASE + TIMER_CTRL);
- sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
- sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0,
+ sp804_clocksource_init(v2m_timer01_base + TIMER_1_BASE, "v2m-timer1");
+ sp804_clockevents_init(v2m_timer01_base + TIMER_2_BASE, IRQ_V2M_TIMER0,
"v2m-timer0");
}
@@ -81,14 +87,14 @@ int v2m_cfg_write(u32 devfn, u32 data)
devfn |= SYS_CFG_START | SYS_CFG_WRITE;
spin_lock(&v2m_cfg_lock);
- val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
- writel(val & ~SYS_CFG_COMPLETE, MMIO_P2V(V2M_SYS_CFGSTAT));
+ val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
+ writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
- writel(data, MMIO_P2V(V2M_SYS_CFGDATA));
- writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+ writel(data, v2m_sysreg_base + V2M_SYS_CFGDATA);
+ writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
do {
- val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+ val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
} while (val == 0);
spin_unlock(&v2m_cfg_lock);
@@ -102,22 +108,27 @@ int v2m_cfg_read(u32 devfn, u32 *data)
devfn |= SYS_CFG_START;
spin_lock(&v2m_cfg_lock);
- writel(0, MMIO_P2V(V2M_SYS_CFGSTAT));
- writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+ writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
+ writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
mb();
do {
cpu_relax();
- val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+ val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
} while (val == 0);
- *data = readl(MMIO_P2V(V2M_SYS_CFGDATA));
+ *data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
spin_unlock(&v2m_cfg_lock);
return !!(val & SYS_CFG_ERR);
}
+void __init v2m_flags_set(u32 data)
+{
+ writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
+ writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
+}
static struct resource v2m_pcie_i2c_resource = {
.start = V2M_SERIAL_BUS_PCI,
@@ -203,7 +214,7 @@ static struct platform_device v2m_usb_device = {
static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
{
- writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
+ writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
}
static struct physmap_flash_data v2m_flash_data = {
@@ -257,7 +268,7 @@ static struct platform_device v2m_cf_device = {
static unsigned int v2m_mmci_status(struct device *dev)
{
- return readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0);
+ return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
}
static struct mmci_platform_data v2m_mmci_data = {
@@ -370,7 +381,7 @@ static void __init v2m_init_early(void)
{
ct_desc->init_early();
clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
- versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
+ versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
}
static void v2m_power_off(void)
@@ -399,7 +410,8 @@ static void __init v2m_populate_ct_desc(void)
u32 current_tile_id;
ct_desc = NULL;
- current_tile_id = readl(MMIO_P2V(V2M_SYS_PROCID0)) & V2M_CT_ID_MASK;
+ current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
+ & V2M_CT_ID_MASK;
for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
if (ct_descs[i]->id == current_tile_id)
@@ -413,6 +425,12 @@ static void __init v2m_populate_ct_desc(void)
static void __init v2m_map_io(void)
{
iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+
+ /* Will become nice ioremap()-s once allowed */
+ v2m_sysreg_base = V2M_PERIPH_P2V(V2M_SYSREGS);
+ v2m_sysctl_base = V2M_PERIPH_P2V(V2M_SYSCTL);
+ v2m_timer01_base = V2M_PERIPH_P2V(V2M_TIMER01);
+
v2m_populate_ct_desc();
ct_desc->map_io();
}
--
1.6.3.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 2/6] ARM: vexpress: Remove platform SMP functions from ct_desc
[not found] ` <1320758169-22668-1-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
2011-11-08 13:16 ` [RFC 1/6] ARM: vexpress: Get rid of MMIO_P2V Pawel Moll
@ 2011-11-08 13:16 ` Pawel Moll
2011-11-08 13:16 ` [RFC 3/6] ARM: vexpress: Add DT support in v2m Pawel Moll
` (3 subsequent siblings)
5 siblings, 0 replies; 16+ messages in thread
From: Pawel Moll @ 2011-11-08 13:16 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Pawel Moll
This patch removes platform SMP callbacks from ct_desc struct
and replaces them with global symbols in preparation for
DT-based support code.
This is a temporary measure till "SoC descriptors" code
gets into the main line.
Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/mach-vexpress/core.h | 6 +++
arch/arm/mach-vexpress/ct-ca9x4.c | 50 +++++++++-----------
arch/arm/mach-vexpress/include/mach/motherboard.h | 4 --
arch/arm/mach-vexpress/platsmp.c | 7 ++-
4 files changed, 34 insertions(+), 33 deletions(-)
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index 711c9a0..7a3ce7a 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -21,3 +21,9 @@ struct amba_device name##_device = { \
#define V2TILE_PERIPH 0xf8200000
#define V2TILE_PERIPH_P2V(offset) ((void __iomem *)(V2TILE_PERIPH | (offset)))
+/* Will disappear once SoC descriptor gets in */
+#if defined(CONFIG_SMP)
+extern void (*vexpress_init_cpu_map)(void);
+extern void (*vexpress_smp_enable)(unsigned int);
+#endif
+
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 567a6aa..f0d9f9a 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -39,9 +39,32 @@ static struct map_desc ct_ca9x4_io_desc[] __initdata = {
},
};
+#ifdef CONFIG_SMP
+static void ct_ca9x4_init_cpu_map(void)
+{
+ int i, ncores;
+ ncores = scu_get_core_count(V2TILE_PERIPH_P2V(A9_MPCORE_SCU));
+
+ for (i = 0; i < ncores; ++i)
+ set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
+}
+
+static void ct_ca9x4_smp_enable(unsigned int max_cpus)
+{
+ scu_enable(V2TILE_PERIPH_P2V(A9_MPCORE_SCU));
+}
+#endif
+
static void __init ct_ca9x4_map_io(void)
{
iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
+#ifdef CONFIG_SMP
+ /* Will be gone once the SoC descriptors are in */
+ vexpress_init_cpu_map = ct_ca9x4_init_cpu_map;
+ vexpress_smp_enable = ct_ca9x4_smp_enable;
+#endif
}
static void __init ct_ca9x4_init_irq(void)
@@ -188,29 +211,6 @@ static void __init ct_ca9x4_init(void)
platform_device_register(&pmu_device);
}
-#ifdef CONFIG_SMP
-static void ct_ca9x4_init_cpu_map(void)
-{
- int i, ncores = scu_get_core_count(V2TILE_PERIPH_P2V(A9_MPCORE_SCU));
-
- if (ncores > nr_cpu_ids) {
- pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
- ncores, nr_cpu_ids);
- ncores = nr_cpu_ids;
- }
-
- for (i = 0; i < ncores; ++i)
- set_cpu_possible(i, true);
-
- set_smp_cross_call(gic_raise_softirq);
-}
-
-static void ct_ca9x4_smp_enable(unsigned int max_cpus)
-{
- scu_enable(V2TILE_PERIPH_P2V(A9_MPCORE_SCU));
-}
-#endif
-
struct ct_desc ct_ca9x4_desc __initdata = {
.id = V2M_CT_ID_CA9,
.name = "CA9x4",
@@ -218,8 +218,4 @@ struct ct_desc ct_ca9x4_desc __initdata = {
.init_early = ct_ca9x4_init_early,
.init_irq = ct_ca9x4_init_irq,
.init_tile = ct_ca9x4_init,
-#ifdef CONFIG_SMP
- .init_cpu_map = ct_ca9x4_init_cpu_map,
- .smp_enable = ct_ca9x4_smp_enable,
-#endif
};
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index da9ac29..848353b 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -129,10 +129,6 @@ struct ct_desc {
void (*init_early)(void);
void (*init_irq)(void);
void (*init_tile)(void);
-#ifdef CONFIG_SMP
- void (*init_cpu_map)(void);
- void (*smp_enable)(unsigned int);
-#endif
};
extern struct ct_desc *ct_desc;
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index e8be99d..b41e4e8 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -20,6 +20,9 @@
#include "core.h"
+void (*vexpress_init_cpu_map)(void);
+void (*vexpress_smp_enable)(unsigned int);
+
extern void versatile_secondary_startup(void);
/*
@@ -28,7 +31,7 @@ extern void versatile_secondary_startup(void);
*/
void __init smp_init_cpus(void)
{
- ct_desc->init_cpu_map();
+ vexpress_init_cpu_map();
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
@@ -37,7 +40,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* Initialise the present map, which describes the set of CPUs
* actually populated at the present time.
*/
- ct_desc->smp_enable(max_cpus);
+ vexpress_smp_enable(max_cpus);
/*
* Write the address of secondary startup into the
--
1.6.3.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 3/6] ARM: vexpress: Add DT support in v2m
[not found] ` <1320758169-22668-1-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
2011-11-08 13:16 ` [RFC 1/6] ARM: vexpress: Get rid of MMIO_P2V Pawel Moll
2011-11-08 13:16 ` [RFC 2/6] ARM: vexpress: Remove platform SMP functions from ct_desc Pawel Moll
@ 2011-11-08 13:16 ` Pawel Moll
2011-11-08 14:17 ` Rob Herring
2011-11-08 13:16 ` [RFC 4/6] ARM: vexpress: DT-based support for Coretile Express A9x4 (V2P-CA9) Pawel Moll
` (2 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Pawel Moll @ 2011-11-08 13:16 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Pawel Moll
This patch provides hooks for DT-based tile machine implementations.
Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/mach-vexpress/Kconfig | 8 ++++
arch/arm/mach-vexpress/core.h | 13 +++++++
arch/arm/mach-vexpress/v2m.c | 79 +++++++++++++++++++++++++++++++++++++++-
3 files changed, 99 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 9311484..9370f5b 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,6 +1,9 @@
menu "Versatile Express platform type"
depends on ARCH_VEXPRESS
+config ARCH_VEXPRESS_LEGACY
+ bool
+
config ARCH_VEXPRESS_CA9X4
bool "Versatile Express Cortex-A9x4 tile"
select CPU_V7
@@ -8,5 +11,10 @@ config ARCH_VEXPRESS_CA9X4
select ARM_ERRATA_720789
select ARM_ERRATA_751472
select ARM_ERRATA_753970
+ select ARCH_VEXPRESS_LEGACY
+
+config ARCH_VEXPRESS_DT
+ bool
+ select OF
endmenu
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index 7a3ce7a..0ea502a 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -27,3 +27,16 @@ extern void (*vexpress_init_cpu_map)(void);
extern void (*vexpress_smp_enable)(unsigned int);
#endif
+extern struct sys_timer v2m_timer;
+
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+
+enum v2m_memory_map {
+ v2m_memory_map_legacy,
+};
+
+void __init v2m_dt_map_io(enum v2m_memory_map map);
+void __init v2m_dt_init_early(void);
+struct of_dev_auxdata * __init v2m_dt_get_auxdata(enum v2m_memory_map map);
+
+#endif
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 2f44425..39900c4 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -6,6 +6,9 @@
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/init.h>
+#include <linux/irqdomain.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/smsc911x.h>
@@ -70,7 +73,8 @@ static void __init v2m_timer_init(void)
"v2m-timer0");
}
-static struct sys_timer v2m_timer = {
+/* May be used by DT-powered machines */
+struct sys_timer v2m_timer = {
.init = v2m_timer_init,
};
@@ -468,3 +472,76 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
.timer = &v2m_timer,
.init_machine = v2m_init,
MACHINE_END
+
+
+
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+
+static unsigned long __init v2m_dt_periph_offset(const char *alias)
+{
+ unsigned long node;
+ __be32 *reg;
+ unsigned long len;
+
+ if (of_flat_dt_find_node_by_alias(alias, &node) != 0)
+ panic("%s: Can't get offset for '%s'!\n", __func__, alias);
+
+ reg = of_get_flat_dt_prop(node, "reg", &len);
+ if (!reg)
+ panic("%s: Can't get reg property for '%s'!\n",
+ __func__, alias);
+
+ return be32_to_cpup(reg);
+}
+
+void __init v2m_dt_map_io(enum v2m_memory_map map)
+{
+ switch (map) {
+ case v2m_memory_map_legacy:
+ iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+ break;
+ default:
+ panic("%s: Unknown memory map requested!\n", __func__);
+ break;
+ }
+
+ /* Will become nice ioremap()-s once allowed */
+ v2m_sysreg_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("sysreg"));
+ v2m_sysctl_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("sysctl"));
+ v2m_timer01_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("timer01"));
+}
+
+void __init v2m_dt_init_early(void)
+{
+ clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
+ versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
+ pm_power_off = v2m_power_off;
+ arm_pm_restart = v2m_restart;
+}
+
+static struct of_dev_auxdata v2m_legacy_dt_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
+ &v2m_flash_data),
+ OF_DEV_AUXDATA("arm,primecell", V2M_WDT, "mb:wdt", NULL),
+ OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
+ OF_DEV_AUXDATA("arm,primecell", V2M_KMI0, "mb:kmi0", NULL),
+ OF_DEV_AUXDATA("arm,primecell", V2M_KMI1, "mb:kmi1", NULL),
+ OF_DEV_AUXDATA("arm,primecell", V2M_UART0, "mb:uart0", NULL),
+ OF_DEV_AUXDATA("arm,primecell", V2M_UART1, "mb:uart1", NULL),
+ OF_DEV_AUXDATA("arm,primecell", V2M_UART2, "mb:uart2", NULL),
+ OF_DEV_AUXDATA("arm,primecell", V2M_UART3, "mb:uart3", NULL),
+ {}
+};
+
+struct of_dev_auxdata * __init v2m_dt_get_auxdata(enum v2m_memory_map map)
+{
+ switch (map) {
+ case v2m_memory_map_legacy:
+ return v2m_legacy_dt_auxdata_lookup;
+ default:
+ panic("%s: Unknown memory map requested!\n", __func__);
+ return NULL;
+ }
+}
+
+#endif
--
1.6.3.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 4/6] ARM: vexpress: DT-based support for Coretile Express A9x4 (V2P-CA9)
[not found] ` <1320758169-22668-1-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
` (2 preceding siblings ...)
2011-11-08 13:16 ` [RFC 3/6] ARM: vexpress: Add DT support in v2m Pawel Moll
@ 2011-11-08 13:16 ` Pawel Moll
2011-11-08 13:16 ` [RFC 5/6] ARM: vexpress: Initial RS1 memory map support Pawel Moll
2011-11-08 13:16 ` [RFC 6/6] ARM: vexpress: DT-based support for Coretile Express A5x2 (V2P-CA5s) Pawel Moll
5 siblings, 0 replies; 16+ messages in thread
From: Pawel Moll @ 2011-11-08 13:16 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Pawel Moll
This patch adds Device Tree for ARM Ltd. Coretile Express A9x4
used with V2M motherboard and an initial implementation of the
DT machine support (this code is separate from the current core
tile code).
Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/boot/dts/vexpress-v2m-legacy.dtsi | 196 ++++++++++++++++++++++++++++
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 135 +++++++++++++++++++
arch/arm/mach-vexpress/Kconfig | 8 +
arch/arm/mach-vexpress/Makefile | 1 +
arch/arm/mach-vexpress/v2p-ca9.c | 97 ++++++++++++++
5 files changed, 437 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2m-legacy.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
create mode 100644 arch/arm/mach-vexpress/v2p-ca9.c
diff --git a/arch/arm/boot/dts/vexpress-v2m-legacy.dtsi b/arch/arm/boot/dts/vexpress-v2m-legacy.dtsi
new file mode 100644
index 0000000..984e917
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-legacy.dtsi
@@ -0,0 +1,196 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * Legacy memory map
+ */
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ timer01 = &timer01;
+ timer23 = &timer23;
+ sysreg = &sysreg;
+ sysctl = &sysctl;
+ };
+
+ motherboard {
+ compatible = "simple-bus";
+ #address-cells = <2>; /* SMB chipselect number and offset */
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ flash@0,00000000 {
+ compatible = "arm,vexpress-flash", "cfi-flash";
+ reg = <0 0x00000000 0x04000000
+ 1 0x00000000 0x04000000>;
+ bank-width = <4>;
+ };
+
+ psram@2,00000000 {
+ compatible = "mtd-ram";
+ reg = <2 0x00000000 0x02000000>;
+ bank-width = <4>;
+ };
+
+ ethernet@3,02000000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <3 0x02000000 0x10000>;
+ interrupts = <15>;
+ phy-mode = "mii";
+ reg-io-width = <32>;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb@3,03000000 {
+ compatible = "nxp,usb-isp1761";
+ reg = <3 0x03000000 0x20000>;
+ interrupts = <16>;
+ port1-otg;
+ };
+
+ peripherals@7,00000000 {
+ compatible = "arm,amba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 7 0 0x20000>;
+
+ sysreg: sysreg@00000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x00000 0x1000>;
+ };
+
+ sysctl: sysctl@01000 {
+ compatible = "arm,sp810";
+ reg = <0x01000 0x1000>;
+ };
+
+ /* PCI-E I2C bus */
+ i2c0: i2c@02000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x02000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie-switch@60 {
+ compatible = "idt,89hpes32h8";
+ reg = <0x60>;
+ };
+ };
+
+ aaci@04000 {
+ compatible = "arm,pl041", "arm,primecell";
+ reg = <0x04000 0x1000>;
+ interrupts = <11>;
+ };
+
+ mmci@05000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x05000 0x1000>;
+ interrupts = <9 10>;
+ };
+
+ kmi@06000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x06000 0x1000>;
+ interrupts = <12>;
+ };
+
+ kmi@07000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x07000 0x1000>;
+ interrupts = <13>;
+ };
+
+ uart0: uart@09000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x09000 0x1000>;
+ interrupts = <5>;
+ };
+
+ uart1: uart@0a000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0a000 0x1000>;
+ interrupts = <6>;
+ };
+
+ uart2: uart@0b000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0b000 0x1000>;
+ interrupts = <7>;
+ };
+
+ uart3: uart@0c000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0c000 0x1000>;
+ interrupts = <8>;
+ };
+
+ wdt@0f000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0f000 0x1000>;
+ interrupts = <0>;
+ };
+
+ timer01: timer@11000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x11000 0x1000>;
+ interrupts = <2>;
+ };
+
+ timer23: timer@12000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ };
+
+ /* DVI I2C bus */
+ i2c1: i2c@16000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x16000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dvi-switch-a@39 {
+ compatible = "sil,sii9022";
+ reg = <0x39>;
+ };
+
+ dvi-switch-b@60 {
+ compatible = "sil,sii9022";
+ reg = <0x60>;
+ };
+ };
+
+ rtc@17000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x017000 0x1000>;
+ interrupts = <4>;
+ };
+
+ compact-flash@1a000 {
+ compatible = "ata-generic";
+ reg = <0x1a000 0x100
+ 0x1a100 0xf00>;
+ reg-shift = <2>;
+ };
+
+ clcd@1f000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x1f000 0x1000>;
+ interrupts = <14>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
new file mode 100644
index 0000000..fc9aa38
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -0,0 +1,135 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Coretile Express A9x4
+ * Cortex-A9 MPCore (V2P-CA9)
+ *
+ * HBI-0191B
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA9";
+ compatible = "arm,vexpress-v2p-ca9", "arm,vexpress-legacy", "arm,vexpress";
+ interrupt-parent = <&gic>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ clcd@10020000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x10020000 0x1000>;
+ interrupts = <0 44 4>;
+ };
+
+ dmc@100e0000 {
+ compatible = "arm,pl341", "arm,primecell";
+ reg = <0x100e0000 0x1000>;
+ };
+
+ smc@100e1000 {
+ compatible = "arm,pl354", "arm,primecell";
+ reg = <0x100e1000 0x1000>;
+ interrupts = <0 45 4>,
+ <0 46 4>;
+ };
+
+ timer@100e4000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x100e4000 0x1000>;
+ interrupts = <0 48 4>,
+ <0 49 4>;
+ };
+
+ watchdog@100e5000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x100e5000 0x1000>;
+ interrupts = <0 51 4>;
+ };
+
+ gic: interrupt-controller@1e001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1e001000 0x1000>,
+ <0x1e000100 0x100>;
+ };
+
+ L2: cache-controller@1e00a000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x1e00a000 0x1000>;
+ interrupts = <0 43 4>;
+ cache-level = <2>;
+ arm,data-latency = <0>;
+ arm,tag-latency = <0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 60 4>,
+ <0 61 4>,
+ <0 62 4>,
+ <0 63 4>;
+ };
+
+ motherboard {
+ ranges = <0 0 0x40000000 0x04000000>,
+ <1 0 0x44000000 0x04000000>,
+ <2 0 0x48000000 0x04000000>,
+ <3 0 0x4c000000 0x04000000>,
+ <7 0 0x10000000 0x00020000>;
+
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 4>,
+ <0 0 1 &gic 0 1 4>,
+ <0 0 2 &gic 0 2 4>,
+ <0 0 3 &gic 0 3 4>,
+ <0 0 4 &gic 0 4 4>,
+ <0 0 5 &gic 0 5 4>,
+ <0 0 6 &gic 0 6 4>,
+ <0 0 7 &gic 0 7 4>,
+ <0 0 8 &gic 0 8 4>,
+ <0 0 9 &gic 0 9 4>,
+ <0 0 10 &gic 0 10 4>,
+ <0 0 11 &gic 0 11 4>,
+ <0 0 12 &gic 0 12 4>,
+ <0 0 13 &gic 0 13 4>,
+ <0 0 14 &gic 0 14 4>,
+ <0 0 15 &gic 0 15 4>,
+ <0 0 16 &gic 0 16 4>,
+ <0 0 17 &gic 0 17 4>,
+ <0 0 18 &gic 0 18 4>,
+ <0 0 19 &gic 0 19 4>,
+ <0 0 20 &gic 0 20 4>,
+ <0 0 21 &gic 0 21 4>,
+ <0 0 22 &gic 0 22 4>,
+ <0 0 23 &gic 0 23 4>,
+ <0 0 24 &gic 0 24 4>,
+ <0 0 25 &gic 0 25 4>,
+ <0 0 26 &gic 0 26 4>,
+ <0 0 27 &gic 0 27 4>,
+ <0 0 28 &gic 0 28 4>,
+ <0 0 29 &gic 0 29 4>,
+ <0 0 30 &gic 0 30 4>,
+ <0 0 31 &gic 0 31 4>,
+ <0 0 32 &gic 0 32 4>,
+ <0 0 33 &gic 0 33 4>,
+ <0 0 34 &gic 0 34 4>,
+ <0 0 35 &gic 0 35 4>,
+ <0 0 36 &gic 0 36 4>,
+ <0 0 37 &gic 0 37 4>,
+ <0 0 38 &gic 0 38 4>,
+ <0 0 39 &gic 0 39 4>,
+ <0 0 40 &gic 0 40 4>,
+ <0 0 41 &gic 0 41 4>,
+ <0 0 42 &gic 0 42 4>;
+ };
+};
+
+/include/ "vexpress-v2m-legacy.dtsi"
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 9370f5b..27c1294 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -17,4 +17,12 @@ config ARCH_VEXPRESS_DT
bool
select OF
+config ARCH_VEXPRESS_V2P_CA9
+ bool "CoreTile Express A9x4 (V2P-CA9) - DT"
+ select ARCH_VEXPRESS_LEGACY
+ select ARCH_VEXPRESS_DT
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_751472
+ select ARM_ERRATA_753970
+
endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 90551b9..9cc4a21 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -4,5 +4,6 @@
obj-y := v2m.o
obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
+obj-$(CONFIG_ARCH_VEXPRESS_V2P_CA9) += v2p-ca9.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-vexpress/v2p-ca9.c b/arch/arm/mach-vexpress/v2p-ca9.c
new file mode 100644
index 0000000..280236c
--- /dev/null
+++ b/arch/arm/mach-vexpress/v2p-ca9.c
@@ -0,0 +1,97 @@
+/*
+ * Device Tree based support for ARM Versatile Express board
+ * with CoreTile Express A9x4 (V2P-CA9)
+ */
+
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/smp_scu.h>
+#include <asm/smp_twd.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "core.h"
+
+#define V2P_CA9_MPCORE_PERIPH 0x1e000000
+
+#define A9_MPCORE_SCU 0x0000
+#define A9_MPCORE_TWD 0x0600
+
+static struct map_desc v2p_ca9_io_desc[] __initdata = {
+ {
+ .virtual = V2TILE_PERIPH,
+ .pfn = __phys_to_pfn(V2P_CA9_MPCORE_PERIPH),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+ },
+};
+
+#ifdef CONFIG_SMP
+static void v2p_ca9_init_cpu_map(void)
+{
+ int i, ncores = scu_get_core_count(V2TILE_PERIPH_P2V(A9_MPCORE_SCU));
+
+ for (i = 0; i < ncores; ++i)
+ set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
+}
+
+static void v2p_ca9_smp_enable(unsigned int max_cpus)
+{
+ scu_enable(V2TILE_PERIPH_P2V(A9_MPCORE_SCU));
+}
+#endif
+
+static void __init v2p_ca9_map_io(void)
+{
+ v2m_dt_map_io(v2m_memory_map_legacy);
+ iotable_init(v2p_ca9_io_desc, ARRAY_SIZE(v2p_ca9_io_desc));
+#ifdef CONFIG_SMP
+ vexpress_init_cpu_map = v2p_ca9_init_cpu_map;
+ vexpress_smp_enable = v2p_ca9_smp_enable;
+#endif
+}
+
+static void __init v2p_ca9_init_early(void)
+{
+#ifdef CONFIG_LOCAL_TIMERS
+ twd_base = V2TILE_PERIPH_P2V(A9_MPCORE_TWD);
+#endif
+ v2m_dt_init_early();
+}
+
+const static struct of_device_id v2p_ca9_irq_match[] = {
+ { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+ {}
+};
+
+static void __init v2p_ca9_init_irq(void)
+{
+ of_irq_init(v2p_ca9_irq_match);
+}
+
+static void __init v2p_ca9_init(void)
+{
+ l2x0_of_init(0x00400000, 0xfe0fffff);
+ of_platform_populate(NULL, of_default_bus_match_table,
+ v2m_dt_get_auxdata(v2m_memory_map_legacy), NULL);
+}
+
+static const char *v2p_ca9_dt_match[] __initdata = {
+ "arm,vexpress-v2p-ca9",
+ NULL,
+};
+
+DT_MACHINE_START(VEXPRESS_V2P_CA9, "ARM Versatile Express V2P-CA9")
+ .map_io = v2p_ca9_map_io,
+ .init_early = v2p_ca9_init_early,
+ .init_irq = v2p_ca9_init_irq,
+ .timer = &v2m_timer,
+ .init_machine = v2p_ca9_init,
+ .dt_compat = v2p_ca9_dt_match,
+MACHINE_END
--
1.6.3.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 5/6] ARM: vexpress: Initial RS1 memory map support
[not found] ` <1320758169-22668-1-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
` (3 preceding siblings ...)
2011-11-08 13:16 ` [RFC 4/6] ARM: vexpress: DT-based support for Coretile Express A9x4 (V2P-CA9) Pawel Moll
@ 2011-11-08 13:16 ` Pawel Moll
2011-11-08 13:16 ` [RFC 6/6] ARM: vexpress: DT-based support for Coretile Express A5x2 (V2P-CA5s) Pawel Moll
5 siblings, 0 replies; 16+ messages in thread
From: Pawel Moll @ 2011-11-08 13:16 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Pawel Moll
This patch adds support for RS1 memory map based Versatile Express
motherboard. As the RAM location has changed, the ZRE values and
PLAT_PHYS_OFFSET defaults are changed to the new address (all
future tiles will use RS1 map) and enforces AUTO_ZRELADD and
ARM_PATCH_PHYS_VIRT when legacy devices are being used.
Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/mach-vexpress/Kconfig | 5 +++
arch/arm/mach-vexpress/Makefile.boot | 6 ++--
arch/arm/mach-vexpress/core.h | 1 +
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 ++++++++++++++++++--
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +++++++-
arch/arm/mach-vexpress/v2m.c | 29 ++++++++++++++++
6 files changed, 83 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 27c1294..9747125 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -3,6 +3,11 @@ menu "Versatile Express platform type"
config ARCH_VEXPRESS_LEGACY
bool
+ select AUTO_ZRELADDR
+ select ARM_PATCH_PHYS_VIRT
+
+config ARCH_VEXPRESS_RS1
+ bool
config ARCH_VEXPRESS_CA9X4
bool "Versatile Express Cortex-A9x4 tile"
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 8630b3d..3278615 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -1,3 +1,3 @@
- zreladdr-y += 0x60008000
-params_phys-y := 0x60000100
-initrd_phys-y := 0x60800000
+ zreladdr-y += 0x80008000
+params_phys-y := 0x80000100
+initrd_phys-y := 0x80800000
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index 0ea502a..0b5c886 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -33,6 +33,7 @@ extern struct sys_timer v2m_timer;
enum v2m_memory_map {
v2m_memory_map_legacy,
+ v2m_memory_map_rs1,
};
void __init v2m_dt_map_io(enum v2m_memory_map map);
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fd9e6c7..adc94ce 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -10,12 +10,41 @@
* published by the Free Software Foundation.
*/
-#define DEBUG_LL_UART_OFFSET 0x00009000
+#define VEXPRESS_PHYS_BASE_LEGACY 0x10000000
+#define VEXPRESS_UART_OFFSET_LEGACY 0x00009000
+
+#define VEXPRESS_PHYS_BASE_RS1 0x1c000000
+#define VEXPRESS_UART_OFFSET_RS1 0x00090000
+
+#define VEXPRESS_VIRT_BASE 0xf8000000
.macro addruart,rp,rv,tmp
- mov \rp, #DEBUG_LL_UART_OFFSET
- orr \rv, \rp, #0xf8000000 @ virtual base
- orr \rp, \rp, #0x10000000 @ physical base
+
+ @ Check the MMU state
+#if defined(CONFIG_MMU)
+ mrc p15, 0, \tmp, c1, c0 @ SCTRL
+ tst \tmp, #1 @ MMU enabled?
+ moveq \tmp, #VEXPRESS_PHYS_BASE_LEGACY
+ movne \tmp, #VEXPRESS_VIRT_BASE
+#else
+ mov \tmp, #VEXPRESS_PHYS_BASE_LEGACY
+#endif
+
+ @ PL011 present in "legacy place"?
+ orr \tmp, \tmp, #VEXPRESS_UART_OFFSET_LEGACY
+ ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
+ teq \tmp, #0x11 @ PL011
+
+ @ Legacy memory map
+ moveq \rp, #VEXPRESS_UART_OFFSET_LEGACY
+ orreq \rv, \rp, #VEXPRESS_VIRT_BASE
+ orreq \rp, \rp, #VEXPRESS_PHYS_BASE_LEGACY
+
+ @ RS1 memory map
+ movne \rp, #VEXPRESS_UART_OFFSET_RS1
+ orrne \rv, \rp, #VEXPRESS_VIRT_BASE
+ orrne \rp, \rp, #VEXPRESS_PHYS_BASE_RS1
+
.endm
#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7972c57..0ac6ba5 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -22,7 +22,18 @@
#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
-#define get_uart_base() (0x10000000 + 0x00009000)
+#define AMBA_PERIPH_ID0(base) (*(volatile unsigned char *)((base) + 0xfe0))
+
+#define UART_BASE_LEGACY 0x10009000
+#define UART_BASE_RS1 0x1c090000
+
+static unsigned long get_uart_base(void)
+{
+ if (AMBA_PERIPH_ID0(UART_BASE_LEGACY) == 0x11)
+ return UART_BASE_LEGACY;
+ else
+ return UART_BASE_RS1;
+}
/*
* This does not append a newline
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 39900c4..b3bbf43 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -34,6 +34,7 @@
#include "core.h"
+/* Legacy memory map values for non-DT code */
#define V2M_PA_CS0 0x40000000
#define V2M_PA_CS1 0x44000000
#define V2M_PA_CS2 0x48000000
@@ -494,12 +495,24 @@ static unsigned long __init v2m_dt_periph_offset(const char *alias)
return be32_to_cpup(reg);
}
+static struct map_desc v2m_rs1_io_desc[] __initdata = {
+ {
+ .virtual = V2M_PERIPH,
+ .pfn = __phys_to_pfn(0x1c000000),
+ .length = SZ_2M,
+ .type = MT_DEVICE,
+ },
+};
+
void __init v2m_dt_map_io(enum v2m_memory_map map)
{
switch (map) {
case v2m_memory_map_legacy:
iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
break;
+ case v2m_memory_map_rs1:
+ iotable_init(v2m_rs1_io_desc, ARRAY_SIZE(v2m_rs1_io_desc));
+ break;
default:
panic("%s: Unknown memory map requested!\n", __func__);
break;
@@ -533,11 +546,27 @@ static struct of_dev_auxdata v2m_legacy_dt_auxdata_lookup[] __initdata = {
{}
};
+static struct of_dev_auxdata v2m_rs1_dt_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
+ &v2m_flash_data),
+ OF_DEV_AUXDATA("arm,primecell", 0x1c0f0000, "mb:wdt", NULL),
+ OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
+ OF_DEV_AUXDATA("arm,primecell", 0x1c060000, "mb:kmi0", NULL),
+ OF_DEV_AUXDATA("arm,primecell", 0x1c070000, "mb:kmi1", NULL),
+ OF_DEV_AUXDATA("arm,primecell", 0x1c090000, "mb:uart0", NULL),
+ OF_DEV_AUXDATA("arm,primecell", 0x1c0a0000, "mb:uart1", NULL),
+ OF_DEV_AUXDATA("arm,primecell", 0x1c0b0000, "mb:uart2", NULL),
+ OF_DEV_AUXDATA("arm,primecell", 0x1c0c0000, "mb:uart3", NULL),
+ {}
+};
+
struct of_dev_auxdata * __init v2m_dt_get_auxdata(enum v2m_memory_map map)
{
switch (map) {
case v2m_memory_map_legacy:
return v2m_legacy_dt_auxdata_lookup;
+ case v2m_memory_map_rs1:
+ return v2m_rs1_dt_auxdata_lookup;
default:
panic("%s: Unknown memory map requested!\n", __func__);
return NULL;
--
1.6.3.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 6/6] ARM: vexpress: DT-based support for Coretile Express A5x2 (V2P-CA5s)
[not found] ` <1320758169-22668-1-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
` (4 preceding siblings ...)
2011-11-08 13:16 ` [RFC 5/6] ARM: vexpress: Initial RS1 memory map support Pawel Moll
@ 2011-11-08 13:16 ` Pawel Moll
2011-11-08 14:34 ` Rob Herring
5 siblings, 1 reply; 16+ messages in thread
From: Pawel Moll @ 2011-11-08 13:16 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Pawel Moll
This patch adds Device Tree for ARM Ltd. Coretile Express A5x2
used with V2M motherboard and an initial implementation of the
DT machine support.
Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 196 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 121 +++++++++++++++++++
arch/arm/mach-vexpress/Kconfig | 5 +
arch/arm/mach-vexpress/Makefile | 1 +
arch/arm/mach-vexpress/v2p-ca5s.c | 97 +++++++++++++++
5 files changed, 420 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/mach-vexpress/v2p-ca5s.c
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 0000000..dd5fed0
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,196 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * RS1 memory map (a.k.a. ARM Cortex-A Series memory map)
+ */
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ timer01 = &timer01;
+ timer23 = &timer23;
+ sysreg = &sysreg;
+ sysctl = &sysctl;
+ };
+
+ motherboard {
+ compatible = "simple-bus";
+ #address-cells = <2>; /* SMB chipselect number and offset */
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ flash@0,00000000 {
+ compatible = "arm,vexpress-flash", "cfi-flash";
+ reg = <0 0x00000000 0x04000000
+ 4 0x00000000 0x04000000>;
+ bank-width = <4>;
+ };
+
+ psram@1,00000000 {
+ compatible = "mtd-ram";
+ reg = <1 0x00000000 0x02000000>;
+ bank-width = <4>;
+ };
+
+ ethernet@2,02000000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <2 0x02000000 0x10000>;
+ interrupts = <15>;
+ phy-mode = "mii";
+ reg-io-width = <32>;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb@2,03000000 {
+ compatible = "nxp,usb-isp1761";
+ reg = <2 0x03000000 0x20000>;
+ interrupts = <16>;
+ port1-otg;
+ };
+
+ peripherals@3,00000000 {
+ compatible = "arm,amba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 3 0 0x200000>;
+
+ sysreg: sysreg@010000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x010000 0x1000>;
+ };
+
+ sysctl: sysctl@020000 {
+ compatible = "arm,sp810";
+ reg = <0x020000 0x1000>;
+ };
+
+ /* PCI-E I2C bus */
+ i2c0: i2c@030000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x030000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie-switch@60 {
+ compatible = "idt,89hpes32h8";
+ reg = <0x60>;
+ };
+ };
+
+ aaci@040000 {
+ compatible = "arm,pl041", "arm,primecell";
+ reg = <0x040000 0x1000>;
+ interrupts = <11>;
+ };
+
+ mmci@050000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x050000 0x1000>;
+ interrupts = <9 10>;
+ };
+
+ kmi@060000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x060000 0x1000>;
+ interrupts = <12>;
+ };
+
+ kmi@070000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x070000 0x1000>;
+ interrupts = <13>;
+ };
+
+ uart0: uart@090000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x090000 0x1000>;
+ interrupts = <5>;
+ };
+
+ uart1: uart@0a0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0a0000 0x1000>;
+ interrupts = <6>;
+ };
+
+ uart2: uart@0b0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0b0000 0x1000>;
+ interrupts = <7>;
+ };
+
+ uart3: uart@0c0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0c0000 0x1000>;
+ interrupts = <8>;
+ };
+
+ wdt@0f0000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0f0000 0x1000>;
+ interrupts = <0>;
+ };
+
+ timer01: timer@110000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x110000 0x1000>;
+ interrupts = <2>;
+ };
+
+ timer23: timer@120000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x120000 0x1000>;
+ };
+
+ /* DVI I2C bus */
+ i2c1: i2c@160000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x160000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dvi-switch-a@39 {
+ compatible = "sil,sii9022";
+ reg = <0x39>;
+ };
+
+ dvi-switch-b@60 {
+ compatible = "sil,sii9022";
+ reg = <0x60>;
+ };
+ };
+
+ rtc@170000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x170000 0x1000>;
+ interrupts = <4>;
+ };
+
+ compact-flash@1a0000 {
+ compatible = "ata-generic";
+ reg = <0x1a0000 0x100
+ 0x1a0100 0xf00>;
+ reg-shift = <2>;
+ };
+
+ clcd@1f0000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x1f0000 0x1000>;
+ interrupts = <14>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 0000000..2614c75
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,121 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Coretile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA5s";
+ compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
+ interrupt-parent = <&gic>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ hdlcd@2a110000 {
+ compatible = "arm,hdlcd";
+ reg = <0x2a110000 0x1000>;
+ interrupts = <0 85 4>;
+ };
+
+ dmc@2a150000 {
+ compatible = "arm,pl341", "arm,primecell";
+ reg = <0x2a150000 0x1000>;
+ };
+
+ smc@2a190000 {
+ compatible = "arm,pl354", "arm,primecell";
+ reg = <0x2a190000 0x1000>;
+ interrupts = <0 86 4>,
+ <0 87 4>;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x2c001000 0x1000>,
+ <0x2c000100 0x100>;
+ };
+
+ L2: cache-controller@2c0f0000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x2c0f0000 0x1000>;
+ interrupts = <0 84 4>;
+ cache-level = <2>;
+ arm,data-latency = <0>;
+ arm,tag-latency = <0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a5-pmu";
+ interrupts = <0 68 4>,
+ <0 69 4>;
+ };
+
+ motherboard {
+ ranges = <0 0 0x08000000 0x04000000>,
+ <1 0 0x14000000 0x04000000>,
+ <2 0 0x18000000 0x04000000>,
+ <3 0 0x1c000000 0x04000000>,
+ <4 0 0x0c000000 0x04000000>,
+ <5 0 0x10000000 0x04000000>;
+
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 4>,
+ <0 0 1 &gic 0 1 4>,
+ <0 0 2 &gic 0 2 4>,
+ <0 0 3 &gic 0 3 4>,
+ <0 0 4 &gic 0 4 4>,
+ <0 0 5 &gic 0 5 4>,
+ <0 0 6 &gic 0 6 4>,
+ <0 0 7 &gic 0 7 4>,
+ <0 0 8 &gic 0 8 4>,
+ <0 0 9 &gic 0 9 4>,
+ <0 0 10 &gic 0 10 4>,
+ <0 0 11 &gic 0 11 4>,
+ <0 0 12 &gic 0 12 4>,
+ <0 0 13 &gic 0 13 4>,
+ <0 0 14 &gic 0 14 4>,
+ <0 0 15 &gic 0 15 4>,
+ <0 0 16 &gic 0 16 4>,
+ <0 0 17 &gic 0 17 4>,
+ <0 0 18 &gic 0 18 4>,
+ <0 0 19 &gic 0 19 4>,
+ <0 0 20 &gic 0 20 4>,
+ <0 0 21 &gic 0 21 4>,
+ <0 0 22 &gic 0 22 4>,
+ <0 0 23 &gic 0 23 4>,
+ <0 0 24 &gic 0 24 4>,
+ <0 0 25 &gic 0 25 4>,
+ <0 0 26 &gic 0 26 4>,
+ <0 0 27 &gic 0 27 4>,
+ <0 0 28 &gic 0 28 4>,
+ <0 0 29 &gic 0 29 4>,
+ <0 0 30 &gic 0 30 4>,
+ <0 0 31 &gic 0 31 4>,
+ <0 0 32 &gic 0 32 4>,
+ <0 0 33 &gic 0 33 4>,
+ <0 0 34 &gic 0 34 4>,
+ <0 0 35 &gic 0 35 4>,
+ <0 0 36 &gic 0 36 4>,
+ <0 0 37 &gic 0 37 4>,
+ <0 0 38 &gic 0 38 4>,
+ <0 0 39 &gic 0 39 4>,
+ <0 0 40 &gic 0 40 4>,
+ <0 0 41 &gic 0 41 4>,
+ <0 0 42 &gic 0 42 4>;
+ };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 9747125..e5d309e 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -22,6 +22,11 @@ config ARCH_VEXPRESS_DT
bool
select OF
+config ARCH_VEXPRESS_V2P_CA5S
+ bool "CoreTile Express A5x2 (V2P-CA5s) - DT"
+ select ARCH_VEXPRESS_RS1
+ select ARCH_VEXPRESS_DT
+
config ARCH_VEXPRESS_V2P_CA9
bool "CoreTile Express A9x4 (V2P-CA9) - DT"
select ARCH_VEXPRESS_LEGACY
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 9cc4a21..4d37963 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -4,6 +4,7 @@
obj-y := v2m.o
obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
+obj-$(CONFIG_ARCH_VEXPRESS_V2P_CA5S) += v2p-ca5s.o
obj-$(CONFIG_ARCH_VEXPRESS_V2P_CA9) += v2p-ca9.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-vexpress/v2p-ca5s.c b/arch/arm/mach-vexpress/v2p-ca5s.c
new file mode 100644
index 0000000..46eec0c
--- /dev/null
+++ b/arch/arm/mach-vexpress/v2p-ca5s.c
@@ -0,0 +1,97 @@
+/*
+ * Device Tree based support for ARM Versatile Express board
+ * with CoreTile Express A5x2 (V2P-CA5s)
+ */
+
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/smp_scu.h>
+#include <asm/smp_twd.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "core.h"
+
+#define V2P_CA5_MPCORE_PERIPH 0x2c000000
+
+#define A5_MPCORE_SCU 0x0000
+#define A5_MPCORE_TWD 0x0600
+
+static struct map_desc v2p_ca5s_io_desc[] __initdata = {
+ {
+ .virtual = V2TILE_PERIPH,
+ .pfn = __phys_to_pfn(V2P_CA5_MPCORE_PERIPH),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+ },
+};
+
+#ifdef CONFIG_SMP
+static void v2p_ca5s_init_cpu_map(void)
+{
+ int i, ncores = scu_get_core_count(V2TILE_PERIPH_P2V(A5_MPCORE_SCU));
+
+ for (i = 0; i < ncores; ++i)
+ set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
+}
+
+static void v2p_ca5s_smp_enable(unsigned int max_cpus)
+{
+ scu_enable(V2TILE_PERIPH_P2V(A5_MPCORE_SCU));
+}
+#endif
+
+static void __init v2p_ca5s_map_io(void)
+{
+ v2m_dt_map_io(v2m_memory_map_rs1);
+ iotable_init(v2p_ca5s_io_desc, ARRAY_SIZE(v2p_ca5s_io_desc));
+#ifdef CONFIG_SMP
+ vexpress_init_cpu_map = v2p_ca5s_init_cpu_map;
+ vexpress_smp_enable = v2p_ca5s_smp_enable;
+#endif
+}
+
+static void __init v2p_ca5s_init_early(void)
+{
+#ifdef CONFIG_LOCAL_TIMERS
+ twd_base = V2TILE_PERIPH_P2V(A5_MPCORE_TWD);
+#endif
+ v2m_dt_init_early();
+}
+
+const static struct of_device_id v2p_ca5s_irq_match[] = {
+ { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+ {}
+};
+
+static void __init v2p_ca5s_init_irq(void)
+{
+ of_irq_init(v2p_ca5s_irq_match);
+}
+
+static void __init v2p_ca5s_init(void)
+{
+ l2x0_of_init(0x00400000, 0xfe0fffff);
+ of_platform_populate(NULL, of_default_bus_match_table,
+ v2m_dt_get_auxdata(v2m_memory_map_rs1), NULL);
+}
+
+static const char *v2p_ca5s_dt_match[] __initdata = {
+ "arm,vexpress-v2p-ca5s",
+ NULL,
+};
+
+DT_MACHINE_START(VEXPRESS_V2P_CA5, "ARM Versatile Express V2P-CA5s")
+ .map_io = v2p_ca5s_map_io,
+ .init_early = v2p_ca5s_init_early,
+ .init_irq = v2p_ca5s_init_irq,
+ .timer = &v2m_timer,
+ .init_machine = v2p_ca5s_init,
+ .dt_compat = v2p_ca5s_dt_match,
+MACHINE_END
--
1.6.3.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 3/6] ARM: vexpress: Add DT support in v2m
@ 2011-11-08 14:17 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2011-11-08 14:17 UTC (permalink / raw)
To: linux-arm-kernel
On 11/08/2011 07:16 AM, Pawel Moll wrote:
> This patch provides hooks for DT-based tile machine implementations.
>
> Signed-off-by: Pawel Moll <pawel.moll@arm.com>
> ---
> arch/arm/mach-vexpress/Kconfig | 8 ++++
> arch/arm/mach-vexpress/core.h | 13 +++++++
> arch/arm/mach-vexpress/v2m.c | 79 +++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 99 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index 9311484..9370f5b 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -1,6 +1,9 @@
> menu "Versatile Express platform type"
> depends on ARCH_VEXPRESS
>
> +config ARCH_VEXPRESS_LEGACY
> + bool
> +
> config ARCH_VEXPRESS_CA9X4
> bool "Versatile Express Cortex-A9x4 tile"
> select CPU_V7
> @@ -8,5 +11,10 @@ config ARCH_VEXPRESS_CA9X4
> select ARM_ERRATA_720789
> select ARM_ERRATA_751472
> select ARM_ERRATA_753970
> + select ARCH_VEXPRESS_LEGACY
> +
> +config ARCH_VEXPRESS_DT
> + bool
> + select OF
>
> endmenu
> diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
> index 7a3ce7a..0ea502a 100644
> --- a/arch/arm/mach-vexpress/core.h
> +++ b/arch/arm/mach-vexpress/core.h
> @@ -27,3 +27,16 @@ extern void (*vexpress_init_cpu_map)(void);
> extern void (*vexpress_smp_enable)(unsigned int);
> #endif
>
> +extern struct sys_timer v2m_timer;
> +
> +#if defined(CONFIG_ARCH_VEXPRESS_DT)
> +
> +enum v2m_memory_map {
> + v2m_memory_map_legacy,
> +};
> +
> +void __init v2m_dt_map_io(enum v2m_memory_map map);
> +void __init v2m_dt_init_early(void);
> +struct of_dev_auxdata * __init v2m_dt_get_auxdata(enum v2m_memory_map map);
> +
> +#endif
> diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
> index 2f44425..39900c4 100644
> --- a/arch/arm/mach-vexpress/v2m.c
> +++ b/arch/arm/mach-vexpress/v2m.c
> @@ -6,6 +6,9 @@
> #include <linux/amba/mmci.h>
> #include <linux/io.h>
> #include <linux/init.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of_fdt.h>
> +#include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/ata_platform.h>
> #include <linux/smsc911x.h>
> @@ -70,7 +73,8 @@ static void __init v2m_timer_init(void)
> "v2m-timer0");
> }
>
> -static struct sys_timer v2m_timer = {
> +/* May be used by DT-powered machines */
> +struct sys_timer v2m_timer = {
> .init = v2m_timer_init,
> };
>
> @@ -468,3 +472,76 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
> .timer = &v2m_timer,
> .init_machine = v2m_init,
> MACHINE_END
> +
> +
> +
> +#if defined(CONFIG_ARCH_VEXPRESS_DT)
> +
> +static unsigned long __init v2m_dt_periph_offset(const char *alias)
> +{
> + unsigned long node;
> + __be32 *reg;
> + unsigned long len;
> +
> + if (of_flat_dt_find_node_by_alias(alias, &node) != 0)
> + panic("%s: Can't get offset for '%s'!\n", __func__, alias);
> +
> + reg = of_get_flat_dt_prop(node, "reg", &len);
> + if (!reg)
> + panic("%s: Can't get reg property for '%s'!\n",
> + __func__, alias);
> +
> + return be32_to_cpup(reg);
> +}
> +
> +void __init v2m_dt_map_io(enum v2m_memory_map map)
> +{
> + switch (map) {
> + case v2m_memory_map_legacy:
> + iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
> + break;
> + default:
> + panic("%s: Unknown memory map requested!\n", __func__);
> + break;
I don't like this approach. Why don't you either have 2 DT machine_descs
for legacy and new memory map or use the machine compatible strings to
select the io table.
> + }
> +
> + /* Will become nice ioremap()-s once allowed */
> + v2m_sysreg_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("sysreg"));
> + v2m_sysctl_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("sysctl"));
> + v2m_timer01_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("timer01"));
Generally, timers can be ioremapped already.
> +}
> +
> +void __init v2m_dt_init_early(void)
> +{
> + clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
> + versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
> + pm_power_off = v2m_power_off;
> + arm_pm_restart = v2m_restart;
> +}
> +
> +static struct of_dev_auxdata v2m_legacy_dt_auxdata_lookup[] __initdata = {
> + OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
> + &v2m_flash_data),
> + OF_DEV_AUXDATA("arm,primecell", V2M_WDT, "mb:wdt", NULL),
> + OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
> + OF_DEV_AUXDATA("arm,primecell", V2M_KMI0, "mb:kmi0", NULL),
> + OF_DEV_AUXDATA("arm,primecell", V2M_KMI1, "mb:kmi1", NULL),
> + OF_DEV_AUXDATA("arm,primecell", V2M_UART0, "mb:uart0", NULL),
> + OF_DEV_AUXDATA("arm,primecell", V2M_UART1, "mb:uart1", NULL),
> + OF_DEV_AUXDATA("arm,primecell", V2M_UART2, "mb:uart2", NULL),
> + OF_DEV_AUXDATA("arm,primecell", V2M_UART3, "mb:uart3", NULL),
You are only adding platform_data in 2 cases, so that probably means the
rest are for clkdev lookups. You can just add the lookups directly.
> + {}
> +};
> +
> +struct of_dev_auxdata * __init v2m_dt_get_auxdata(enum v2m_memory_map map)
> +{
> + switch (map) {
> + case v2m_memory_map_legacy:
> + return v2m_legacy_dt_auxdata_lookup;
Because auxdata is matched against addresses, you can just put all
entries into 1 table for both legacy and new memory map.
Rob
> + default:
> + panic("%s: Unknown memory map requested!\n", __func__);
> + return NULL;
> + }
> +}
> +
> +#endif
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 3/6] ARM: vexpress: Add DT support in v2m
@ 2011-11-08 14:17 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2011-11-08 14:17 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 11/08/2011 07:16 AM, Pawel Moll wrote:
> This patch provides hooks for DT-based tile machine implementations.
>
> Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm/mach-vexpress/Kconfig | 8 ++++
> arch/arm/mach-vexpress/core.h | 13 +++++++
> arch/arm/mach-vexpress/v2m.c | 79 +++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 99 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index 9311484..9370f5b 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -1,6 +1,9 @@
> menu "Versatile Express platform type"
> depends on ARCH_VEXPRESS
>
> +config ARCH_VEXPRESS_LEGACY
> + bool
> +
> config ARCH_VEXPRESS_CA9X4
> bool "Versatile Express Cortex-A9x4 tile"
> select CPU_V7
> @@ -8,5 +11,10 @@ config ARCH_VEXPRESS_CA9X4
> select ARM_ERRATA_720789
> select ARM_ERRATA_751472
> select ARM_ERRATA_753970
> + select ARCH_VEXPRESS_LEGACY
> +
> +config ARCH_VEXPRESS_DT
> + bool
> + select OF
>
> endmenu
> diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
> index 7a3ce7a..0ea502a 100644
> --- a/arch/arm/mach-vexpress/core.h
> +++ b/arch/arm/mach-vexpress/core.h
> @@ -27,3 +27,16 @@ extern void (*vexpress_init_cpu_map)(void);
> extern void (*vexpress_smp_enable)(unsigned int);
> #endif
>
> +extern struct sys_timer v2m_timer;
> +
> +#if defined(CONFIG_ARCH_VEXPRESS_DT)
> +
> +enum v2m_memory_map {
> + v2m_memory_map_legacy,
> +};
> +
> +void __init v2m_dt_map_io(enum v2m_memory_map map);
> +void __init v2m_dt_init_early(void);
> +struct of_dev_auxdata * __init v2m_dt_get_auxdata(enum v2m_memory_map map);
> +
> +#endif
> diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
> index 2f44425..39900c4 100644
> --- a/arch/arm/mach-vexpress/v2m.c
> +++ b/arch/arm/mach-vexpress/v2m.c
> @@ -6,6 +6,9 @@
> #include <linux/amba/mmci.h>
> #include <linux/io.h>
> #include <linux/init.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of_fdt.h>
> +#include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/ata_platform.h>
> #include <linux/smsc911x.h>
> @@ -70,7 +73,8 @@ static void __init v2m_timer_init(void)
> "v2m-timer0");
> }
>
> -static struct sys_timer v2m_timer = {
> +/* May be used by DT-powered machines */
> +struct sys_timer v2m_timer = {
> .init = v2m_timer_init,
> };
>
> @@ -468,3 +472,76 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
> .timer = &v2m_timer,
> .init_machine = v2m_init,
> MACHINE_END
> +
> +
> +
> +#if defined(CONFIG_ARCH_VEXPRESS_DT)
> +
> +static unsigned long __init v2m_dt_periph_offset(const char *alias)
> +{
> + unsigned long node;
> + __be32 *reg;
> + unsigned long len;
> +
> + if (of_flat_dt_find_node_by_alias(alias, &node) != 0)
> + panic("%s: Can't get offset for '%s'!\n", __func__, alias);
> +
> + reg = of_get_flat_dt_prop(node, "reg", &len);
> + if (!reg)
> + panic("%s: Can't get reg property for '%s'!\n",
> + __func__, alias);
> +
> + return be32_to_cpup(reg);
> +}
> +
> +void __init v2m_dt_map_io(enum v2m_memory_map map)
> +{
> + switch (map) {
> + case v2m_memory_map_legacy:
> + iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
> + break;
> + default:
> + panic("%s: Unknown memory map requested!\n", __func__);
> + break;
I don't like this approach. Why don't you either have 2 DT machine_descs
for legacy and new memory map or use the machine compatible strings to
select the io table.
> + }
> +
> + /* Will become nice ioremap()-s once allowed */
> + v2m_sysreg_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("sysreg"));
> + v2m_sysctl_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("sysctl"));
> + v2m_timer01_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("timer01"));
Generally, timers can be ioremapped already.
> +}
> +
> +void __init v2m_dt_init_early(void)
> +{
> + clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
> + versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
> + pm_power_off = v2m_power_off;
> + arm_pm_restart = v2m_restart;
> +}
> +
> +static struct of_dev_auxdata v2m_legacy_dt_auxdata_lookup[] __initdata = {
> + OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
> + &v2m_flash_data),
> + OF_DEV_AUXDATA("arm,primecell", V2M_WDT, "mb:wdt", NULL),
> + OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
> + OF_DEV_AUXDATA("arm,primecell", V2M_KMI0, "mb:kmi0", NULL),
> + OF_DEV_AUXDATA("arm,primecell", V2M_KMI1, "mb:kmi1", NULL),
> + OF_DEV_AUXDATA("arm,primecell", V2M_UART0, "mb:uart0", NULL),
> + OF_DEV_AUXDATA("arm,primecell", V2M_UART1, "mb:uart1", NULL),
> + OF_DEV_AUXDATA("arm,primecell", V2M_UART2, "mb:uart2", NULL),
> + OF_DEV_AUXDATA("arm,primecell", V2M_UART3, "mb:uart3", NULL),
You are only adding platform_data in 2 cases, so that probably means the
rest are for clkdev lookups. You can just add the lookups directly.
> + {}
> +};
> +
> +struct of_dev_auxdata * __init v2m_dt_get_auxdata(enum v2m_memory_map map)
> +{
> + switch (map) {
> + case v2m_memory_map_legacy:
> + return v2m_legacy_dt_auxdata_lookup;
Because auxdata is matched against addresses, you can just put all
entries into 1 table for both legacy and new memory map.
Rob
> + default:
> + panic("%s: Unknown memory map requested!\n", __func__);
> + return NULL;
> + }
> +}
> +
> +#endif
^ permalink raw reply [flat|nested] 16+ messages in thread
* [RFC 6/6] ARM: vexpress: DT-based support for Coretile Express A5x2 (V2P-CA5s)
@ 2011-11-08 14:34 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2011-11-08 14:34 UTC (permalink / raw)
To: linux-arm-kernel
On 11/08/2011 07:16 AM, Pawel Moll wrote:
> This patch adds Device Tree for ARM Ltd. Coretile Express A5x2
> used with V2M motherboard and an initial implementation of the
> DT machine support.
>
> Signed-off-by: Pawel Moll <pawel.moll@arm.com>
> ---
> arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 196 +++++++++++++++++++++++++++++++
> arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 121 +++++++++++++++++++
> arch/arm/mach-vexpress/Kconfig | 5 +
> arch/arm/mach-vexpress/Makefile | 1 +
> arch/arm/mach-vexpress/v2p-ca5s.c | 97 +++++++++++++++
I really think v2p-ca5s.c and v2p-ca9.c should be combined into 1 file.
There's a lot of duplication and the parts that are different can go in
the DT.
> 5 files changed, 420 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
> create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> create mode 100644 arch/arm/mach-vexpress/v2p-ca5s.c
>
> diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
> new file mode 100644
> index 0000000..dd5fed0
> --- /dev/null
> +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
> @@ -0,0 +1,196 @@
> +/*
> + * ARM Ltd. Versatile Express
> + *
> + * Motherboard Express uATX
> + * V2M-P1
> + *
> + * HBI-0190D
> + *
> + * RS1 memory map (a.k.a. ARM Cortex-A Series memory map)
> + */
> +
> +/ {
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + timer01 = &timer01;
> + timer23 = &timer23;
> + sysreg = &sysreg;
> + sysctl = &sysctl;
> + };
> +
> + motherboard {
> + compatible = "simple-bus";
> + #address-cells = <2>; /* SMB chipselect number and offset */
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + flash at 0,00000000 {
> + compatible = "arm,vexpress-flash", "cfi-flash";
> + reg = <0 0x00000000 0x04000000
> + 4 0x00000000 0x04000000>;
> + bank-width = <4>;
> + };
> +
> + psram at 1,00000000 {
> + compatible = "mtd-ram";
> + reg = <1 0x00000000 0x02000000>;
> + bank-width = <4>;
> + };
> +
> + ethernet at 2,02000000 {
> + compatible = "smsc,lan9118", "smsc,lan9115";
> + reg = <2 0x02000000 0x10000>;
> + interrupts = <15>;
> + phy-mode = "mii";
> + reg-io-width = <32>;
> + smsc,irq-active-high;
> + smsc,irq-push-pull;
> + };
> +
> + usb at 2,03000000 {
> + compatible = "nxp,usb-isp1761";
> + reg = <2 0x03000000 0x20000>;
> + interrupts = <16>;
> + port1-otg;
> + };
> +
> + peripherals at 3,00000000 {
> + compatible = "arm,amba-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 3 0 0x200000>;
> +
> + sysreg: sysreg at 010000 {
> + compatible = "arm,vexpress-sysreg";
> + reg = <0x010000 0x1000>;
> + };
> +
> + sysctl: sysctl at 020000 {
> + compatible = "arm,sp810";
> + reg = <0x020000 0x1000>;
> + };
> +
> + /* PCI-E I2C bus */
> + i2c0: i2c at 030000 {
> + compatible = "arm,versatile-i2c";
> + reg = <0x030000 0x1000>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pcie-switch at 60 {
> + compatible = "idt,89hpes32h8";
> + reg = <0x60>;
> + };
> + };
> +
> + aaci at 040000 {
> + compatible = "arm,pl041", "arm,primecell";
> + reg = <0x040000 0x1000>;
> + interrupts = <11>;
> + };
> +
> + mmci at 050000 {
> + compatible = "arm,pl180", "arm,primecell";
> + reg = <0x050000 0x1000>;
> + interrupts = <9 10>;
> + };
> +
> + kmi at 060000 {
> + compatible = "arm,pl050", "arm,primecell";
> + reg = <0x060000 0x1000>;
> + interrupts = <12>;
> + };
> +
> + kmi at 070000 {
> + compatible = "arm,pl050", "arm,primecell";
> + reg = <0x070000 0x1000>;
> + interrupts = <13>;
> + };
> +
> + uart0: uart at 090000 {
Use generic names:
s/uart/serial/
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x090000 0x1000>;
> + interrupts = <5>;
> + };
> +
> + uart1: uart at 0a0000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0a0000 0x1000>;
> + interrupts = <6>;
> + };
> +
> + uart2: uart at 0b0000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0b0000 0x1000>;
> + interrupts = <7>;
> + };
> +
> + uart3: uart at 0c0000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0c0000 0x1000>;
> + interrupts = <8>;
> + };
> +
> + wdt at 0f0000 {
> + compatible = "arm,sp805", "arm,primecell";
> + reg = <0x0f0000 0x1000>;
> + interrupts = <0>;
> + };
> +
> + timer01: timer at 110000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x110000 0x1000>;
> + interrupts = <2>;
> + };
> +
> + timer23: timer at 120000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x120000 0x1000>;
> + };
> +
> + /* DVI I2C bus */
> + i2c1: i2c at 160000 {
> + compatible = "arm,versatile-i2c";
> + reg = <0x160000 0x1000>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dvi-switch-a at 39 {
> + compatible = "sil,sii9022";
> + reg = <0x39>;
> + };
> +
> + dvi-switch-b at 60 {
> + compatible = "sil,sii9022";
> + reg = <0x60>;
> + };
> + };
> +
> + rtc at 170000 {
> + compatible = "arm,pl031", "arm,primecell";
> + reg = <0x170000 0x1000>;
> + interrupts = <4>;
> + };
> +
> + compact-flash at 1a0000 {
> + compatible = "ata-generic";
> + reg = <0x1a0000 0x100
> + 0x1a0100 0xf00>;
> + reg-shift = <2>;
> + };
> +
> + clcd at 1f0000 {
> + compatible = "arm,pl111", "arm,primecell";
> + reg = <0x1f0000 0x1000>;
> + interrupts = <14>;
> + };
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> new file mode 100644
> index 0000000..2614c75
> --- /dev/null
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> @@ -0,0 +1,121 @@
> +/*
> + * ARM Ltd. Versatile Express
> + *
> + * Coretile Express A5x2
> + * Cortex-A5 MPCore (V2P-CA5s)
> + *
> + * HBI-0225B
> + */
> +
> +/dts-v1/;
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + model = "V2P-CA5s";
> + compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
> + interrupt-parent = <&gic>;
> +
> + memory {
memory at 80000000
> + device_type = "memory";
> + reg = <0x80000000 0x40000000>;
> + };
> +
> + hdlcd at 2a110000 {
> + compatible = "arm,hdlcd";
> + reg = <0x2a110000 0x1000>;
> + interrupts = <0 85 4>;
> + };
> +
> + dmc at 2a150000 {
> + compatible = "arm,pl341", "arm,primecell";
> + reg = <0x2a150000 0x1000>;
> + };
> +
> + smc at 2a190000 {
> + compatible = "arm,pl354", "arm,primecell";
> + reg = <0x2a190000 0x1000>;
> + interrupts = <0 86 4>,
> + <0 87 4>;
> + };
> +
> + gic: interrupt-controller at 2c001000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x2c001000 0x1000>,
> + <0x2c000100 0x100>;
> + };
> +
> + L2: cache-controller at 2c0f0000 {
> + compatible = "arm,pl310-cache";
> + reg = <0x2c0f0000 0x1000>;
> + interrupts = <0 84 4>;
> + cache-level = <2>;
> + arm,data-latency = <0>;
> + arm,tag-latency = <0>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a5-pmu";
> + interrupts = <0 68 4>,
> + <0 69 4>;
> + };
> +
> + motherboard {
> + ranges = <0 0 0x08000000 0x04000000>,
> + <1 0 0x14000000 0x04000000>,
> + <2 0 0x18000000 0x04000000>,
> + <3 0 0x1c000000 0x04000000>,
> + <4 0 0x0c000000 0x04000000>,
> + <5 0 0x10000000 0x04000000>;
> +
> + interrupt-map-mask = <0 0 63>;
> + interrupt-map = <0 0 0 &gic 0 0 4>,
> + <0 0 1 &gic 0 1 4>,
> + <0 0 2 &gic 0 2 4>,
> + <0 0 3 &gic 0 3 4>,
> + <0 0 4 &gic 0 4 4>,
> + <0 0 5 &gic 0 5 4>,
> + <0 0 6 &gic 0 6 4>,
> + <0 0 7 &gic 0 7 4>,
> + <0 0 8 &gic 0 8 4>,
> + <0 0 9 &gic 0 9 4>,
> + <0 0 10 &gic 0 10 4>,
> + <0 0 11 &gic 0 11 4>,
> + <0 0 12 &gic 0 12 4>,
> + <0 0 13 &gic 0 13 4>,
> + <0 0 14 &gic 0 14 4>,
> + <0 0 15 &gic 0 15 4>,
> + <0 0 16 &gic 0 16 4>,
> + <0 0 17 &gic 0 17 4>,
> + <0 0 18 &gic 0 18 4>,
> + <0 0 19 &gic 0 19 4>,
> + <0 0 20 &gic 0 20 4>,
> + <0 0 21 &gic 0 21 4>,
> + <0 0 22 &gic 0 22 4>,
> + <0 0 23 &gic 0 23 4>,
> + <0 0 24 &gic 0 24 4>,
> + <0 0 25 &gic 0 25 4>,
> + <0 0 26 &gic 0 26 4>,
> + <0 0 27 &gic 0 27 4>,
> + <0 0 28 &gic 0 28 4>,
> + <0 0 29 &gic 0 29 4>,
> + <0 0 30 &gic 0 30 4>,
> + <0 0 31 &gic 0 31 4>,
> + <0 0 32 &gic 0 32 4>,
> + <0 0 33 &gic 0 33 4>,
> + <0 0 34 &gic 0 34 4>,
> + <0 0 35 &gic 0 35 4>,
> + <0 0 36 &gic 0 36 4>,
> + <0 0 37 &gic 0 37 4>,
> + <0 0 38 &gic 0 38 4>,
> + <0 0 39 &gic 0 39 4>,
> + <0 0 40 &gic 0 40 4>,
> + <0 0 41 &gic 0 41 4>,
> + <0 0 42 &gic 0 42 4>;
> + };
> +};
> +
> +/include/ "vexpress-v2m-rs1.dtsi"
> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index 9747125..e5d309e 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -22,6 +22,11 @@ config ARCH_VEXPRESS_DT
> bool
> select OF
>
> +config ARCH_VEXPRESS_V2P_CA5S
> + bool "CoreTile Express A5x2 (V2P-CA5s) - DT"
> + select ARCH_VEXPRESS_RS1
> + select ARCH_VEXPRESS_DT
> +
> config ARCH_VEXPRESS_V2P_CA9
> bool "CoreTile Express A9x4 (V2P-CA9) - DT"
> select ARCH_VEXPRESS_LEGACY
> diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
> index 9cc4a21..4d37963 100644
> --- a/arch/arm/mach-vexpress/Makefile
> +++ b/arch/arm/mach-vexpress/Makefile
> @@ -4,6 +4,7 @@
>
> obj-y := v2m.o
> obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
> +obj-$(CONFIG_ARCH_VEXPRESS_V2P_CA5S) += v2p-ca5s.o
> obj-$(CONFIG_ARCH_VEXPRESS_V2P_CA9) += v2p-ca9.o
> obj-$(CONFIG_SMP) += platsmp.o
> obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
> diff --git a/arch/arm/mach-vexpress/v2p-ca5s.c b/arch/arm/mach-vexpress/v2p-ca5s.c
> new file mode 100644
> index 0000000..46eec0c
> --- /dev/null
> +++ b/arch/arm/mach-vexpress/v2p-ca5s.c
> @@ -0,0 +1,97 @@
> +/*
> + * Device Tree based support for ARM Versatile Express board
> + * with CoreTile Express A5x2 (V2P-CA5s)
> + */
> +
> +#include <linux/init.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/smp_scu.h>
> +#include <asm/smp_twd.h>
> +#include <asm/hardware/cache-l2x0.h>
> +#include <asm/hardware/gic.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/map.h>
> +
> +#include "core.h"
> +
> +#define V2P_CA5_MPCORE_PERIPH 0x2c000000
> +
> +#define A5_MPCORE_SCU 0x0000
> +#define A5_MPCORE_TWD 0x0600
> +
> +static struct map_desc v2p_ca5s_io_desc[] __initdata = {
> + {
> + .virtual = V2TILE_PERIPH,
> + .pfn = __phys_to_pfn(V2P_CA5_MPCORE_PERIPH),
> + .length = SZ_8K,
> + .type = MT_DEVICE,
> + },
> +};
> +
> +#ifdef CONFIG_SMP
> +static void v2p_ca5s_init_cpu_map(void)
> +{
> + int i, ncores = scu_get_core_count(V2TILE_PERIPH_P2V(A5_MPCORE_SCU));
This works on A9, does it work on A5? If not, an SCU binding should be
created.
/* Get SCU base */
asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
> +
> + for (i = 0; i < ncores; ++i)
> + set_cpu_possible(i, true);
> +
> + set_smp_cross_call(gic_raise_softirq);
> +}
> +
> +static void v2p_ca5s_smp_enable(unsigned int max_cpus)
> +{
> + scu_enable(V2TILE_PERIPH_P2V(A5_MPCORE_SCU));
> +}
> +#endif
> +
> +static void __init v2p_ca5s_map_io(void)
> +{
> + v2m_dt_map_io(v2m_memory_map_rs1);
> + iotable_init(v2p_ca5s_io_desc, ARRAY_SIZE(v2p_ca5s_io_desc));
> +#ifdef CONFIG_SMP
> + vexpress_init_cpu_map = v2p_ca5s_init_cpu_map;
> + vexpress_smp_enable = v2p_ca5s_smp_enable;
> +#endif
> +}
> +
> +static void __init v2p_ca5s_init_early(void)
> +{
> +#ifdef CONFIG_LOCAL_TIMERS
> + twd_base = V2TILE_PERIPH_P2V(A5_MPCORE_TWD);
> +#endif
> + v2m_dt_init_early();
> +}
> +
> +const static struct of_device_id v2p_ca5s_irq_match[] = {
> + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
> + {}
> +};
> +
> +static void __init v2p_ca5s_init_irq(void)
> +{
> + of_irq_init(v2p_ca5s_irq_match);
> +}
> +
> +static void __init v2p_ca5s_init(void)
> +{
> + l2x0_of_init(0x00400000, 0xfe0fffff);
> + of_platform_populate(NULL, of_default_bus_match_table,
> + v2m_dt_get_auxdata(v2m_memory_map_rs1), NULL);
> +}
> +
> +static const char *v2p_ca5s_dt_match[] __initdata = {
> + "arm,vexpress-v2p-ca5s",
> + NULL,
> +};
> +
> +DT_MACHINE_START(VEXPRESS_V2P_CA5, "ARM Versatile Express V2P-CA5s")
> + .map_io = v2p_ca5s_map_io,
> + .init_early = v2p_ca5s_init_early,
> + .init_irq = v2p_ca5s_init_irq,
> + .timer = &v2m_timer,
> + .init_machine = v2p_ca5s_init,
> + .dt_compat = v2p_ca5s_dt_match,
> +MACHINE_END
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 6/6] ARM: vexpress: DT-based support for Coretile Express A5x2 (V2P-CA5s)
@ 2011-11-08 14:34 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2011-11-08 14:34 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 11/08/2011 07:16 AM, Pawel Moll wrote:
> This patch adds Device Tree for ARM Ltd. Coretile Express A5x2
> used with V2M motherboard and an initial implementation of the
> DT machine support.
>
> Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 196 +++++++++++++++++++++++++++++++
> arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 121 +++++++++++++++++++
> arch/arm/mach-vexpress/Kconfig | 5 +
> arch/arm/mach-vexpress/Makefile | 1 +
> arch/arm/mach-vexpress/v2p-ca5s.c | 97 +++++++++++++++
I really think v2p-ca5s.c and v2p-ca9.c should be combined into 1 file.
There's a lot of duplication and the parts that are different can go in
the DT.
> 5 files changed, 420 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
> create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> create mode 100644 arch/arm/mach-vexpress/v2p-ca5s.c
>
> diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
> new file mode 100644
> index 0000000..dd5fed0
> --- /dev/null
> +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
> @@ -0,0 +1,196 @@
> +/*
> + * ARM Ltd. Versatile Express
> + *
> + * Motherboard Express uATX
> + * V2M-P1
> + *
> + * HBI-0190D
> + *
> + * RS1 memory map (a.k.a. ARM Cortex-A Series memory map)
> + */
> +
> +/ {
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + timer01 = &timer01;
> + timer23 = &timer23;
> + sysreg = &sysreg;
> + sysctl = &sysctl;
> + };
> +
> + motherboard {
> + compatible = "simple-bus";
> + #address-cells = <2>; /* SMB chipselect number and offset */
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + flash@0,00000000 {
> + compatible = "arm,vexpress-flash", "cfi-flash";
> + reg = <0 0x00000000 0x04000000
> + 4 0x00000000 0x04000000>;
> + bank-width = <4>;
> + };
> +
> + psram@1,00000000 {
> + compatible = "mtd-ram";
> + reg = <1 0x00000000 0x02000000>;
> + bank-width = <4>;
> + };
> +
> + ethernet@2,02000000 {
> + compatible = "smsc,lan9118", "smsc,lan9115";
> + reg = <2 0x02000000 0x10000>;
> + interrupts = <15>;
> + phy-mode = "mii";
> + reg-io-width = <32>;
> + smsc,irq-active-high;
> + smsc,irq-push-pull;
> + };
> +
> + usb@2,03000000 {
> + compatible = "nxp,usb-isp1761";
> + reg = <2 0x03000000 0x20000>;
> + interrupts = <16>;
> + port1-otg;
> + };
> +
> + peripherals@3,00000000 {
> + compatible = "arm,amba-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 3 0 0x200000>;
> +
> + sysreg: sysreg@010000 {
> + compatible = "arm,vexpress-sysreg";
> + reg = <0x010000 0x1000>;
> + };
> +
> + sysctl: sysctl@020000 {
> + compatible = "arm,sp810";
> + reg = <0x020000 0x1000>;
> + };
> +
> + /* PCI-E I2C bus */
> + i2c0: i2c@030000 {
> + compatible = "arm,versatile-i2c";
> + reg = <0x030000 0x1000>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pcie-switch@60 {
> + compatible = "idt,89hpes32h8";
> + reg = <0x60>;
> + };
> + };
> +
> + aaci@040000 {
> + compatible = "arm,pl041", "arm,primecell";
> + reg = <0x040000 0x1000>;
> + interrupts = <11>;
> + };
> +
> + mmci@050000 {
> + compatible = "arm,pl180", "arm,primecell";
> + reg = <0x050000 0x1000>;
> + interrupts = <9 10>;
> + };
> +
> + kmi@060000 {
> + compatible = "arm,pl050", "arm,primecell";
> + reg = <0x060000 0x1000>;
> + interrupts = <12>;
> + };
> +
> + kmi@070000 {
> + compatible = "arm,pl050", "arm,primecell";
> + reg = <0x070000 0x1000>;
> + interrupts = <13>;
> + };
> +
> + uart0: uart@090000 {
Use generic names:
s/uart/serial/
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x090000 0x1000>;
> + interrupts = <5>;
> + };
> +
> + uart1: uart@0a0000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0a0000 0x1000>;
> + interrupts = <6>;
> + };
> +
> + uart2: uart@0b0000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0b0000 0x1000>;
> + interrupts = <7>;
> + };
> +
> + uart3: uart@0c0000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0c0000 0x1000>;
> + interrupts = <8>;
> + };
> +
> + wdt@0f0000 {
> + compatible = "arm,sp805", "arm,primecell";
> + reg = <0x0f0000 0x1000>;
> + interrupts = <0>;
> + };
> +
> + timer01: timer@110000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x110000 0x1000>;
> + interrupts = <2>;
> + };
> +
> + timer23: timer@120000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x120000 0x1000>;
> + };
> +
> + /* DVI I2C bus */
> + i2c1: i2c@160000 {
> + compatible = "arm,versatile-i2c";
> + reg = <0x160000 0x1000>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dvi-switch-a@39 {
> + compatible = "sil,sii9022";
> + reg = <0x39>;
> + };
> +
> + dvi-switch-b@60 {
> + compatible = "sil,sii9022";
> + reg = <0x60>;
> + };
> + };
> +
> + rtc@170000 {
> + compatible = "arm,pl031", "arm,primecell";
> + reg = <0x170000 0x1000>;
> + interrupts = <4>;
> + };
> +
> + compact-flash@1a0000 {
> + compatible = "ata-generic";
> + reg = <0x1a0000 0x100
> + 0x1a0100 0xf00>;
> + reg-shift = <2>;
> + };
> +
> + clcd@1f0000 {
> + compatible = "arm,pl111", "arm,primecell";
> + reg = <0x1f0000 0x1000>;
> + interrupts = <14>;
> + };
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> new file mode 100644
> index 0000000..2614c75
> --- /dev/null
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> @@ -0,0 +1,121 @@
> +/*
> + * ARM Ltd. Versatile Express
> + *
> + * Coretile Express A5x2
> + * Cortex-A5 MPCore (V2P-CA5s)
> + *
> + * HBI-0225B
> + */
> +
> +/dts-v1/;
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + model = "V2P-CA5s";
> + compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
> + interrupt-parent = <&gic>;
> +
> + memory {
memory@80000000
> + device_type = "memory";
> + reg = <0x80000000 0x40000000>;
> + };
> +
> + hdlcd@2a110000 {
> + compatible = "arm,hdlcd";
> + reg = <0x2a110000 0x1000>;
> + interrupts = <0 85 4>;
> + };
> +
> + dmc@2a150000 {
> + compatible = "arm,pl341", "arm,primecell";
> + reg = <0x2a150000 0x1000>;
> + };
> +
> + smc@2a190000 {
> + compatible = "arm,pl354", "arm,primecell";
> + reg = <0x2a190000 0x1000>;
> + interrupts = <0 86 4>,
> + <0 87 4>;
> + };
> +
> + gic: interrupt-controller@2c001000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x2c001000 0x1000>,
> + <0x2c000100 0x100>;
> + };
> +
> + L2: cache-controller@2c0f0000 {
> + compatible = "arm,pl310-cache";
> + reg = <0x2c0f0000 0x1000>;
> + interrupts = <0 84 4>;
> + cache-level = <2>;
> + arm,data-latency = <0>;
> + arm,tag-latency = <0>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a5-pmu";
> + interrupts = <0 68 4>,
> + <0 69 4>;
> + };
> +
> + motherboard {
> + ranges = <0 0 0x08000000 0x04000000>,
> + <1 0 0x14000000 0x04000000>,
> + <2 0 0x18000000 0x04000000>,
> + <3 0 0x1c000000 0x04000000>,
> + <4 0 0x0c000000 0x04000000>,
> + <5 0 0x10000000 0x04000000>;
> +
> + interrupt-map-mask = <0 0 63>;
> + interrupt-map = <0 0 0 &gic 0 0 4>,
> + <0 0 1 &gic 0 1 4>,
> + <0 0 2 &gic 0 2 4>,
> + <0 0 3 &gic 0 3 4>,
> + <0 0 4 &gic 0 4 4>,
> + <0 0 5 &gic 0 5 4>,
> + <0 0 6 &gic 0 6 4>,
> + <0 0 7 &gic 0 7 4>,
> + <0 0 8 &gic 0 8 4>,
> + <0 0 9 &gic 0 9 4>,
> + <0 0 10 &gic 0 10 4>,
> + <0 0 11 &gic 0 11 4>,
> + <0 0 12 &gic 0 12 4>,
> + <0 0 13 &gic 0 13 4>,
> + <0 0 14 &gic 0 14 4>,
> + <0 0 15 &gic 0 15 4>,
> + <0 0 16 &gic 0 16 4>,
> + <0 0 17 &gic 0 17 4>,
> + <0 0 18 &gic 0 18 4>,
> + <0 0 19 &gic 0 19 4>,
> + <0 0 20 &gic 0 20 4>,
> + <0 0 21 &gic 0 21 4>,
> + <0 0 22 &gic 0 22 4>,
> + <0 0 23 &gic 0 23 4>,
> + <0 0 24 &gic 0 24 4>,
> + <0 0 25 &gic 0 25 4>,
> + <0 0 26 &gic 0 26 4>,
> + <0 0 27 &gic 0 27 4>,
> + <0 0 28 &gic 0 28 4>,
> + <0 0 29 &gic 0 29 4>,
> + <0 0 30 &gic 0 30 4>,
> + <0 0 31 &gic 0 31 4>,
> + <0 0 32 &gic 0 32 4>,
> + <0 0 33 &gic 0 33 4>,
> + <0 0 34 &gic 0 34 4>,
> + <0 0 35 &gic 0 35 4>,
> + <0 0 36 &gic 0 36 4>,
> + <0 0 37 &gic 0 37 4>,
> + <0 0 38 &gic 0 38 4>,
> + <0 0 39 &gic 0 39 4>,
> + <0 0 40 &gic 0 40 4>,
> + <0 0 41 &gic 0 41 4>,
> + <0 0 42 &gic 0 42 4>;
> + };
> +};
> +
> +/include/ "vexpress-v2m-rs1.dtsi"
> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index 9747125..e5d309e 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -22,6 +22,11 @@ config ARCH_VEXPRESS_DT
> bool
> select OF
>
> +config ARCH_VEXPRESS_V2P_CA5S
> + bool "CoreTile Express A5x2 (V2P-CA5s) - DT"
> + select ARCH_VEXPRESS_RS1
> + select ARCH_VEXPRESS_DT
> +
> config ARCH_VEXPRESS_V2P_CA9
> bool "CoreTile Express A9x4 (V2P-CA9) - DT"
> select ARCH_VEXPRESS_LEGACY
> diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
> index 9cc4a21..4d37963 100644
> --- a/arch/arm/mach-vexpress/Makefile
> +++ b/arch/arm/mach-vexpress/Makefile
> @@ -4,6 +4,7 @@
>
> obj-y := v2m.o
> obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
> +obj-$(CONFIG_ARCH_VEXPRESS_V2P_CA5S) += v2p-ca5s.o
> obj-$(CONFIG_ARCH_VEXPRESS_V2P_CA9) += v2p-ca9.o
> obj-$(CONFIG_SMP) += platsmp.o
> obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
> diff --git a/arch/arm/mach-vexpress/v2p-ca5s.c b/arch/arm/mach-vexpress/v2p-ca5s.c
> new file mode 100644
> index 0000000..46eec0c
> --- /dev/null
> +++ b/arch/arm/mach-vexpress/v2p-ca5s.c
> @@ -0,0 +1,97 @@
> +/*
> + * Device Tree based support for ARM Versatile Express board
> + * with CoreTile Express A5x2 (V2P-CA5s)
> + */
> +
> +#include <linux/init.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/smp_scu.h>
> +#include <asm/smp_twd.h>
> +#include <asm/hardware/cache-l2x0.h>
> +#include <asm/hardware/gic.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/map.h>
> +
> +#include "core.h"
> +
> +#define V2P_CA5_MPCORE_PERIPH 0x2c000000
> +
> +#define A5_MPCORE_SCU 0x0000
> +#define A5_MPCORE_TWD 0x0600
> +
> +static struct map_desc v2p_ca5s_io_desc[] __initdata = {
> + {
> + .virtual = V2TILE_PERIPH,
> + .pfn = __phys_to_pfn(V2P_CA5_MPCORE_PERIPH),
> + .length = SZ_8K,
> + .type = MT_DEVICE,
> + },
> +};
> +
> +#ifdef CONFIG_SMP
> +static void v2p_ca5s_init_cpu_map(void)
> +{
> + int i, ncores = scu_get_core_count(V2TILE_PERIPH_P2V(A5_MPCORE_SCU));
This works on A9, does it work on A5? If not, an SCU binding should be
created.
/* Get SCU base */
asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
> +
> + for (i = 0; i < ncores; ++i)
> + set_cpu_possible(i, true);
> +
> + set_smp_cross_call(gic_raise_softirq);
> +}
> +
> +static void v2p_ca5s_smp_enable(unsigned int max_cpus)
> +{
> + scu_enable(V2TILE_PERIPH_P2V(A5_MPCORE_SCU));
> +}
> +#endif
> +
> +static void __init v2p_ca5s_map_io(void)
> +{
> + v2m_dt_map_io(v2m_memory_map_rs1);
> + iotable_init(v2p_ca5s_io_desc, ARRAY_SIZE(v2p_ca5s_io_desc));
> +#ifdef CONFIG_SMP
> + vexpress_init_cpu_map = v2p_ca5s_init_cpu_map;
> + vexpress_smp_enable = v2p_ca5s_smp_enable;
> +#endif
> +}
> +
> +static void __init v2p_ca5s_init_early(void)
> +{
> +#ifdef CONFIG_LOCAL_TIMERS
> + twd_base = V2TILE_PERIPH_P2V(A5_MPCORE_TWD);
> +#endif
> + v2m_dt_init_early();
> +}
> +
> +const static struct of_device_id v2p_ca5s_irq_match[] = {
> + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
> + {}
> +};
> +
> +static void __init v2p_ca5s_init_irq(void)
> +{
> + of_irq_init(v2p_ca5s_irq_match);
> +}
> +
> +static void __init v2p_ca5s_init(void)
> +{
> + l2x0_of_init(0x00400000, 0xfe0fffff);
> + of_platform_populate(NULL, of_default_bus_match_table,
> + v2m_dt_get_auxdata(v2m_memory_map_rs1), NULL);
> +}
> +
> +static const char *v2p_ca5s_dt_match[] __initdata = {
> + "arm,vexpress-v2p-ca5s",
> + NULL,
> +};
> +
> +DT_MACHINE_START(VEXPRESS_V2P_CA5, "ARM Versatile Express V2P-CA5s")
> + .map_io = v2p_ca5s_map_io,
> + .init_early = v2p_ca5s_init_early,
> + .init_irq = v2p_ca5s_init_irq,
> + .timer = &v2m_timer,
> + .init_machine = v2p_ca5s_init,
> + .dt_compat = v2p_ca5s_dt_match,
> +MACHINE_END
^ permalink raw reply [flat|nested] 16+ messages in thread
* [RFC 3/6] ARM: vexpress: Add DT support in v2m
2011-11-08 14:17 ` Rob Herring
@ 2011-11-08 16:11 ` Pawel Moll
-1 siblings, 0 replies; 16+ messages in thread
From: Pawel Moll @ 2011-11-08 16:11 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 2011-11-08 at 14:17 +0000, Rob Herring wrote:
> > +void __init v2m_dt_map_io(enum v2m_memory_map map)
> > +{
> > + switch (map) {
> > + case v2m_memory_map_legacy:
> > + iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
> > + break;
> > + default:
> > + panic("%s: Unknown memory map requested!\n", __func__);
> > + break;
>
> I don't like this approach. Why don't you either have 2 DT machine_descs
> for legacy and new memory map
Well, I do, actually :-)
> > +static void __init v2p_ca9_map_io(void)
> > +{
> > + v2m_dt_map_io(v2m_memory_map_legacy);
> <...>
> > +DT_MACHINE_START(VEXPRESS_V2P_CA9, "ARM Versatile Express V2P-CA9")
> > + .map_io = v2p_ca9_map_io,
> > + .init_early = v2p_ca9_init_early,
> > + .init_irq = v2p_ca9_init_irq,
> > + .timer = &v2m_timer,
> > + .init_machine = v2p_ca9_init,
> > + .dt_compat = v2p_ca9_dt_match,
> > +MACHINE_END
... and...
> > +static void __init v2p_ca5s_map_io(void)
> > +{
> > + v2m_dt_map_io(v2m_memory_map_rs1);
> > + iotable_init(v2p_ca5s_io_desc,
> > ARRAY_SIZE(v2p_ca5s_io_desc));
> <...>
> > +DT_MACHINE_START(VEXPRESS_V2P_CA5, "ARM Versatile Express
> > V2P-CA5s")
> > + .map_io = v2p_ca5s_map_io,
> > + .init_early = v2p_ca5s_init_early,
> > + .init_irq = v2p_ca5s_init_irq,
> > + .timer = &v2m_timer,
> > + .init_machine = v2p_ca5s_init,
> > + .dt_compat = v2p_ca5s_dt_match,
> > +MACHINE_END
> or use the machine compatible strings to select the io table.
I have a way compat variant for the legacy motherboard already:
> + model = "V2P-CA9";
> + compatible = "arm,vexpress-v2p-ca9", "arm,vexpress-legacy", "arm,vexpress";
so I could use it in v2m_dt_map_io(), but it has to be called from the
tile code anyway. And as the tile code knows what memory map is to be
used, I made my life easier :-)
This will most likely change if the A9 and A5 tiles merge...
> > + }
> > +
> > + /* Will become nice ioremap()-s once allowed */
> > + v2m_sysreg_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("sysreg"));
> > + v2m_sysctl_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("sysctl"));
> > + v2m_timer01_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("timer01"));
>
> Generally, timers can be ioremapped already.
Yeah, I suppose I could simply ioremap() the timers (and sysctl, while
we are on that) in v2m_timer_init() itself...
> > +static struct of_dev_auxdata v2m_legacy_dt_auxdata_lookup[] __initdata = {
> > + OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
> > + &v2m_flash_data),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_WDT, "mb:wdt", NULL),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_KMI0, "mb:kmi0", NULL),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_KMI1, "mb:kmi1", NULL),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_UART0, "mb:uart0", NULL),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_UART1, "mb:uart1", NULL),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_UART2, "mb:uart2", NULL),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_UART3, "mb:uart3", NULL),
>
> You are only adding platform_data in 2 cases, so that probably means the
> rest are for clkdev lookups. You can just add the lookups directly.
You're right that most of the auxdata is there purely for the clock
framework's sake. And I just followed the mach-versatile... So what do
you exactly mean? Extending the v2m_lookups[] like that?
}, { /* UART0 */
.dev_id = "mb:uart0",
.clk = &osc2_clk,
}, { /* UART0 DT */
.dev_id = "1c090000.uart",
.clk = &osc2_clk,
}
If so, I'm not sure, really... I think Grant wanted to avoid exactly
that (and that's why he used auxdata in case of versatile...)
The platform data for the flash and mmci will disappear once I'm done
with the relevant bindings, so it would be nice to get rid of the
auxdata then, not waiting for the DT&clocks wedding day ;-)
> > + {}
> > +};
> > +
> > +struct of_dev_auxdata * __init v2m_dt_get_auxdata(enum v2m_memory_map map)
> > +{
> > + switch (map) {
> > + case v2m_memory_map_legacy:
> > + return v2m_legacy_dt_auxdata_lookup;
>
> Because auxdata is matched against addresses, you can just put all
> entries into 1 table for both legacy and new memory map.
Good point. Will do.
Cheers!
Pawel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 3/6] ARM: vexpress: Add DT support in v2m
@ 2011-11-08 16:11 ` Pawel Moll
0 siblings, 0 replies; 16+ messages in thread
From: Pawel Moll @ 2011-11-08 16:11 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-discuss@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org
On Tue, 2011-11-08 at 14:17 +0000, Rob Herring wrote:
> > +void __init v2m_dt_map_io(enum v2m_memory_map map)
> > +{
> > + switch (map) {
> > + case v2m_memory_map_legacy:
> > + iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
> > + break;
> > + default:
> > + panic("%s: Unknown memory map requested!\n", __func__);
> > + break;
>
> I don't like this approach. Why don't you either have 2 DT machine_descs
> for legacy and new memory map
Well, I do, actually :-)
> > +static void __init v2p_ca9_map_io(void)
> > +{
> > + v2m_dt_map_io(v2m_memory_map_legacy);
> <...>
> > +DT_MACHINE_START(VEXPRESS_V2P_CA9, "ARM Versatile Express V2P-CA9")
> > + .map_io = v2p_ca9_map_io,
> > + .init_early = v2p_ca9_init_early,
> > + .init_irq = v2p_ca9_init_irq,
> > + .timer = &v2m_timer,
> > + .init_machine = v2p_ca9_init,
> > + .dt_compat = v2p_ca9_dt_match,
> > +MACHINE_END
... and...
> > +static void __init v2p_ca5s_map_io(void)
> > +{
> > + v2m_dt_map_io(v2m_memory_map_rs1);
> > + iotable_init(v2p_ca5s_io_desc,
> > ARRAY_SIZE(v2p_ca5s_io_desc));
> <...>
> > +DT_MACHINE_START(VEXPRESS_V2P_CA5, "ARM Versatile Express
> > V2P-CA5s")
> > + .map_io = v2p_ca5s_map_io,
> > + .init_early = v2p_ca5s_init_early,
> > + .init_irq = v2p_ca5s_init_irq,
> > + .timer = &v2m_timer,
> > + .init_machine = v2p_ca5s_init,
> > + .dt_compat = v2p_ca5s_dt_match,
> > +MACHINE_END
> or use the machine compatible strings to select the io table.
I have a way compat variant for the legacy motherboard already:
> + model = "V2P-CA9";
> + compatible = "arm,vexpress-v2p-ca9", "arm,vexpress-legacy", "arm,vexpress";
so I could use it in v2m_dt_map_io(), but it has to be called from the
tile code anyway. And as the tile code knows what memory map is to be
used, I made my life easier :-)
This will most likely change if the A9 and A5 tiles merge...
> > + }
> > +
> > + /* Will become nice ioremap()-s once allowed */
> > + v2m_sysreg_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("sysreg"));
> > + v2m_sysctl_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("sysctl"));
> > + v2m_timer01_base = V2M_PERIPH_P2V(v2m_dt_periph_offset("timer01"));
>
> Generally, timers can be ioremapped already.
Yeah, I suppose I could simply ioremap() the timers (and sysctl, while
we are on that) in v2m_timer_init() itself...
> > +static struct of_dev_auxdata v2m_legacy_dt_auxdata_lookup[] __initdata = {
> > + OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
> > + &v2m_flash_data),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_WDT, "mb:wdt", NULL),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_KMI0, "mb:kmi0", NULL),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_KMI1, "mb:kmi1", NULL),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_UART0, "mb:uart0", NULL),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_UART1, "mb:uart1", NULL),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_UART2, "mb:uart2", NULL),
> > + OF_DEV_AUXDATA("arm,primecell", V2M_UART3, "mb:uart3", NULL),
>
> You are only adding platform_data in 2 cases, so that probably means the
> rest are for clkdev lookups. You can just add the lookups directly.
You're right that most of the auxdata is there purely for the clock
framework's sake. And I just followed the mach-versatile... So what do
you exactly mean? Extending the v2m_lookups[] like that?
}, { /* UART0 */
.dev_id = "mb:uart0",
.clk = &osc2_clk,
}, { /* UART0 DT */
.dev_id = "1c090000.uart",
.clk = &osc2_clk,
}
If so, I'm not sure, really... I think Grant wanted to avoid exactly
that (and that's why he used auxdata in case of versatile...)
The platform data for the flash and mmci will disappear once I'm done
with the relevant bindings, so it would be nice to get rid of the
auxdata then, not waiting for the DT&clocks wedding day ;-)
> > + {}
> > +};
> > +
> > +struct of_dev_auxdata * __init v2m_dt_get_auxdata(enum v2m_memory_map map)
> > +{
> > + switch (map) {
> > + case v2m_memory_map_legacy:
> > + return v2m_legacy_dt_auxdata_lookup;
>
> Because auxdata is matched against addresses, you can just put all
> entries into 1 table for both legacy and new memory map.
Good point. Will do.
Cheers!
Pawel
^ permalink raw reply [flat|nested] 16+ messages in thread
* [RFC 6/6] ARM: vexpress: DT-based support for Coretile Express A5x2 (V2P-CA5s)
2011-11-08 14:34 ` Rob Herring
@ 2011-11-08 16:11 ` Pawel Moll
-1 siblings, 0 replies; 16+ messages in thread
From: Pawel Moll @ 2011-11-08 16:11 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 2011-11-08 at 14:34 +0000, Rob Herring wrote:
> I really think v2p-ca5s.c and v2p-ca9.c should be combined into 1 file.
> There's a lot of duplication and the parts that are different can go in
> the DT.
As I mentioned in the cover letter - that's the goal. My (minor) worry
is how to treat such file... The A5 and A9 are very similar indeed, but
A7/A15 are slightly different. So there would be "a5_and_a9.c" and
"a7_and_a15.c" and "64bit_chip.c"... I'll see how it works.
> > + uart0: uart at 090000 {
>
> Use generic names:
>
> s/uart/serial/
Ok, will do.
> > + memory {
>
> memory at 80000000
Ok.
> > +#ifdef CONFIG_SMP
> > +static void v2p_ca5s_init_cpu_map(void)
> > +{
> > + int i, ncores = scu_get_core_count(V2TILE_PERIPH_P2V(A5_MPCORE_SCU));
>
> This works on A9, does it work on A5?
>
> /* Get SCU base */
> asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
Cool, didn't know about this :-) And as this is a PERIPHBASE value
(http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407g/CACCJFCJ.html) it could help with TWD as well.
> If not, an SCU binding should be created.
I'll do one or the other.
Thanks!
Pawel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [RFC 6/6] ARM: vexpress: DT-based support for Coretile Express A5x2 (V2P-CA5s)
@ 2011-11-08 16:11 ` Pawel Moll
0 siblings, 0 replies; 16+ messages in thread
From: Pawel Moll @ 2011-11-08 16:11 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-discuss@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org
On Tue, 2011-11-08 at 14:34 +0000, Rob Herring wrote:
> I really think v2p-ca5s.c and v2p-ca9.c should be combined into 1 file.
> There's a lot of duplication and the parts that are different can go in
> the DT.
As I mentioned in the cover letter - that's the goal. My (minor) worry
is how to treat such file... The A5 and A9 are very similar indeed, but
A7/A15 are slightly different. So there would be "a5_and_a9.c" and
"a7_and_a15.c" and "64bit_chip.c"... I'll see how it works.
> > + uart0: uart@090000 {
>
> Use generic names:
>
> s/uart/serial/
Ok, will do.
> > + memory {
>
> memory@80000000
Ok.
> > +#ifdef CONFIG_SMP
> > +static void v2p_ca5s_init_cpu_map(void)
> > +{
> > + int i, ncores = scu_get_core_count(V2TILE_PERIPH_P2V(A5_MPCORE_SCU));
>
> This works on A9, does it work on A5?
>
> /* Get SCU base */
> asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
Cool, didn't know about this :-) And as this is a PERIPHBASE value
(http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407g/CACCJFCJ.html) it could help with TWD as well.
> If not, an SCU binding should be created.
I'll do one or the other.
Thanks!
Pawel
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2011-11-08 16:11 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-11-08 13:16 [RFC 0/6] Versatile Express DT support Pawel Moll
2011-11-08 13:16 ` Pawel Moll
[not found] ` <1320758169-22668-1-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
2011-11-08 13:16 ` [RFC 1/6] ARM: vexpress: Get rid of MMIO_P2V Pawel Moll
2011-11-08 13:16 ` [RFC 2/6] ARM: vexpress: Remove platform SMP functions from ct_desc Pawel Moll
2011-11-08 13:16 ` [RFC 3/6] ARM: vexpress: Add DT support in v2m Pawel Moll
2011-11-08 14:17 ` Rob Herring
2011-11-08 14:17 ` Rob Herring
2011-11-08 16:11 ` Pawel Moll
2011-11-08 16:11 ` Pawel Moll
2011-11-08 13:16 ` [RFC 4/6] ARM: vexpress: DT-based support for Coretile Express A9x4 (V2P-CA9) Pawel Moll
2011-11-08 13:16 ` [RFC 5/6] ARM: vexpress: Initial RS1 memory map support Pawel Moll
2011-11-08 13:16 ` [RFC 6/6] ARM: vexpress: DT-based support for Coretile Express A5x2 (V2P-CA5s) Pawel Moll
2011-11-08 14:34 ` Rob Herring
2011-11-08 14:34 ` Rob Herring
2011-11-08 16:11 ` Pawel Moll
2011-11-08 16:11 ` Pawel Moll
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