[Qemu-devel] Patches for SMSC LAN911X driver

[Qemu-devel] Patches for SMSC LAN911X driver

[Cachet Bertrand]

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Hello,

In the driver for the SMSC LAN9118 device (hw/lan9118.c), I modify the code to update the PM_CTRL register (switch PM_MODE bits to D0 and set (1b) READY bit ) when writing to the BYTE_TEST register.

Writing to PM_CTRL was not permitted before this modification => raise an harware error => QEMU crash when happen. So when you try to perform network connection in u-boot stage in QEMU, QEMU crashed.

This way it follow the way the device really work. I add to this email an abstract from the LAN9118 datasheet which explain exactly the modification I made :

3.10.2
Functional Description
There is one normal operating power state, D0 and there are two power saving states: D1, and D2. Upon entry into either of the two power saving states, only the PMT_CTRL register is accessible for read operations. In either of the power saving states the READY bit in the PMT_CTRL register will be cleared. Reads of any other addresses are forbidden until the READY bit is set. All writes, with the exception of the wakeup write to BYTE_TEST, are also forbidden until the READY bit is set. Only when in the D0 (Normal) state, when the READY bit is set, can the rest of the device be accessed.

Patch is contained in the following commit : https://bitbucket.org/bca/qemu-linaro/changeset/0aa1f76e5141

I have sent this patch to qemu-linaro but Peter Maydell (pm215 on #qemu IRC channel) told me to send it here because it is against upstream qemu.

Hope I have understood the documentation correctly and that this patch will be helpfull.

Sincerely

--
Bertrand Cachet, Ingénieur CPE (Lyon, France)
Institut REDS, Reconfigurable & Embedded Digital Systems

Tél     : +41 24/55 77 372
Email   : bertrand.cachet@heig-vd.ch<mailto:bertrand.cachet@heig-vd.ch>
Internet: http://www.reds.ch

HEIG-VD, Haute Ecole d'Ingénierie et de Gestion du Canton de Vaud
Rte de Cheseaux 1
CH-1401 Yverdon-les-Bains
Internet: http://www.heig-vd.ch


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Re: [Qemu-devel] Patches for SMSC LAN911X driver

[Andreas Färber]

Hi,

Am 11.11.2011 14:44, schrieb Cachet Bertrand:
> Patch is contained in the following commit :
> https://bitbucket.org/bca/qemu-linaro/changeset/0aa1f76e5141
> 
> I have sent this patch to qemu-linaro but Peter Maydell (pm215 on #qemu
> IRC channel) told me to send it here because it is against upstream qemu.

That's probably not what Peter meant. :)

Please see http://wiki.qemu.org/Contribute/SubmitAPatch

In particular the patch needs to be sent with git-send-email, for review
and git-am compatibility; there should be a short summary line showing
what part of code (file) it applies to (before the in-depth
description); and it needs Signed-off-by(s).

Regards,
Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] Patches for SMSC LAN911X driver

[Peter Maydell]

On 11 November 2011 13:44, Cachet Bertrand <bertrand.cachet@heig-vd.ch> wrote:
> In the driver for the SMSC LAN9118 device (hw/lan9118.c), I modify the code
> to update the PM_CTRL register (switch PM_MODE bits to D0 and set (1b) READY
> bit ) when writing to the BYTE_TEST register.

As Andreas says, if you can submit your patches in line with the
guidelines in http://wiki.qemu.org/Contribute/SubmitAPatch I'd
appreciate it. (In particular we can't apply any patch without a
Signed-off-by: line.)

On the meat of the patch:

   s->pmt_ctrl &= ~0x03000;
   s->pmt_ctrl |= 0x01;

At the moment these two lines will always have no effect, because
pmt_ctrl is set to 0x1 on initialisation and the register-writing
code never allows bits 0x3000 to be set or bit 0x1 to be cleared.

So I'm wondering if we should implement the other power modes
in a slightly more serious way. (Or perhaps we should just have
a comment that that code currently does nothing but is there
for if/when we do do the other power modes properly. Dunno.)

More generally, the data sheet is clear that "read only" means
"writes ignored" and "write only" means "reads as zero" so we
should make sure we implement that for all registers (not just
this one) rather than giving a hw_error().

-- PMM