[U-Boot] [PATCH 1/2] ARM: omap3: added common configuration for Technexion TAM3517

[Igor Grinberg <grinberg@compulab.co.il>]

Hi Stefano,

On 11/23/11 11:26, Stefano Babic wrote:
> The TAM3517 is a SOM module that can be used on custom boards.
> The patch add a common configuration file that is included
> by the boards using this module.
> 
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> CC: Tapani Utrianen <tapani@technexion.com>
> CC: Tom Rini <tom.rini@gmail.com>
> CC: Sandeep Paulraj <s-paulraj@ti.com>
> ---
>  include/configs/tam3517-common.h |  334 ++++++++++++++++++++++++++++++++++++++
>  1 files changed, 334 insertions(+), 0 deletions(-)
>  create mode 100644 include/configs/tam3517-common.h
> 
> diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
> new file mode 100644
> index 0000000..c76138a
> --- /dev/null
> +++ b/include/configs/tam3517-common.h
> @@ -0,0 +1,334 @@
> +/*
> + * Copyright (C) 2011
> + * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
> + *
> + * Copyright (C) 2009 TechNexion Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#ifndef __TAM3517_H
> +#define __TAM3517_H
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_OMAP		/* in a TI OMAP core */
> +#define CONFIG_OMAP34XX		/* which is a 34XX */
> +
> +/* TODO : Check these ones ! */
> +#define CONFIG_TAM3517		/* working with TAM3517 */
> +
> +#define CONFIG_SYS_TEXT_BASE 0x80008000
> +
> +#define CONFIG_SYS_CACHELINE_SIZE	64
> +
> +#define CONFIG_EMIF4	/* The chip has EMIF4 controller */
> +
> +#include <asm/arch/cpu.h>		/* get chip and board defs */
> +#include <asm/arch/omap3.h>
> +
> +/*
> + * Display CPU and Board information
> + */
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +/* Clock Defines */
> +#define V_OSCK			26000000	/* Clock output from T2 */
> +#define V_SCLK			(V_OSCK >> 1)
> +
> +#undef CONFIG_USE_IRQ				/* no support for IRQs */
> +#define CONFIG_MISC_INIT_R
> +
> +#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_REVISION_TAG
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
> +#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
> +					2 * 1024 * 1024)
> +/*
> + * DDR related
> + */
> +#define CONFIG_OMAP3_MICRON_DDR		/* Micron DDR */
> +#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
> +
> +/*
> + * Hardware drivers
> + */
> +
> +/*
> + * NS16550 Configuration
> + */
> +#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
> +
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
> +#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

Can this be inlined? instead of defining the define...

> +
> +/*
> + * select serial console configuration
> + */
> +#define CONFIG_CONS_INDEX		1
> +#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
> +#define CONFIG_SERIAL1			/* UART1 */
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_BAUDRATE			115200
> +#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
> +					115200}
> +#define CONFIG_MMC
> +#define CONFIG_OMAP_HSMMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_DOS_PARTITION
> +
> +#define CONFIG_USB_STORAGE
> +#define CONGIG_CMD_STORAGE
> +#define CONFIG_CMD_FAT
> +
> +/* EHCI */
> +#define CONFIG_OMAP3_GPIO_5
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_OMAP
> +#define CONFIG_OMAP_EHCI_PHY1_RESET	25

The latest patch from Ilya makes it:
CONFIG_OMAP_EHCI_PHY1_RESET_GPIO

> +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
> +/* #define CONFIG_EHCI_DCACHE */
> +
> +/* commands to include */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
> +#define CONFIG_CMD_FAT		/* FAT support			*/
> +#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
> +
> +#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
> +#define CONFIG_CMD_MMC		/* MMC support			*/
> +#define CONFIG_CMD_FAT		/* FAT support			*/
> +#define CONFIG_CMD_NAND		/* NAND support			*/
> +#define CONFIG_CMD_USB
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_CACHE
> +#define CONFIG_CMD_GPIO
> +
> +#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
> +#undef CONFIG_CMD_IMI		/* iminfo			*/
> +#undef CONFIG_CMD_IMLS		/* List all found images	*/
> +
> +#define CONFIG_SYS_NO_FLASH
> +#define CONFIG_HARD_I2C
> +#define CONFIG_SYS_I2C_SPEED		400000
> +#define CONFIG_SYS_I2C_SLAVE		1
> +#define CONFIG_SYS_I2C_BUS		0
> +#define CONFIG_SYS_I2C_BUS_SELECT	1
> +#define CONFIG_DRIVER_OMAP34XX_I2C
> +
> +#define CONFIG_CMD_NET
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NFS
> +
> +/*
> + * Board NAND Info.
> + */
> +#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
> +							/* to access nand */
> +#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
> +							/* to access */
> +							/* nand at CS0 */
> +
> +#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
> +							/* NAND devices */
> +#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
> +
> +#define CONFIG_JFFS2_NAND
> +/* nand device jffs2 lives on */
> +#define CONFIG_JFFS2_DEV		"nand0"
> +/* start of jffs2 partition */
> +#define CONFIG_JFFS2_PART_OFFSET	0x680000
> +#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */

Can SZ_* defines from arch/arm/include/asm/sizes.h be used here?

> +
> +#define CONFIG_AUTO_COMPLETE
> +/*
> + * Miscellaneous configurable options
> + */
> +
> +#define CONFIG_SYS_LONGHELP		/* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
> +
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> +					sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS		32	/* max number of command */
> +						/* args */
> +/* Boot Argument Buffer Size */
> +#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
> +/* memtest works on */
> +#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
> +#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
> +					0x01F00000) /* 31MB */
> +
> +#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
> +								/* address */
> +
> +/*
> + * AM3517 has 12 GP timers, they can be driven by the system clock
> + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
> + * This rate is divided by a local divisor.
> + */
> +#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
> +#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
> +#define CONFIG_SYS_HZ			1000
> +
> +/*-----------------------------------------------------------------------
> + * Stack sizes
> + *
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
> +#ifdef CONFIG_USE_IRQ
> +#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
> +#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
> +#endif

These can be removed, as already done in a recent patch from Thomas:
http://patchwork.ozlabs.org/patch/127087/

> +
> +/*-----------------------------------------------------------------------
> + * Physical Memory Map
> + */
> +#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
> +#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
> +#define PHYS_SDRAM_1_SIZE	(32 << 20)	/*@least 32 MiB */
> +#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
> +
> +/* SDRAM Bank Allocation method */
> +/* TODO : Check */
> +/* #define SDRC_R_B_C		1 */

This is also, removed by a patch from Thomas:
http://patchwork.ozlabs.org/patch/127145/

> +
> +/*-----------------------------------------------------------------------
> + * FLASH and environment organization
> + */
> +
> +/* **** PISMO SUPPORT *** */
> +
> +/* Configure the PISMO */
> +#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
> +
> +#define CONFIG_NAND_OMAP_GPMC
> +#define GPMC_NAND_ECC_LP_x16_LAYOUT
> +#define CONFIG_ENV_IS_IN_NAND
> +#define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
> +
> +#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
> +#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
> +#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
> +
> +/*-----------------------------------------------------------------------
> + * CFI FLASH driver setup
> + */
> +/* timeout values are in ticks */
> +#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
> +#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
> +
> +/* Flash banks JFFS2 should use */
> +#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
> +					CONFIG_SYS_MAX_NAND_DEVICE)
> +#define CONFIG_SYS_JFFS2_MEM_NAND
> +/* use flash_info[2] */
> +#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
> +#define CONFIG_SYS_JFFS2_NUM_BANKS	1
> +
> +#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
> +#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
> +#define CONFIG_SYS_INIT_RAM_SIZE	0x800
> +#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
> +					 CONFIG_SYS_INIT_RAM_SIZE - \
> +					 GENERATED_GBL_DATA_SIZE)
> +
> +/*
> + * ethernet support
> + *
> + */
> +#if defined(CONFIG_CMD_NET)
> +#define CONFIG_DRIVER_TI_EMAC
> +#define CONFIG_DRIVER_TI_EMAC_USE_RMII
> +#define CONFIG_MII
> +#define CONFIG_EMAC_MDIO_PHY_NUM	0
> +#define	CONFIG_BOOTP_DEFAULT

Can this be aligned with all the others?

> +#define CONFIG_BOOTP_DNS
> +#define CONFIG_BOOTP_DNS2
> +#define CONFIG_BOOTP_SEND_HOSTNAME
> +#define CONFIG_NET_RETRY_COUNT 10
> +#define CONFIG_NET_MULTI
> +
> +#endif
> +
> +/* Defines for SPL */
> +#define CONFIG_SPL
> +#define CONFIG_SPL_CONSOLE
> +#define CONFIG_SPL_NAND_SIMPLE
> +#define CONFIG_SPL_NAND_SOFTECC
> +#define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */
> +
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBDISK_SUPPORT
> +#define CONFIG_SPL_I2C_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SPL_POWER_SUPPORT
> +#define CONFIG_SPL_NAND_SUPPORT
> +#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
> +
> +#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
> +#define CONFIG_SPL_MAX_SIZE		0xB400  /* 45 K */
> +#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
> +
> +#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
> +#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
> +#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
> +
> +/* NAND boot config */
> +#define CONFIG_SYS_NAND_PAGE_COUNT	64
> +#define CONFIG_SYS_NAND_PAGE_SIZE	2048
> +#define CONFIG_SYS_NAND_OOBSIZE		64
> +#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)

Can this have a spaces around the '*' operator?

> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
> +#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
> +					 48, 49, 50, 51, 52, 53, 54, 55,\
> +					 56, 57, 58, 59, 60, 61, 62, 63}
> +#define CONFIG_SYS_NAND_ECCSIZE		256
> +#define CONFIG_SYS_NAND_ECCBYTES	3
> +
> +#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
> +						CONFIG_SYS_NAND_ECCSIZE)
> +#define CONFIG_SYS_NAND_ECCTOTAL       (CONFIG_SYS_NAND_ECCBYTES * \
> +						CONFIG_SYS_NAND_ECCSTEPS)
> +
> +#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE

Here (and in some more places) you have spaces for alignment.

> +
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
> +#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
> +
> +#endif /* __TAM3517_H */

-- 
Regards,
Igor.