Re: [r600g] ATI Radeon HD6950, dual monitor and power profile

[Harald Judt <h.judt@gmx.at>]

Am 20.12.2011 21:20, schrieb Adam Jackson:
> On 12/20/11 1:38 PM, Harald Judt wrote:
>> Hi,
>>
>> When using more than one monitor, the card uses higher clocks than in
>> single-monitor mode and low-power profile. As a subjectively negative
>> side-effect, the fan on the card starts making more noise. Other cards I
>> used before had no problem with staying quiet even when more monitors
>> were attached.
>>
>> As soon as I switch back to single-monitor mode, clocks go down and the
>> card becomes silent again.
>>
>> Is there a way to manually force lower clock speeds, and therefore reach
>> an acceptable noise level? Maybe make it use the same power profile
>> settings in dual-monitor as in single-monitor?
>
> It really depends on what kind of power profiles the device exposes.
> Boot with drm.debug=0x2 and they'll be in dmesg.
>
> - ajax

Here we go:

[drm] Initialized drm 1.1.0 20060810
[drm] radeon defaulting to kernel modesetting.
[drm] radeon kernel modesetting enabled.
radeon 0000:01:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
radeon 0000:01:00.0: setting latency timer to 64
[drm] initializing kernel modesetting (CAYMAN 0x1002:0x6719 0x1002:0x0B00).
[drm] register mmio base: 0xFE620000
[drm] register mmio size: 131072
ATOM BIOS: CAYMAN
radeon 0000:01:00.0: VRAM: 2048M 0x0000000000000000 - 0x000000007FFFFFFF 
(2048M used)
radeon 0000:01:00.0: GTT: 512M 0x0000000080000000 - 0x000000009FFFFFFF
mtrr: type mismatch for c0000000,10000000 old: write-back new: 
write-combining
[drm] Detected VRAM RAM=2048M, BAR=256M
[drm] RAM width 256bits DDR
[TTM] Zone  kernel: Available graphics memory: 8209192 kiB.
[TTM] Zone   dma32: Available graphics memory: 2097152 kiB.
[TTM] Initializing pool allocator.
[drm] radeon: 2048M of VRAM memory ready
[drm] radeon: 512M of GTT memory ready.
[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[drm] Driver supports precise vblank timestamp query.
radeon 0000:01:00.0: irq 54 for MSI/MSI-X
radeon 0000:01:00.0: radeon: using MSI.
[drm] radeon: irq initialized.
[drm] GART: num cpu pages 131072, num gpu pages 131072
[drm] Loading CAYMAN Microcode
[drm] PCIE GART of 512M enabled (table at 0x0000000000040000).
radeon 0000:01:00.0: WB enabled
[drm] ring test succeeded in 3 usecs
[drm] radeon: ib pool ready.
[drm] ib test succeeded in 0 usecs
[drm] Radeon Display Connectors
[drm] Connector 0:
[drm]   DisplayPort
[drm]   HPD5
[drm]   DDC: 0x6430 0x6430 0x6434 0x6434 0x6438 0x6438 0x643c 0x643c
[drm]   Encoders:
[drm]     DFP1: INTERNAL_UNIPHY2
[drm] Connector 1:
[drm]   DisplayPort
[drm]   HPD4
[drm]   DDC: 0x6440 0x6440 0x6444 0x6444 0x6448 0x6448 0x644c 0x644c
[drm]   Encoders:
[drm]     DFP2: INTERNAL_UNIPHY2
[drm] Connector 2:
[drm]   HDMI-A
[drm]   HPD6
[drm]   DDC: 0x6460 0x6460 0x6464 0x6464 0x6468 0x6468 0x646c 0x646c
[drm]   Encoders:
[drm]     DFP3: INTERNAL_UNIPHY1
[drm] Connector 3:
[drm]   DVI-D
[drm]   HPD1
[drm]   DDC: 0x6450 0x6450 0x6454 0x6454 0x6458 0x6458 0x645c 0x645c
[drm]   Encoders:
[drm]     DFP4: INTERNAL_UNIPHY1
[drm] Connector 4:
[drm]   DVI-I
[drm]   HPD3
[drm]   DDC: 0x6470 0x6470 0x6474 0x6474 0x6478 0x6478 0x647c 0x647c
[drm]   Encoders:
[drm]     DFP5: INTERNAL_UNIPHY
[drm]     CRT1: INTERNAL_KLDSCP_DAC1
[drm] Internal thermal controller with fan control
[drm:radeon_pm_print_states], 4 Power State(s)
[drm:radeon_pm_print_states], State 0: Default
[drm:radeon_pm_print_states], 	Default
[drm:radeon_pm_print_states], 	16 PCIE Lanes
[drm:radeon_pm_print_states], 	3 Clock Mode(s)
[drm:radeon_pm_print_states], 		0 e: 800000	m: 1250000	v: 1060	No 
display only
[drm:radeon_pm_print_states], 		1 e: 800000	m: 1250000	v: 1060
[drm:radeon_pm_print_states], 		2 e: 800000	m: 1250000	v: 1060
[drm:radeon_pm_print_states], State 1: Performance
[drm:radeon_pm_print_states], 	16 PCIE Lanes
[drm:radeon_pm_print_states], 	3 Clock Mode(s)
[drm:radeon_pm_print_states], 		0 e: 250000	m: 150000	v: 900	No display only
[drm:radeon_pm_print_states], 		1 e: 500000	m: 1250000	v: 1000
[drm:radeon_pm_print_states], 		2 e: 800000	m: 1250000	v: 1060
[drm:radeon_pm_print_states], State 2: Default
[drm:radeon_pm_print_states], 	16 PCIE Lanes
[drm:radeon_pm_print_states], 	3 Clock Mode(s)
[drm:radeon_pm_print_states], 		0 e: 500000	m: 1250000	v: 1000	No 
display only
[drm:radeon_pm_print_states], 		1 e: 500000	m: 1250000	v: 1000
[drm:radeon_pm_print_states], 		2 e: 725000	m: 1250000	v: 1060
[drm:radeon_pm_print_states], State 3: Default
[drm:radeon_pm_print_states], 	16 PCIE Lanes
[drm:radeon_pm_print_states], 	3 Clock Mode(s)
[drm:radeon_pm_print_states], 		0 e: 500000	m: 1250000	v: 1000	No 
display only
[drm:radeon_pm_print_states], 		1 e: 500000	m: 1250000	v: 1000
[drm:radeon_pm_print_states], 		2 e: 725000	m: 1250000	v: 1060
[drm] radeon: power management initialized
[drm] fb mappable at 0xC0142000
[drm] vram apper at 0xC0000000
[drm] size 8294400
[drm] fb depth is 24
[drm]    pitch is 7680
fbcon: radeondrmfb (fb0) is primary device
[drm:radeon_set_power_state], Setting: e: 80000
[drm:radeon_set_power_state], Setting: m: 125000
Console: switching to colour frame buffer device 240x67
fb0: radeondrmfb frame buffer device
drm: registered panic notifier
[drm] Initialized radeon 2.12.0 20080528 for 0000:01:00.0 on minor 0

There are three Default and one Performance State. How can they be 
related to the /sys profile entry? Further, how are the ones for 
multi-display configuration chosen?

BTW: I guess there is a typo somewhere in the drm debug code? Evidently, 
the last 0 is missing here:
   [drm:radeon_set_power_state], Setting: e: 80000
   [drm:radeon_set_power_state], Setting: m: 125000

Regards,
Harald

-- 
`Experience is the best teacher.'