From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes
Date: Mon, 16 Jan 2012 10:22:34 -0800 [thread overview]
Message-ID: <4F146AEA.90600@codeaurora.org> (raw)
In-Reply-To: <1326728658-10029-1-git-send-email-will.deacon@arm.com>
On 01/16/12 07:44, Will Deacon wrote:
> The linker script assumes a cacheline size of 32 bytes when aligning
> the .data..cacheline_aligned and .data..percpu sections.
>
> This patch updates the script to use L1_CACHE_BYTES, which should be set
> to 64 on platforms that require it.
>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
>
> v2: incorporated suggestions from Stephen Boyd
What do you think about aligning the exception fixup table to the same
value?
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2012-01-16 18:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-01-16 15:44 [PATCH 1/2] ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes Will Deacon
2012-01-16 15:44 ` [PATCH 2/2] ARM: cache: assume 64-byte L1 cachelines for ARMv7 CPUs Will Deacon
2012-01-16 15:52 ` Shilimkar, Santosh
2012-01-16 16:09 ` Russell King - ARM Linux
2012-01-16 16:14 ` Will Deacon
2012-01-16 16:24 ` Shilimkar, Santosh
2012-01-16 18:22 ` Stephen Boyd [this message]
2012-01-16 18:26 ` [PATCH 1/2] ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes Will Deacon
2012-01-16 18:30 ` Stephen Boyd
2012-01-16 19:11 ` Will Deacon
2012-01-16 19:35 ` Nicolas Pitre
2012-01-17 10:11 ` Will Deacon
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