From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes
Date: Mon, 16 Jan 2012 10:30:23 -0800 [thread overview]
Message-ID: <4F146CBF.6030104@codeaurora.org> (raw)
In-Reply-To: <20120116182622.GC11088@mudshark.cambridge.arm.com>
On 01/16/12 10:26, Will Deacon wrote:
> On Mon, Jan 16, 2012 at 06:22:34PM +0000, Stephen Boyd wrote:
>>
>> What do you think about aligning the exception fixup table to the same
>> value?
> Hmm, I'm not sure I see what that gains us over the current 32-byte
> alignment. Are you seeing any measurable performance difference with it being
> cacheline-aligned?
>
I haven't measured anything yet. I just see that it's another value
hard-coded to 32 in the linker script and that tile has decided to use
L1_CACHE_BYTES for it.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2012-01-16 18:30 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-01-16 15:44 [PATCH 1/2] ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes Will Deacon
2012-01-16 15:44 ` [PATCH 2/2] ARM: cache: assume 64-byte L1 cachelines for ARMv7 CPUs Will Deacon
2012-01-16 15:52 ` Shilimkar, Santosh
2012-01-16 16:09 ` Russell King - ARM Linux
2012-01-16 16:14 ` Will Deacon
2012-01-16 16:24 ` Shilimkar, Santosh
2012-01-16 18:22 ` [PATCH 1/2] ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes Stephen Boyd
2012-01-16 18:26 ` Will Deacon
2012-01-16 18:30 ` Stephen Boyd [this message]
2012-01-16 19:11 ` Will Deacon
2012-01-16 19:35 ` Nicolas Pitre
2012-01-17 10:11 ` Will Deacon
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