[PATCH v2] powerpc/usb: fix issue of CPU halt when missing USB PHY clock

[PATCH v2] powerpc/usb: fix issue of CPU halt when missing USB PHY clock

[Shengzhou Liu]

when missing USB PHY clock, kernel booting up will halt during USB
initialization. We should check USBGP[PHY_CLK_VALID] bit to avoid
CPU hang in this case.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
---
v2: changes: return -ENODEV instead of -1

 drivers/usb/host/ehci-fsl.c |   11 +++++++++--
 drivers/usb/host/ehci-fsl.h |    1 +
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index b556a72..c26a82e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -239,7 +239,7 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
 	ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
 }
 
-static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
+static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
 {
 	struct usb_hcd *hcd = ehci_to_hcd(ehci);
 	struct fsl_usb2_platform_data *pdata;
@@ -299,12 +299,19 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
 #endif
 		out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
 	}
+
+	if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & CTRL_PHY_CLK_VALID)) {
+		printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");
+		return -ENODEV;
+	}
+	return 0;
 }
 
 /* called after powerup, by probe or system-pm "wakeup" */
 static int ehci_fsl_reinit(struct ehci_hcd *ehci)
 {
-	ehci_fsl_usb_setup(ehci);
+	if (ehci_fsl_usb_setup(ehci))
+		return -ENODEV;
 	ehci_port_power(ehci, 0);
 
 	return 0;
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index 4918062..dd3dc47 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -45,5 +45,6 @@
 #define FSL_SOC_USB_PRICTRL	0x40c	/* NOTE: big-endian */
 #define FSL_SOC_USB_SICTRL	0x410	/* NOTE: big-endian */
 #define FSL_SOC_USB_CTRL	0x500	/* NOTE: big-endian */
+#define CTRL_PHY_CLK_VALID      (1 << 17)
 #define SNOOP_SIZE_2GB		0x1e
 #endif				/* _EHCI_FSL_H */
-- 
1.6.4

Re: [PATCH v2] powerpc/usb: fix issue of CPU halt when missing USB PHY clock

[Sergei Shtylyov]

Hello.

On 02-02-2012 7:23, Shengzhou Liu wrote:

> when missing USB PHY clock, kernel booting up will halt during USB
> initialization. We should check USBGP[PHY_CLK_VALID] bit to avoid
> CPU hang in this case.

> Signed-off-by: Shengzhou Liu<Shengzhou.Liu@freescale.com>
[...]

> diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
> index 4918062..dd3dc47 100644
> --- a/drivers/usb/host/ehci-fsl.h
> +++ b/drivers/usb/host/ehci-fsl.h
> @@ -45,5 +45,6 @@
>   #define FSL_SOC_USB_PRICTRL	0x40c	/* NOTE: big-endian */
>   #define FSL_SOC_USB_SICTRL	0x410	/* NOTE: big-endian */
>   #define FSL_SOC_USB_CTRL	0x500	/* NOTE: big-endian */
> +#define CTRL_PHY_CLK_VALID      (1 << 17)

    Indent the macro value with tabs please.

WBR, Sergei

Re: [PATCH v2] powerpc/usb: fix issue of CPU halt when missing USB PHY clock

[Greg KH]

On Thu, Feb 02, 2012 at 03:39:48PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 02-02-2012 7:23, Shengzhou Liu wrote:
> 
> >when missing USB PHY clock, kernel booting up will halt during USB
> >initialization. We should check USBGP[PHY_CLK_VALID] bit to avoid
> >CPU hang in this case.
> 
> >Signed-off-by: Shengzhou Liu<Shengzhou.Liu@freescale.com>
> [...]
> 
> >diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
> >index 4918062..dd3dc47 100644
> >--- a/drivers/usb/host/ehci-fsl.h
> >+++ b/drivers/usb/host/ehci-fsl.h
> >@@ -45,5 +45,6 @@
> >  #define FSL_SOC_USB_PRICTRL	0x40c	/* NOTE: big-endian */
> >  #define FSL_SOC_USB_SICTRL	0x410	/* NOTE: big-endian */
> >  #define FSL_SOC_USB_CTRL	0x500	/* NOTE: big-endian */
> >+#define CTRL_PHY_CLK_VALID      (1 << 17)
> 
>    Indent the macro value with tabs please.

I fixed this by hand.