[PATCH 0/9] MIPS: lantiq: convert to clkdev api

[PATCH 0/9] MIPS: lantiq: convert to clkdev api

[John Crispin]

arch/mips/lantiq/* used its own functions to handle some clocks and the clock
gating. This series changes the code to use clkdev api instead.

This change also allows us to merge the clock code for all xway socs into a
single file.


John Crispin (9):
  MIPS: add clkdev.h
  MIPS: lantiq: convert to clkdev api
  MIPS: lantiq: convert xway to clkdev api
  MIPS: lantiq: convert falcon to clkdev api
  MIPS: lantiq: convert dma driver to clkdev api
  MIPS: lantiq: convert gpio_stp driver to clkdev api
  SERIAL: MIPS: lantiq: convert serial driver to clkdev api
  NET: MIPS: lantiq: convert etop driver to clkdev api
  WDT: MIPS: lantiq: convert watchdog driver to clkdev api

 arch/mips/Kconfig                                  |    3 +-
 arch/mips/include/asm/clkdev.h                     |   25 ++
 .../include/asm/mach-lantiq/falcon/lantiq_soc.h    |    8 +-
 arch/mips/include/asm/mach-lantiq/lantiq.h         |   17 +-
 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   13 -
 arch/mips/lantiq/clk.c                             |   85 +++----
 arch/mips/lantiq/clk.h                             |   59 ++++-
 arch/mips/lantiq/falcon/Makefile                   |    2 +-
 arch/mips/lantiq/falcon/clk.c                      |   44 ----
 arch/mips/lantiq/falcon/sysctrl.c                  |  131 ++++++----
 arch/mips/lantiq/prom.c                            |    1 -
 arch/mips/lantiq/xway/Makefile                     |    6 +-
 arch/mips/lantiq/xway/clk-ase.c                    |   48 ----
 arch/mips/lantiq/xway/clk-xway.c                   |  223 ----------------
 arch/mips/lantiq/xway/clk.c                        |  266 ++++++++++++++++++++
 arch/mips/lantiq/xway/dma.c                        |    5 +-
 arch/mips/lantiq/xway/gpio_stp.c                   |    6 +-
 arch/mips/lantiq/xway/sysctrl.c                    |  106 +++++++-
 drivers/net/ethernet/lantiq_etop.c                 |   27 ++-
 drivers/tty/serial/lantiq.c                        |    2 +-
 drivers/watchdog/lantiq_wdt.c                      |    2 +-
 21 files changed, 603 insertions(+), 476 deletions(-)
 create mode 100644 arch/mips/include/asm/clkdev.h
 delete mode 100644 arch/mips/lantiq/falcon/clk.c
 delete mode 100644 arch/mips/lantiq/xway/clk-ase.c
 delete mode 100644 arch/mips/lantiq/xway/clk-xway.c
 create mode 100644 arch/mips/lantiq/xway/clk.c

-- 
1.7.7.1

[PATCH 1/9] MIPS: add clkdev.h

[John Crispin]

For clkdev to work on MIPS we need this file

include/linux/clkdev.h:#include <asm/clkdev.h>

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/clkdev.h |   25 +++++++++++++++++++++++++
 1 files changed, 25 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/clkdev.h

diff --git a/arch/mips/include/asm/clkdev.h b/arch/mips/include/asm/clkdev.h
new file mode 100644
index 0000000..2624754
--- /dev/null
+++ b/arch/mips/include/asm/clkdev.h
@@ -0,0 +1,25 @@
+/*
+ *  based on arch/arm/include/asm/clkdev.h
+ *
+ *  Copyright (C) 2008 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Helper for the clk API to assist looking up a struct clk.
+ */
+#ifndef __ASM_CLKDEV_H
+#define __ASM_CLKDEV_H
+
+#include <linux/slab.h>
+
+#define __clk_get(clk)	({ 1; })
+#define __clk_put(clk)	do { } while (0)
+
+static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
+{
+	return kzalloc(size, GFP_KERNEL);
+}
+
+#endif
-- 
1.7.7.1

[PATCH 2/9] MIPS: lantiq: convert to clkdev api

[John Crispin]

Add clk_activate/clk_deactivate and add better error paths to the clk
api functions.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/Kconfig                          |    3 +-
 arch/mips/include/asm/mach-lantiq/lantiq.h |   17 ++----
 arch/mips/lantiq/clk.c                     |   85 +++++++++++----------------
 arch/mips/lantiq/clk.h                     |   59 ++++++++++++++++++-
 arch/mips/lantiq/prom.c                    |    1 -
 5 files changed, 97 insertions(+), 68 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c4c1312..b106c9e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -228,7 +228,8 @@ config LANTIQ
 	select ARCH_REQUIRE_GPIOLIB
 	select SWAP_IO_SPACE
 	select BOOT_RAW
-	select HAVE_CLK
+	select HAVE_MACH_CLKDEV
+	select CLKDEV_LOOKUP
 	select MIPS_MACHINE
 
 config LASAT
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index d90eef3..895a346 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -9,6 +9,7 @@
 #define _LANTIQ_H__
 
 #include <linux/irq.h>
+#include <linux/clk.h>
 #include <linux/ioport.h>
 
 /* generic reg access */
@@ -24,18 +25,6 @@ static inline void ltq_w32_mask(u32 c, u32 s, volatile void __iomem *r)
 extern unsigned int ltq_get_cpu_ver(void);
 extern unsigned int ltq_get_soc_type(void);
 
-/* clock speeds */
-#define CLOCK_60M	60000000
-#define CLOCK_83M	83333333
-#define CLOCK_100M	100000000
-#define CLOCK_111M	111111111
-#define CLOCK_133M	133333333
-#define CLOCK_167M	166666667
-#define CLOCK_200M	200000000
-#define CLOCK_266M	266666666
-#define CLOCK_333M	333333333
-#define CLOCK_400M	400000000
-
 /* spinlock all ebu i/o */
 extern spinlock_t ebu_lock;
 
@@ -48,6 +37,10 @@ extern void ltq_disable_irq(struct irq_data *data);
 extern void ltq_mask_and_ack_irq(struct irq_data *data);
 extern void ltq_enable_irq(struct irq_data *data);
 
+/* clock handling */
+extern int clk_activate(struct clk *clk);
+extern void clk_deactivate(struct clk *clk);
+
 /* find out what caused the last cpu reset */
 extern int ltq_reset_cause(void);
 
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index 39eef7f..66d1a60 100644
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -12,6 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/clk.h>
+#include <linux/clkdev.h>
 #include <linux/err.h>
 #include <linux/list.h>
 
@@ -24,35 +25,6 @@
 #include "clk.h"
 #include "prom.h"
 
-struct clk {
-	const char *name;
-	unsigned long rate;
-	unsigned long (*get_rate) (void);
-};
-
-static struct clk *cpu_clk;
-static int cpu_clk_cnt;
-
-/* lantiq socs have 3 static clocks */
-static struct clk cpu_clk_generic[] = {
-	{
-		.name = "cpu",
-		.get_rate = ltq_get_cpu_hz,
-	}, {
-		.name = "fpi",
-		.get_rate = ltq_get_fpi_hz,
-	}, {
-		.name = "io",
-		.get_rate = ltq_get_io_region_clock,
-	},
-};
-
-void clk_init(void)
-{
-	cpu_clk = cpu_clk_generic;
-	cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic);
-}
-
 static inline int clk_good(struct clk *clk)
 {
 	return clk && !IS_ERR(clk);
@@ -61,7 +33,7 @@ static inline int clk_good(struct clk *clk)
 unsigned long clk_get_rate(struct clk *clk)
 {
 	if (unlikely(!clk_good(clk)))
-		return 0;
+		return -1;
 
 	if (clk->rate != 0)
 		return clk->rate;
@@ -69,40 +41,53 @@ unsigned long clk_get_rate(struct clk *clk)
 	if (clk->get_rate != NULL)
 		return clk->get_rate();
 
-	return 0;
+	return -1;
 }
 EXPORT_SYMBOL(clk_get_rate);
 
-struct clk *clk_get(struct device *dev, const char *id)
+int clk_enable(struct clk *clk)
 {
-	int i;
+	if (unlikely(!clk_good(clk)))
+		return -1;
 
-	for (i = 0; i < cpu_clk_cnt; i++)
-		if (!strcmp(id, cpu_clk[i].name))
-			return &cpu_clk[i];
-	BUG();
-	return ERR_PTR(-ENOENT);
+	if (clk->enable)
+		return clk->enable(clk);
+
+	return -1;
 }
-EXPORT_SYMBOL(clk_get);
+EXPORT_SYMBOL(clk_enable);
 
-void clk_put(struct clk *clk)
+void clk_disable(struct clk *clk)
 {
-	/* not used */
+	if (unlikely(!clk_good(clk)))
+		return;
+
+	if (clk->disable)
+		clk->disable(clk);
 }
-EXPORT_SYMBOL(clk_put);
+EXPORT_SYMBOL(clk_disable);
 
-int clk_enable(struct clk *clk)
+int clk_activate(struct clk *clk)
 {
-	/* not used */
-	return 0;
+	if (unlikely(!clk_good(clk)))
+		return -1;
+
+	if (clk->activate)
+		return clk->activate(clk);
+
+	return -1;
 }
-EXPORT_SYMBOL(clk_enable);
+EXPORT_SYMBOL(clk_activate);
 
-void clk_disable(struct clk *clk)
+void clk_deactivate(struct clk *clk)
 {
-	/* not used */
+	if (unlikely(!clk_good(clk)))
+		return;
+
+	if (clk->deactivate)
+		clk->deactivate(clk);
 }
-EXPORT_SYMBOL(clk_disable);
+EXPORT_SYMBOL(clk_deactivate);
 
 static inline u32 ltq_get_counter_resolution(void)
 {
@@ -126,7 +111,7 @@ void __init plat_time_init(void)
 
 	ltq_soc_init();
 
-	clk = clk_get(0, "cpu");
+	clk = clk_get_sys("cpu", NULL);
 	mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
 	write_c0_compare(read_c0_count());
 	pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h
index 3328925..1179bb3 100644
--- a/arch/mips/lantiq/clk.h
+++ b/arch/mips/lantiq/clk.h
@@ -9,10 +9,61 @@
 #ifndef _LTQ_CLK_H__
 #define _LTQ_CLK_H__
 
-extern void clk_init(void);
+#include <linux/clkdev.h>
 
-extern unsigned long ltq_get_cpu_hz(void);
-extern unsigned long ltq_get_fpi_hz(void);
-extern unsigned long ltq_get_io_region_clock(void);
+/* clock speeds */
+#define CLOCK_60M	60000000
+#define CLOCK_62_5M	62500000
+#define CLOCK_83M	83333333
+#define CLOCK_83_5M	83500000
+#define CLOCK_98_304M	98304000
+#define CLOCK_100M	100000000
+#define CLOCK_111M	111111111
+#define CLOCK_125M	125000000
+#define CLOCK_133M	133333333
+#define CLOCK_150M	150000000
+#define CLOCK_166M	166666666
+#define CLOCK_167M	166666667
+#define CLOCK_196_608M	196608000
+#define CLOCK_200M	200000000
+#define CLOCK_250M	250000000
+#define CLOCK_266M	266666666
+#define CLOCK_300M	300000000
+#define CLOCK_333M	333333333
+#define CLOCK_393M	393215332
+#define CLOCK_400M	400000000
+#define CLOCK_500M	500000000
+#define CLOCK_600M	600000000
+
+struct clk {
+	struct clk_lookup cl;
+	unsigned long rate;
+	unsigned long (*get_rate) (void);
+	unsigned int module;
+	unsigned int bits;
+	int (*enable) (struct clk *clk);
+	void (*disable) (struct clk *clk);
+	int (*activate) (struct clk *clk);
+	void (*deactivate) (struct clk *clk);
+	void (*reboot) (struct clk *clk);
+};
+
+static inline void clkdev_add_static(const char *dev, unsigned long rate)
+{
+	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+	clk->cl.dev_id = dev;
+	clk->cl.clk = clk;
+	clk->rate = rate;
+	clkdev_add(&clk->cl);
+}
+
+extern unsigned long ltq_danube_cpu_hz(void);
+extern unsigned long ltq_danube_fpi_hz(void);
+extern unsigned long ltq_danube_io_region_clock(void);
+
+extern unsigned long ltq_vr9_cpu_hz(void);
+extern unsigned long ltq_vr9_fpi_hz(void);
+extern unsigned long ltq_vr9_io_region_clock(void);
 
 #endif
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index ee63a33..b002bc7 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -103,7 +103,6 @@ EXPORT_SYMBOL(ltq_remap_resource);
 void __init prom_init(void)
 {
 	ltq_soc_detect(&soc_info);
-	clk_init();
 	snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
 		soc_info.name, soc_info.rev_type);
 	soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
-- 
1.7.7.1

[PATCH 3/9] MIPS: lantiq: convert xway to clkdev api

[John Crispin]

Unify xway/ase clock code and add clkdev hooks to sysctrl.c

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   13 -
 arch/mips/lantiq/xway/Makefile                     |    6 +-
 arch/mips/lantiq/xway/clk-ase.c                    |   48 ----
 arch/mips/lantiq/xway/clk-xway.c                   |  223 ----------------
 arch/mips/lantiq/xway/clk.c                        |  266 ++++++++++++++++++++
 arch/mips/lantiq/xway/sysctrl.c                    |  106 +++++++-
 6 files changed, 366 insertions(+), 296 deletions(-)
 delete mode 100644 arch/mips/lantiq/xway/clk-ase.c
 delete mode 100644 arch/mips/lantiq/xway/clk-xway.c
 create mode 100644 arch/mips/lantiq/xway/clk.c

diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 4213926..6dfb65e 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -81,15 +81,6 @@
 #define LTQ_PMU_BASE_ADDR	0x1F102000
 #define LTQ_PMU_SIZE		0x1000
 
-#define PMU_DMA			0x0020
-#define PMU_EPHY		0x0080
-#define PMU_USB			0x8041
-#define PMU_LED			0x0800
-#define PMU_GPT			0x1000
-#define PMU_PPE			0x2000
-#define PMU_FPI			0x4000
-#define PMU_SWITCH		0x10000000
-
 /* ETOP - ethernet */
 #define LTQ_ETOP_BASE_ADDR	0x1E180000
 #define LTQ_ETOP_SIZE		0x40000
@@ -167,10 +158,6 @@ static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r)
 	ltq_cgu_w32((ltq_cgu_r32(r) & ~(c)) | (s), r);
 }
 
-extern void ltq_pmu_enable(unsigned int module);
-extern void ltq_pmu_disable(unsigned int module);
-extern void ltq_cgu_enable(unsigned int clk);
-
 static inline int ltq_is_ase(void)
 {
 	return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE);
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 6678402..4dcb96f 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,7 +1,7 @@
-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o
 
-obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
-obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
+obj-$(CONFIG_SOC_XWAY) += prom-xway.o
+obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o
 
 obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
 obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c
deleted file mode 100644
index 6522583..0000000
--- a/arch/mips/lantiq/xway/clk-ase.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/io.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-
-#include <asm/time.h>
-#include <asm/irq.h>
-#include <asm/div64.h>
-
-#include <lantiq_soc.h>
-
-/* cgu registers */
-#define LTQ_CGU_SYS	0x0010
-
-unsigned int ltq_get_io_region_clock(void)
-{
-	return CLOCK_133M;
-}
-EXPORT_SYMBOL(ltq_get_io_region_clock);
-
-unsigned int ltq_get_fpi_bus_clock(int fpi)
-{
-	return CLOCK_133M;
-}
-EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
-
-unsigned int ltq_get_cpu_hz(void)
-{
-	if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
-		return CLOCK_266M;
-	else
-		return CLOCK_133M;
-}
-EXPORT_SYMBOL(ltq_get_cpu_hz);
-
-unsigned int ltq_get_fpi_hz(void)
-{
-	return CLOCK_133M;
-}
-EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c
deleted file mode 100644
index 696b1a3..0000000
--- a/arch/mips/lantiq/xway/clk-xway.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/io.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-
-#include <asm/time.h>
-#include <asm/irq.h>
-#include <asm/div64.h>
-
-#include <lantiq_soc.h>
-
-static unsigned int ltq_ram_clocks[] = {
-	CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
-#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
-
-#define BASIC_FREQUENCY_1	35328000
-#define BASIC_FREQUENCY_2	36000000
-#define BASIS_REQUENCY_USB	12000000
-
-#define GET_BITS(x, msb, lsb) \
-	(((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
-
-#define LTQ_CGU_PLL0_CFG	0x0004
-#define LTQ_CGU_PLL1_CFG	0x0008
-#define LTQ_CGU_PLL2_CFG	0x000C
-#define LTQ_CGU_SYS		0x0010
-#define LTQ_CGU_UPDATE		0x0014
-#define LTQ_CGU_IF_CLK		0x0018
-#define LTQ_CGU_OSC_CON		0x001C
-#define LTQ_CGU_SMD		0x0020
-#define LTQ_CGU_CT1SR		0x0028
-#define LTQ_CGU_CT2SR		0x002C
-#define LTQ_CGU_PCMCR		0x0030
-#define LTQ_CGU_PCI_CR		0x0034
-#define LTQ_CGU_PD_PC		0x0038
-#define LTQ_CGU_FMR		0x003C
-
-#define CGU_PLL0_PHASE_DIVIDER_ENABLE	\
-	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
-#define CGU_PLL0_BYPASS			\
-	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
-#define CGU_PLL0_CFG_DSMSEL		\
-	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
-#define CGU_PLL0_CFG_FRAC_EN		\
-	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
-#define CGU_PLL1_SRC			\
-	(ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
-#define CGU_PLL2_PHASE_DIVIDER_ENABLE	\
-	(ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
-#define CGU_SYS_FPI_SEL			(1 << 6)
-#define CGU_SYS_DDR_SEL			0x3
-#define CGU_PLL0_SRC			(1 << 29)
-
-#define CGU_PLL0_CFG_PLLK	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
-#define CGU_PLL0_CFG_PLLN	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
-#define CGU_PLL0_CFG_PLLM	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
-#define CGU_PLL2_SRC		GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
-#define CGU_PLL2_CFG_INPUT_DIV	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
-
-static unsigned int ltq_get_pll0_fdiv(void);
-
-static inline unsigned int get_input_clock(int pll)
-{
-	switch (pll) {
-	case 0:
-		if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
-			return BASIS_REQUENCY_USB;
-		else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
-			return BASIC_FREQUENCY_1;
-		else
-			return BASIC_FREQUENCY_2;
-	case 1:
-		if (CGU_PLL1_SRC)
-			return BASIS_REQUENCY_USB;
-		else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
-			return BASIC_FREQUENCY_1;
-		else
-			return BASIC_FREQUENCY_2;
-	case 2:
-		switch (CGU_PLL2_SRC) {
-		case 0:
-			return ltq_get_pll0_fdiv();
-		case 1:
-			return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
-				BASIC_FREQUENCY_1 :
-				BASIC_FREQUENCY_2;
-		case 2:
-			return BASIS_REQUENCY_USB;
-		}
-	default:
-		return 0;
-	}
-}
-
-static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
-{
-	u64 res, clock = get_input_clock(pll);
-
-	res = num * clock;
-	do_div(res, den);
-	return res;
-}
-
-static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
-	unsigned int K)
-{
-	unsigned int num = ((N + 1) << 10) + K;
-	unsigned int den = (M + 1) << 10;
-
-	return cal_dsm(pll, num, den);
-}
-
-static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
-	unsigned int K)
-{
-	unsigned int num = ((N + 1) << 11) + K + 512;
-	unsigned int den = (M + 1) << 11;
-
-	return cal_dsm(pll, num, den);
-}
-
-static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
-	unsigned int K)
-{
-	unsigned int num = K >= 512 ?
-		((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
-	unsigned int den = (M + 1) << 12;
-
-	return cal_dsm(pll, num, den);
-}
-
-static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
-	unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
-{
-	if (!dsmsel)
-		return mash_dsm(pll, M, N, K);
-	else if (!phase_div_en)
-		return mash_dsm(pll, M, N, K);
-	else
-		return ssff_dsm_2(pll, M, N, K);
-}
-
-static inline unsigned int ltq_get_pll0_fosc(void)
-{
-	if (CGU_PLL0_BYPASS)
-		return get_input_clock(0);
-	else
-		return !CGU_PLL0_CFG_FRAC_EN
-			? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
-				CGU_PLL0_CFG_DSMSEL,
-				CGU_PLL0_PHASE_DIVIDER_ENABLE)
-			: dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
-				CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
-				CGU_PLL0_PHASE_DIVIDER_ENABLE);
-}
-
-static unsigned int ltq_get_pll0_fdiv(void)
-{
-	unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
-
-	return (ltq_get_pll0_fosc() + (div >> 1)) / div;
-}
-
-unsigned int ltq_get_io_region_clock(void)
-{
-	unsigned int ret = ltq_get_pll0_fosc();
-
-	switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
-	default:
-	case 0:
-		return (ret + 1) / 2;
-	case 1:
-		return (ret * 2 + 2) / 5;
-	case 2:
-		return (ret + 1) / 3;
-	case 3:
-		return (ret + 2) / 4;
-	}
-}
-EXPORT_SYMBOL(ltq_get_io_region_clock);
-
-unsigned int ltq_get_fpi_bus_clock(int fpi)
-{
-	unsigned int ret = ltq_get_io_region_clock();
-
-	if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
-		ret >>= 1;
-	return ret;
-}
-EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
-
-unsigned int ltq_get_cpu_hz(void)
-{
-	switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
-	case 0:
-		return CLOCK_333M;
-	case 4:
-		return DDR_HZ;
-	case 8:
-		return DDR_HZ << 1;
-	default:
-		return DDR_HZ >> 1;
-	}
-}
-EXPORT_SYMBOL(ltq_get_cpu_hz);
-
-unsigned int ltq_get_fpi_hz(void)
-{
-	unsigned int ddr_clock = DDR_HZ;
-
-	if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
-		return ddr_clock >> 1;
-	return ddr_clock;
-}
-EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
new file mode 100644
index 0000000..88a1017
--- /dev/null
+++ b/arch/mips/lantiq/xway/clk.c
@@ -0,0 +1,266 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/io.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+
+#include <asm/time.h>
+#include <asm/irq.h>
+#include <asm/div64.h>
+
+#include <lantiq_soc.h>
+
+#include "../clk.h"
+
+static unsigned int ltq_ram_clocks[] = {
+	CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
+#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
+
+#define BASIC_FREQUENCY_1	35328000
+#define BASIC_FREQUENCY_2	36000000
+#define BASIS_REQUENCY_USB	12000000
+
+#define GET_BITS(x, msb, lsb) \
+	(((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
+
+/* legacy xway clock */
+#define LTQ_CGU_PLL0_CFG	0x0004
+#define LTQ_CGU_PLL1_CFG	0x0008
+#define LTQ_CGU_PLL2_CFG	0x000C
+#define LTQ_CGU_SYS		0x0010
+#define LTQ_CGU_UPDATE		0x0014
+#define LTQ_CGU_IF_CLK		0x0018
+#define LTQ_CGU_OSC_CON		0x001C
+#define LTQ_CGU_SMD		0x0020
+#define LTQ_CGU_CT1SR		0x0028
+#define LTQ_CGU_CT2SR		0x002C
+#define LTQ_CGU_PCMCR		0x0030
+#define LTQ_CGU_PCI_CR		0x0034
+#define LTQ_CGU_PD_PC		0x0038
+#define LTQ_CGU_FMR		0x003C
+
+#define CGU_PLL0_PHASE_DIVIDER_ENABLE	\
+	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
+#define CGU_PLL0_BYPASS			\
+	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
+#define CGU_PLL0_CFG_DSMSEL		\
+	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
+#define CGU_PLL0_CFG_FRAC_EN		\
+	(ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
+#define CGU_PLL1_SRC			\
+	(ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
+#define CGU_PLL2_PHASE_DIVIDER_ENABLE	\
+	(ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
+#define CGU_SYS_FPI_SEL			(1 << 6)
+#define CGU_SYS_DDR_SEL			0x3
+#define CGU_PLL0_SRC			(1 << 29)
+
+#define CGU_PLL0_CFG_PLLK	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
+#define CGU_PLL0_CFG_PLLN	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
+#define CGU_PLL0_CFG_PLLM	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
+#define CGU_PLL2_SRC		GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
+#define CGU_PLL2_CFG_INPUT_DIV	GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
+
+/* vr9 clock */
+#define LTQ_CGU_SYS_VR9	0x0c
+#define LTQ_CGU_IF_CLK_VR9	0x24
+
+
+static unsigned int ltq_get_pll0_fdiv(void);
+
+static inline unsigned int get_input_clock(int pll)
+{
+	switch (pll) {
+	case 0:
+		if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
+			return BASIS_REQUENCY_USB;
+		else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
+			return BASIC_FREQUENCY_1;
+		else
+			return BASIC_FREQUENCY_2;
+	case 1:
+		if (CGU_PLL1_SRC)
+			return BASIS_REQUENCY_USB;
+		else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
+			return BASIC_FREQUENCY_1;
+		else
+			return BASIC_FREQUENCY_2;
+	case 2:
+		switch (CGU_PLL2_SRC) {
+		case 0:
+			return ltq_get_pll0_fdiv();
+		case 1:
+			return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
+				BASIC_FREQUENCY_1 :
+				BASIC_FREQUENCY_2;
+		case 2:
+			return BASIS_REQUENCY_USB;
+		}
+	default:
+		return 0;
+	}
+}
+
+static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
+{
+	u64 res, clock = get_input_clock(pll);
+
+	res = num * clock;
+	do_div(res, den);
+	return res;
+}
+
+static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
+	unsigned int K)
+{
+	unsigned int num = ((N + 1) << 10) + K;
+	unsigned int den = (M + 1) << 10;
+
+	return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
+	unsigned int K)
+{
+	unsigned int num = ((N + 1) << 11) + K + 512;
+	unsigned int den = (M + 1) << 11;
+
+	return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
+	unsigned int K)
+{
+	unsigned int num = K >= 512 ?
+		((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
+	unsigned int den = (M + 1) << 12;
+
+	return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
+	unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
+{
+	if (!dsmsel)
+		return mash_dsm(pll, M, N, K);
+	else if (!phase_div_en)
+		return mash_dsm(pll, M, N, K);
+	else
+		return ssff_dsm_2(pll, M, N, K);
+}
+
+static inline unsigned int ltq_get_pll0_fosc(void)
+{
+	if (CGU_PLL0_BYPASS)
+		return get_input_clock(0);
+	else
+		return !CGU_PLL0_CFG_FRAC_EN
+			? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
+				CGU_PLL0_CFG_DSMSEL,
+				CGU_PLL0_PHASE_DIVIDER_ENABLE)
+			: dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
+				CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
+				CGU_PLL0_PHASE_DIVIDER_ENABLE);
+}
+
+static unsigned int ltq_get_pll0_fdiv(void)
+{
+	unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
+
+	return (ltq_get_pll0_fosc() + (div >> 1)) / div;
+}
+
+unsigned long ltq_danube_io_region_clock(void)
+{
+	unsigned int ret = ltq_get_pll0_fosc();
+
+	switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
+	default:
+	case 0:
+		return (ret + 1) / 2;
+	case 1:
+		return (ret * 2 + 2) / 5;
+	case 2:
+		return (ret + 1) / 3;
+	case 3:
+		return (ret + 2) / 4;
+	}
+}
+
+unsigned long ltq_danube_fpi_bus_clock(int fpi)
+{
+	unsigned long ret = ltq_danube_io_region_clock();
+
+	if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
+		ret >>= 1;
+	return ret;
+}
+
+unsigned long ltq_danube_cpu_hz(void)
+{
+	switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
+	case 0:
+		return CLOCK_333M;
+	case 4:
+		return DDR_HZ;
+	case 8:
+		return DDR_HZ << 1;
+	default:
+		return DDR_HZ >> 1;
+	}
+}
+
+unsigned long ltq_danube_fpi_hz(void)
+{
+	unsigned long ddr_clock = DDR_HZ;
+
+	if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
+		return ddr_clock >> 1;
+	return ddr_clock;
+}
+
+unsigned long ltq_vr9_cpu_hz(void)
+{
+	long clks[] = {
+		CLOCK_600M, CLOCK_500M,	CLOCK_393M, CLOCK_333M,
+		CLOCK_125M, CLOCK_125M, CLOCK_196_608M, CLOCK_166M,
+		CLOCK_125M, CLOCK_125M };
+	int val = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf;
+
+	if (val > 9)
+		panic("bad cpu speed");
+	if (val == 2)
+		panic("missing workaround");
+	return clks[val];
+}
+
+unsigned long ltq_vr9_fpi_hz(void)
+{
+	long clks[] = {
+		CLOCK_62_5M, CLOCK_62_5M, CLOCK_83_5M, CLOCK_125M,
+		CLOCK_125M, CLOCK_125M, CLOCK_167M, CLOCK_200M,
+		CLOCK_250M, CLOCK_300M, CLOCK_62_5M, CLOCK_98_304M,
+		CLOCK_150M, CLOCK_196_608M };
+	int val = ((ltq_cgu_r32(LTQ_CGU_IF_CLK_VR9) >> 25) & 0xf);
+
+	if (val > 13)
+		panic("bad fpi speed");
+	return clks[val];
+}
+
+unsigned long ltq_vr9_io_region_clock(void)
+{
+	return ltq_vr9_fpi_hz() / 2;
+}
+
+unsigned long ltq_vr9_fpi_bus_clock(int fpi)
+{
+	return ltq_vr9_fpi_hz();
+}
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 38c122f..879c89a 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -8,17 +8,48 @@
 
 #include <linux/ioport.h>
 #include <linux/export.h>
+#include <linux/clkdev.h>
 
 #include <lantiq_soc.h>
 
+#include "../clk.h"
 #include "../devices.h"
 
 /* clock control register */
 #define LTQ_CGU_IFCCR	0x0018
+/* system clock register */
+#define LTQ_CGU_SYS     0x0010
 
 /* the enable / disable registers */
 #define LTQ_PMU_PWDCR	0x1C
 #define LTQ_PMU_PWDSR	0x20
+#define LTQ_PMU_PWDCR1	0x24
+#define LTQ_PMU_PWDSR1	0x28
+
+#define PWDCR(x) ((x) ? (LTQ_PMU_PWDCR1) : (LTQ_PMU_PWDCR))
+#define PWDSR(x) ((x) ? (LTQ_PMU_PWDSR1) : (LTQ_PMU_PWDSR))
+
+/* CGU - clock generation unit */
+#define CGU_EPHY		0x10
+
+/* PMU - power management unit */
+#define PMU_DMA			0x0020
+#define PMU_SPI			0x0100
+#define PMU_EPHY		0x0080
+#define PMU_USB			0x8041
+#define PMU_STP			0x0800
+#define PMU_GPT			0x1000
+#define PMU_PPE			0x2000
+#define PMU_FPI			0x4000
+#define PMU_SWITCH		0x10000000
+#define PMU_AHBS		0x2000
+#define PMU_AHBM		0x8000
+#define PMU_PCIE_CLK            0x80000000
+
+#define PMU1_PCIE_PHY		0x0001
+#define PMU1_PCIE_CTL		0x0002
+#define PMU1_PCIE_MSI		0x0020
+#define PMU1_PCIE_PDI		0x0010
 
 #define ltq_pmu_w32(x, y)	ltq_w32((x), ltq_pmu_membase + (y))
 #define ltq_pmu_r32(x)		ltq_r32(ltq_pmu_membase + (x))
@@ -36,28 +67,63 @@ void __iomem *ltq_cgu_membase;
 void __iomem *ltq_ebu_membase;
 static void __iomem *ltq_pmu_membase;
 
-void ltq_cgu_enable(unsigned int clk)
+static int ltq_cgu_enable(struct clk *clk)
 {
-	ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR);
+	ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk->bits, LTQ_CGU_IFCCR);
+	return 0;
 }
 
-void ltq_pmu_enable(unsigned int module)
+static void ltq_cgu_disable(struct clk *clk)
+{
+	ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~clk->bits, LTQ_CGU_IFCCR);
+}
+
+static int ltq_pmu_enable(struct clk *clk)
 {
 	int err = 1000000;
 
-	ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
-	do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
+	ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) & ~clk->bits,
+		PWDCR(clk->module));
+	do {} while (--err && (ltq_pmu_r32(PWDSR(clk->module)) & clk->bits));
 
 	if (!err)
 		panic("activating PMU module failed!");
+
+	return 0;
 }
-EXPORT_SYMBOL(ltq_pmu_enable);
 
-void ltq_pmu_disable(unsigned int module)
+static void ltq_pmu_disable(struct clk *clk)
 {
-	ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
+	ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | clk->bits, LTQ_PMU_PWDCR);
+}
+
+static inline void clkdev_add_pmu(const char *dev, const char *con,
+	unsigned int module, unsigned int bits)
+{
+	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+	clk->cl.dev_id = dev;
+	clk->cl.con_id = con;
+	clk->cl.clk = clk;
+	clk->enable = ltq_pmu_enable;
+	clk->disable = ltq_pmu_disable;
+	clk->module = module;
+	clk->bits = bits;
+	clkdev_add(&clk->cl);
+}
+
+static inline void clkdev_add_cgu(const char *con, unsigned int bits)
+{
+	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+	clk->cl.dev_id = "fpi";
+	clk->cl.con_id = con;
+	clk->cl.clk = clk;
+	clk->enable = ltq_cgu_enable;
+	clk->disable = ltq_cgu_disable;
+	clk->bits = bits;
+	clkdev_add(&clk->cl);
 }
-EXPORT_SYMBOL(ltq_pmu_disable);
 
 void __init ltq_soc_init(void)
 {
@@ -75,4 +141,26 @@ void __init ltq_soc_init(void)
 
 	/* make sure to unprotect the memory region where flash is located */
 	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
+
+	/* add our clocks */
+	if (ltq_is_ase()) {
+		if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
+			clkdev_add_static("cpu", CLOCK_266M);
+		else
+			clkdev_add_static("cpu", CLOCK_133M);
+		clkdev_add_static("fpi", CLOCK_133M);
+		clkdev_add_static("io", CLOCK_133M);
+		clkdev_add_cgu("ephycgu", CGU_EPHY),
+		clkdev_add_pmu("fpi", "ephy", 0, PMU_EPHY);
+	} else {
+		clkdev_add_static("cpu", ltq_danube_cpu_hz());
+		clkdev_add_static("fpi", ltq_danube_fpi_hz());
+		clkdev_add_static("io", ltq_danube_io_region_clock());
+		if (ltq_is_ar9())
+			clkdev_add_pmu("fpi", "switch", 0, PMU_SWITCH);
+	}
+	clkdev_add_pmu("fpi", "dma", 0, PMU_DMA);
+	clkdev_add_pmu("fpi", "stp", 0, PMU_STP);
+	clkdev_add_pmu("fpi", "spi", 0, PMU_SPI);
+	clkdev_add_pmu("fpi", "ppe", 0, PMU_PPE);
 }
-- 
1.7.7.1

[PATCH 4/9] MIPS: lantiq: convert falcon to clkdev api

[John Crispin]

Unify prom/clock code and add clkdev hooks to sysctrl.c

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 .../include/asm/mach-lantiq/falcon/lantiq_soc.h    |    8 +-
 arch/mips/lantiq/falcon/Makefile                   |    2 +-
 arch/mips/lantiq/falcon/clk.c                      |   44 -------
 arch/mips/lantiq/falcon/sysctrl.c                  |  131 ++++++++++++--------
 4 files changed, 82 insertions(+), 103 deletions(-)
 delete mode 100644 arch/mips/lantiq/falcon/clk.c

diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index 1a4b836..59c4f56 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -95,6 +95,7 @@
 
 /* Activation Status Register */
 #define ACTS_ASC1_ACT	0x00000800
+#define ACTS_I2C_ACT	0x00004000
 #define ACTS_P0		0x00010000
 #define ACTS_P1		0x00010000
 #define ACTS_P2		0x00020000
@@ -106,13 +107,6 @@
 #define ACTS_PADCTRL3	0x00200000
 #define ACTS_PADCTRL4	0x00400000
 
-extern void ltq_sysctl_activate(int module, unsigned int mask);
-extern void ltq_sysctl_deactivate(int module, unsigned int mask);
-extern void ltq_sysctl_clken(int module, unsigned int mask);
-extern void ltq_sysctl_clkdis(int module, unsigned int mask);
-extern void ltq_sysctl_reboot(int module, unsigned int mask);
-extern int ltq_gpe_is_activated(unsigned int mask);
-
 /* global register ranges */
 extern void __iomem *ltq_ebu_membase;
 extern void __iomem *ltq_sys1_membase;
diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
index 56b22eb..3634154 100644
--- a/arch/mips/lantiq/falcon/Makefile
+++ b/arch/mips/lantiq/falcon/Makefile
@@ -1,2 +1,2 @@
-obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
+obj-y := prom.o reset.o sysctrl.o devices.o gpio.o
 obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c
deleted file mode 100644
index afe1b52..0000000
--- a/arch/mips/lantiq/falcon/clk.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/ioport.h>
-#include <linux/export.h>
-
-#include <lantiq_soc.h>
-
-#include "devices.h"
-
-/* CPU0 Clock Control Register */
-#define LTQ_SYS1_CPU0CC		0x0040
-/* clock divider bit */
-#define LTQ_CPU0CC_CPUDIV	0x0001
-
-unsigned int
-ltq_get_io_region_clock(void)
-{
-	return CLOCK_200M;
-}
-EXPORT_SYMBOL(ltq_get_io_region_clock);
-
-unsigned int
-ltq_get_cpu_hz(void)
-{
-	if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
-		return CLOCK_200M;
-	else
-		return CLOCK_400M;
-}
-EXPORT_SYMBOL(ltq_get_cpu_hz);
-
-unsigned int
-ltq_get_fpi_hz(void)
-{
-	return CLOCK_100M;
-}
-EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index 905a142..08eca20 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -9,11 +9,13 @@
 
 #include <linux/ioport.h>
 #include <linux/export.h>
+#include <linux/clkdev.h>
 #include <asm/delay.h>
 
 #include <lantiq_soc.h>
 
 #include "devices.h"
+#include "../clk.h"
 
 /* infrastructure control register */
 #define SYS1_INFRAC		0x00bc
@@ -38,6 +40,10 @@
 #define LTQ_SYSCTL_DEACT	0x0028
 /* reboot Register */
 #define LTQ_SYSCTL_RBT		0x002c
+/* CPU0 Clock Control Register */
+#define LTQ_SYS1_CPU0CC         0x0040
+/* clock divider bit */
+#define LTQ_CPU0CC_CPUDIV       0x0001
 
 static struct resource ltq_sysctl_res[] = {
 	MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE),
@@ -64,79 +70,67 @@ void __iomem *ltq_ebu_membase;
 #define ltq_status_r32(x)	ltq_r32(ltq_status_membase + (x))
 
 static inline void
-ltq_sysctl_wait(int module, unsigned int mask,
+ltq_sysctl_wait(struct clk *clk,
 		unsigned int test, unsigned int reg)
 {
 	int err = 1000000;
 
-	do {} while (--err && ((ltq_reg_r32(module, reg)
-					& mask) != test));
+	do {} while (--err && ((ltq_reg_r32(clk->module, reg)
+					& clk->bits) != test));
 	if (!err)
-		pr_err("module de/activation failed %d %08X %08X\n",
-							module, mask, test);
+		pr_err("module de/activation failed %d %08X %08X %08X\n",
+				clk->module, clk->bits, test,
+				ltq_reg_r32(clk->module, reg) & clk->bits);
 }
 
-void
-ltq_sysctl_activate(int module, unsigned int mask)
+static int
+ltq_sysctl_activate(struct clk *clk)
 {
-	if (module > SYSCTL_SYSGPE)
-		return;
-
-	ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
-	ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT);
-	ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
+	ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN);
+	ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_ACT);
+	ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS);
+	return 0;
 }
-EXPORT_SYMBOL(ltq_sysctl_activate);
 
-void
-ltq_sysctl_deactivate(int module, unsigned int mask)
+static void
+ltq_sysctl_deactivate(struct clk *clk)
 {
-	if (module > SYSCTL_SYSGPE)
-		return;
-
-	ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
-	ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT);
-	ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS);
+	ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR);
+	ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_DEACT);
+	ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_ACTS);
 }
-EXPORT_SYMBOL(ltq_sysctl_deactivate);
 
-void
-ltq_sysctl_clken(int module, unsigned int mask)
+static int
+ltq_sysctl_clken(struct clk *clk)
 {
-	if (module > SYSCTL_SYSGPE)
-		return;
-
-	ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
-	ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS);
+	ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN);
+	ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_CLKS);
+	return 0;
 }
-EXPORT_SYMBOL(ltq_sysctl_clken);
 
-void
-ltq_sysctl_clkdis(int module, unsigned int mask)
+static void
+ltq_sysctl_clkdis(struct clk *clk)
 {
-	if (module > SYSCTL_SYSGPE)
-		return;
-
-	ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
-	ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS);
+	ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR);
+	ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_CLKS);
 }
-EXPORT_SYMBOL(ltq_sysctl_clkdis);
 
-void
-ltq_sysctl_reboot(int module, unsigned int mask)
+static void
+ltq_sysctl_reboot(struct clk *clk)
 {
 	unsigned int act;
-
-	if (module > SYSCTL_SYSGPE)
-		return;
-
-	act = ltq_reg_r32(module, LTQ_SYSCTL_ACT);
-	if ((~act & mask) != 0)
-		ltq_sysctl_activate(module, ~act & mask);
-	ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT);
-	ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
+	unsigned int bits;
+
+	act = ltq_reg_r32(clk->module, LTQ_SYSCTL_ACT);
+	bits = ~act & clk->bits;
+	if (bits != 0) {
+		ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_CLKEN);
+		ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_ACT);
+		ltq_sysctl_wait(clk, bits, LTQ_SYSCTL_ACTS);
+	}
+	ltq_reg_w32(clk->module, act & clk->bits, LTQ_SYSCTL_RBT);
+	ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS);
 }
-EXPORT_SYMBOL(ltq_sysctl_reboot);
 
 /* enable the ONU core */
 static void
@@ -167,6 +161,24 @@ ltq_gpe_enable(void)
 	udelay(1);
 }
 
+static inline void
+clkdev_add_sys(const char *dev, unsigned int module,
+				unsigned int bits)
+{
+	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+	clk->cl.dev_id = dev;
+	clk->cl.con_id = NULL;
+	clk->cl.clk = clk;
+	clk->module = module;
+	clk->activate = ltq_sysctl_activate;
+	clk->deactivate = ltq_sysctl_deactivate;
+	clk->enable = ltq_sysctl_clken;
+	clk->disable = ltq_sysctl_clkdis;
+	clk->reboot = ltq_sysctl_reboot;
+	clkdev_add(&clk->cl);
+}
+
 void __init
 ltq_soc_init(void)
 {
@@ -180,4 +192,21 @@ ltq_soc_init(void)
 	ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_res);
 
 	ltq_gpe_enable();
+
+	/* get our 3 static rates for cpu, fpi and io clocks */
+	if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
+		clkdev_add_static("cpu", CLOCK_200M);
+	else
+		clkdev_add_static("cpu", CLOCK_400M);
+	clkdev_add_static("fpi", CLOCK_100M);
+	clkdev_add_static("io", CLOCK_200M);
+
+	/* add our clock domains */
+	clkdev_add_sys("gpio0", SYSCTL_SYSETH, ACTS_PADCTRL0 | ACTS_P0);
+	clkdev_add_sys("gpio1", SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1);
+	clkdev_add_sys("gpio2", SYSCTL_SYSETH, ACTS_PADCTRL2 | ACTS_P2);
+	clkdev_add_sys("gpio3", SYSCTL_SYS1, ACTS_PADCTRL3 | ACTS_P3);
+	clkdev_add_sys("gpio4", SYSCTL_SYS1, ACTS_PADCTRL4 | ACTS_P4);
+	clkdev_add_sys("i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
+	clkdev_add_sys("asc-debug", SYSCTL_SYS1, ACTS_ASC1_ACT);
 }
-- 
1.7.7.1

[PATCH 5/9] MIPS: lantiq: convert dma driver to clkdev api

[John Crispin]

Update from old pmu_{dis,en}able() to ckldev api.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/xway/dma.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index 6cf883b..ed04da9 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -20,6 +20,7 @@
 #include <linux/io.h>
 #include <linux/dma-mapping.h>
 #include <linux/export.h>
+#include <linux/clk.h>
 
 #include <lantiq_soc.h>
 #include <xway_dma.h>
@@ -216,6 +217,7 @@ EXPORT_SYMBOL_GPL(ltq_dma_init_port);
 int __init
 ltq_dma_init(void)
 {
+	struct clk *clk;
 	int i;
 
 	/* remap dma register range */
@@ -224,7 +226,8 @@ ltq_dma_init(void)
 		panic("Failed to remap dma memory");
 
 	/* power up and reset the dma engine */
-	ltq_pmu_enable(PMU_DMA);
+	clk = clk_get_sys("fpi", "dma");
+	clk_enable(clk);
 	ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
 
 	/* disable all interrupts */
-- 
1.7.7.1

[PATCH 6/9] MIPS: lantiq: convert gpio_stp driver to clkdev api

[John Crispin]

Update from old pmu_{dis,en}able() to ckldev api.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/xway/gpio_stp.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
index e6b4809..c9bf38b 100644
--- a/arch/mips/lantiq/xway/gpio_stp.c
+++ b/arch/mips/lantiq/xway/gpio_stp.c
@@ -15,6 +15,7 @@
 #include <linux/mutex.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/clk.h>
 
 #include <lantiq_soc.h>
 
@@ -80,6 +81,8 @@ static struct gpio_chip ltq_stp_chip = {
 
 static int ltq_stp_hw_init(void)
 {
+	struct clk *clk;
+
 	/* sane defaults */
 	ltq_stp_w32(0, LTQ_STP_AR);
 	ltq_stp_w32(0, LTQ_STP_CPU0);
@@ -105,7 +108,8 @@ static int ltq_stp_hw_init(void)
 	 */
 	ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0);
 
-	ltq_pmu_enable(PMU_LED);
+	clk = clk_get_sys("fpi", "stp");
+	clk_enable(clk);
 	return 0;
 }
 
-- 
1.7.7.1

[PATCH 7/9] SERIAL: MIPS: lantiq: convert serial driver to clkdev api

[John Crispin]

Update from old pmu_{dis,en}able() to ckldev api.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-serial@vger.kernel.org
---
This patch should go via MIPS with the rest of the series.

 drivers/tty/serial/lantiq.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index 96c1cac..136dae8 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -686,7 +686,7 @@ lqasc_probe(struct platform_device *pdev)
 	if (lqasc_port[pdev->id] != NULL)
 		return -EBUSY;
 
-	clk = clk_get(&pdev->dev, "fpi");
+	clk = clk_get_sys("fpi", NULL);
 	if (IS_ERR(clk)) {
 		pr_err("failed to get fpi clk\n");
 		return -ENOENT;
-- 
1.7.7.1

[PATCH 8/9] NET: MIPS: lantiq: convert etop driver to clkdev api

[John Crispin]

Update from old pmu_{dis,en}able() to ckldev api.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: netdev@vger.kernel.org
---
This patch should go via MIPS with the rest of the series.

 drivers/net/ethernet/lantiq_etop.c |   27 ++++++++++++++++++++++-----
 1 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index 80ce6d9..fa2580b 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -36,6 +36,7 @@
 #include <linux/io.h>
 #include <linux/dma-mapping.h>
 #include <linux/module.h>
+#include <linux/clk.h>
 
 #include <asm/checksum.h>
 
@@ -278,10 +279,18 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
 static void
 ltq_etop_hw_exit(struct net_device *dev)
 {
+	struct clk *clk;
 	struct ltq_etop_priv *priv = netdev_priv(dev);
 	int i;
 
-	ltq_pmu_disable(PMU_PPE);
+	clk = clk_get_sys("ppe", NULL);
+	clk_disable(clk);
+
+	if (ltq_has_gbit()) {
+		clk = clk_get_sys("fpi", "switch");
+		clk_disable(clk);
+	}
+
 	for (i = 0; i < MAX_DMA_CHAN; i++)
 		if (IS_TX(i) || IS_RX(i))
 			ltq_etop_free_channel(dev, &priv->ch[i]);
@@ -290,7 +299,10 @@ ltq_etop_hw_exit(struct net_device *dev)
 static void
 ltq_etop_gbit_init(void)
 {
-	ltq_pmu_enable(PMU_SWITCH);
+	struct clk *clk;
+
+	clk = clk_get_sys("fpi", "switch");
+	clk_enable(clk);
 
 	ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
 	/** Disable MDIO auto polling mode */
@@ -312,8 +324,10 @@ ltq_etop_hw_init(struct net_device *dev)
 	unsigned int mii_mode = priv->pldata->mii_mode;
 	int err = 0;
 	int i;
+	struct clk *clk;
 
-	ltq_pmu_enable(PMU_PPE);
+	clk = clk_get_sys("fpi", "ppe");
+	clk_enable(clk);
 
 	if (ltq_has_gbit()) {
 		ltq_etop_gbit_init();
@@ -334,11 +348,14 @@ ltq_etop_hw_init(struct net_device *dev)
 
 	default:
 		if (ltq_is_ase()) {
-			ltq_pmu_enable(PMU_EPHY);
+			clk = clk_get_sys("fpi", "ephy");
+			clk_enable(clk);
+
 			/* disable external MII */
 			ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
 			/* enable clock for internal PHY */
-			ltq_cgu_enable(CGU_EPHY);
+			clk = clk_get_sys("fpi", "ephycgu");
+			clk_enable(clk);
 			/* we need to write this magic to the internal phy to
 			   make it work */
 			ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
-- 
1.7.7.1

[PATCH 9/9] WDT: MIPS: lantiq: convert watchdog driver to clkdev api

[John Crispin]

Update from old pmu_{dis,en}able() to ckldev api.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-watchdog@vger.kernel.org
---
This patch should go via MIPS with the rest of the series.

 drivers/watchdog/lantiq_wdt.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
index 9c8b10c..05646b8 100644
--- a/drivers/watchdog/lantiq_wdt.c
+++ b/drivers/watchdog/lantiq_wdt.c
@@ -206,7 +206,7 @@ ltq_wdt_probe(struct platform_device *pdev)
 	}
 
 	/* we do not need to enable the clock as it is always running */
-	clk = clk_get(&pdev->dev, "io");
+	clk = clk_get_sys("io", NULL);
 	WARN_ON(!clk);
 	ltq_io_region_clk_rate = clk_get_rate(clk);
 	clk_put(clk);
-- 
1.7.7.1

Re: [PATCH 9/9] WDT: MIPS: lantiq: convert watchdog driver to clkdev api

[John Crispin]

Hi Sergei,
> ( The comment doesn't match the essence of patch. )

> Again, you're doing something different.
>

sorry

>    Why not clk_get(&pdev->dev, NULL)?
>
> WBR, Sergei
>
>

clk_get_sys uses the clkdev lookup table, which is added by this series.
it makes the clock code consistent throughout the lantiq related files.
we use clk connections other places, which we cannot reference with
clk_get that easily

John

Re: [PATCH 7/9] SERIAL: MIPS: lantiq: convert serial driver to clkdev api

[John Crispin]

Hi Sergei,

>    The comment doesn't match the essence of patch.
>

sorry

>    Why not just clk_get(&pdev->dev, NULL)?
>
> WBR, Sergei
>


clk_get_sys uses the clkdev lookup table, which is added by this series.
it makes the clock code consistent throughout the lantiq related files.
we use clk connections other places, which we cannot reference with
clk_get that easily

John

Re: [PATCH 7/9] SERIAL: MIPS: lantiq: convert serial driver to clkdev api

[Sergei Shtylyov]

Hello.

On 02/17/2012 01:33 PM, John Crispin wrote:

> Update from old pmu_{dis,en}able() to ckldev api.

    The comment doesn't match the essence of patch.

> Signed-off-by: John Crispin<blogic@openwrt.org>
> Cc: linux-serial@vger.kernel.org
> ---
> This patch should go via MIPS with the rest of the series.

>   drivers/tty/serial/lantiq.c |    2 +-
>   1 files changed, 1 insertions(+), 1 deletions(-)

> diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
> index 96c1cac..136dae8 100644
> --- a/drivers/tty/serial/lantiq.c
> +++ b/drivers/tty/serial/lantiq.c
> @@ -686,7 +686,7 @@ lqasc_probe(struct platform_device *pdev)
>   	if (lqasc_port[pdev->id] != NULL)
>   		return -EBUSY;
>
> -	clk = clk_get(&pdev->dev, "fpi");
> +	clk = clk_get_sys("fpi", NULL);

    Why not just clk_get(&pdev->dev, NULL)?

WBR, Sergei

Re: [PATCH 9/9] WDT: MIPS: lantiq: convert watchdog driver to clkdev api

[Sergei Shtylyov]

Hello.

On 02/17/2012 01:33 PM, John Crispin wrote:

> Update from old pmu_{dis,en}able() to ckldev api.

   Again, you're doing something different.

> Signed-off-by: John Crispin<blogic@openwrt.org>
> Cc: linux-watchdog@vger.kernel.org
> ---
> This patch should go via MIPS with the rest of the series.
>
>   drivers/watchdog/lantiq_wdt.c |    2 +-
>   1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
> index 9c8b10c..05646b8 100644
> --- a/drivers/watchdog/lantiq_wdt.c
> +++ b/drivers/watchdog/lantiq_wdt.c
> @@ -206,7 +206,7 @@ ltq_wdt_probe(struct platform_device *pdev)
>   	}
>
>   	/* we do not need to enable the clock as it is always running */
> -	clk = clk_get(&pdev->dev, "io");
> +	clk = clk_get_sys("io", NULL);

    Why not clk_get(&pdev->dev, NULL)?

WBR, Sergei

Re: [PATCH 7/9] SERIAL: MIPS: lantiq: convert serial driver to clkdev api

[Sergei Shtylyov]

Hello.

On 02/17/2012 07:47 PM, John Crispin wrote:

>>     The comment doesn't match the essence of patch.

> sorry

>>     Why not just clk_get(&pdev->dev, NULL)?

>> WBR, Sergei

> clk_get_sys uses the clkdev lookup table, which is added by this series.

    clk_get() does the same, indirectly.

> it makes the clock code consistent throughout the lantiq related files.
> we use clk connections other places, which we cannot reference with
> clk_get that easily

    clkdev assumes you don't need to use connection ID if the clock is bound to 
be matched by device ID via the lookup table. clk_get() is a common case when 
using clkdev, that's why your use of clk_get_sys() stands out as something 
unusual. I'll have to have a look at your lookup tables...

> John

WBR, Sergei