[Qemu-devel] [PATCH 0/7] cpu model bug fixes and definition corrections (v3)

[Qemu-devel] [PATCH 0/7] cpu model bug fixes and definition corrections (v3)

[Eduardo Habkost]

These are patches based on a series that John Cooper sent back in May 2011, and
that I resent last June. Not all changes from that series are here, but just
the most obvious ones.

The previous submission of this series is:
Message-Id: <1307041990-26194-1-git-send-email-ehabkost@redhat.com>
http://marc.info/?l=qemu-devel&m=130704282917358

Eduardo Habkost (7):
  cpu models: reorder flag list to match bit order
  cpu flags: aliases: pclmuldq|pclmulqdq and ffxsr|fxsr_opt
  cpu defs: use Intel flag names for Intel models (v2)
  cpu defs: add pse36, mca, mtrr to AMD CPU definitions (v2)
  cpu defs: remove replicated flags from Intel (v2)
  add Westmere as a qemu cpu model (v2)
  cpu defs: uncomment empty extfeatures_ecx definition for Opteron_G1
    (v2)

 sysconfigs/target/target-x86_64.conf |   52 +++++++++++++++++++++------------
 target-i386/cpuid.c                  |    8 ++--
 2 files changed, 37 insertions(+), 23 deletions(-)

-- 
1.7.3.2

[Qemu-devel] [PATCH 1/7] cpu models: reorder flag list to match bit order

[Eduardo Habkost]

This will make it easier to review and change the flag list in the future.

No behaviour change should be introduced by this, as it is just changing
the flag order on the config file.

To make sure the flag sets are really not changed by this patch, I have
used the following stupid script to compare the flag values in the
config files:
https://gist.github.com/1004885

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 sysconfigs/target/target-x86_64.conf |   36 +++++++++++++++++-----------------
 1 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index 43ad282..6720778 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -7,9 +7,9 @@
    family = "6"
    model = "2"
    stepping = "3"
-   feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu    mtrr clflush mca pse36"
-   feature_ecx = "sse3 ssse3"
-   extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu    lm syscall nx"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "ssse3 sse3"
+   extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
    extfeature_ecx = "lahf_lm"
    xlevel = "0x8000000A"
    model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"
@@ -21,9 +21,9 @@
    family = "6"
    model = "2"
    stepping = "3"
-   feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu    mtrr clflush mca pse36"
-   feature_ecx = "sse3 cx16 ssse3 sse4.1"
-   extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu    lm syscall nx"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "sse4.1 cx16 ssse3 sse3"
+   extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
    extfeature_ecx = "lahf_lm"
    xlevel = "0x8000000A"
    model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"
@@ -35,9 +35,9 @@
    family = "6"
    model = "2"
    stepping = "3"
-   feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu    mtrr clflush mca pse36"
-   feature_ecx = "sse3 cx16 ssse3 sse4.1 sse4.2 popcnt"
-   extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu    lm syscall nx"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
+   extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
    extfeature_ecx = "lahf_lm"
    xlevel = "0x8000000A"
    model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
@@ -49,9 +49,9 @@
    family = "15"
    model = "6"
    stepping = "1"
-   feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu    mtrr clflush mca pse36"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
    feature_ecx = "sse3"
-   extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu    lm syscall nx"
+   extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
 #   extfeature_ecx = ""
    xlevel = "0x80000008"
    model_id = "AMD Opteron 240 (Gen 1 Class Opteron)"
@@ -63,9 +63,9 @@
    family = "15"
    model = "6"
    stepping = "1"
-   feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu    mtrr clflush mca pse36"
-   feature_ecx = "sse3 cx16"
-   extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu    lm syscall nx rdtscp"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "cx16 sse3"
+   extfeature_edx = "lm rdtscp fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
    extfeature_ecx = "svm lahf_lm"
    xlevel = "0x80000008"
    model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)"
@@ -77,10 +77,10 @@
    family = "15"
    model = "6"
    stepping = "1"
-   feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu    mtrr clflush mca pse36"
-   feature_ecx = "sse3 cx16 monitor popcnt"
-   extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu    lm syscall nx rdtscp"
-   extfeature_ecx = "svm sse4a  abm misalignsse lahf_lm"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "popcnt cx16 monitor sse3"
+   extfeature_edx = "lm rdtscp fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_ecx = "misalignsse sse4a abm svm lahf_lm"
    xlevel = "0x80000008"
    model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)"
 
-- 
1.7.3.2

[Qemu-devel] [PATCH 2/7] cpu flags: aliases: pclmuldq|pclmulqdq and ffxsr|fxsr_opt

[Eduardo Habkost]

pclmulqdq: /proc/cpuinfo on Linux and all documentation I have seen uses
pclmulqdq as the flag name. As the only document using pclmuldq seems to
be the Intel CPUID documentation (Application Note 485), it looks like a
typo and not the correct name for the flag.

ffxsr: AMD docs refer to fxsr_opt as ffxsr, so allow this named to be
used too.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 target-i386/cpuid.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c
index b9bfeaf..aa19260 100644
--- a/target-i386/cpuid.c
+++ b/target-i386/cpuid.c
@@ -44,7 +44,7 @@ static const char *feature_name[] = {
     "ht" /* Intel htt */, "tm", "ia64", "pbe",
 };
 static const char *ext_feature_name[] = {
-    "pni|sse3" /* Intel,AMD sse3 */, "pclmuldq", "dtes64", "monitor",
+    "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
     "ds_cpl", "vmx", "smx", "est",
     "tm2", "ssse3", "cid", NULL,
     "fma", "cx16", "xtpr", "pdcm",
@@ -60,7 +60,7 @@ static const char *ext2_feature_name[] = {
     "mtrr", "pge", "mca", "cmov",
     "pat", "pse36", NULL, NULL /* Linux mp */,
     "nx" /* Intel xd */, NULL, "mmxext", "mmx",
-    "fxsr", "fxsr_opt" /* AMD ffxsr */, "pdpe1gb" /* AMD Page1GB */, "rdtscp",
+    "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
     NULL, "lm" /* Intel 64 */, "3dnowext", "3dnow",
 };
 static const char *ext3_feature_name[] = {
-- 
1.7.3.2

[Qemu-devel] [PATCH 3/7] cpu defs: use Intel flag names for Intel models (v2)

[Eduardo Habkost]

Use 'i64' instead of 'lm' and 'xd' instead of 'nx' on Intel models.

The flags have different names on Intel docs, so use those names for clarity.

This is based on a previous patch from John Cooper where this was introduced
with many other changes at the same time. Original John's patch submission is
at Message-ID: <4DDAD5E7.2020002@redhat.com>, <http://marc.info/?l=qemu-devel&m=130618871926030>.

Changes v1 -> v2:
 - Rebase patch against latest Qemu git tree

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 sysconfigs/target/target-x86_64.conf |    6 +++---
 target-i386/cpuid.c                  |    4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index 6720778..09b255e 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -9,7 +9,7 @@
    stepping = "3"
    feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
    feature_ecx = "ssse3 sse3"
-   extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
    extfeature_ecx = "lahf_lm"
    xlevel = "0x8000000A"
    model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"
@@ -23,7 +23,7 @@
    stepping = "3"
    feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
    feature_ecx = "sse4.1 cx16 ssse3 sse3"
-   extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
    extfeature_ecx = "lahf_lm"
    xlevel = "0x8000000A"
    model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"
@@ -37,7 +37,7 @@
    stepping = "3"
    feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
    feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
-   extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
    extfeature_ecx = "lahf_lm"
    xlevel = "0x8000000A"
    model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c
index aa19260..ace2a67 100644
--- a/target-i386/cpuid.c
+++ b/target-i386/cpuid.c
@@ -59,9 +59,9 @@ static const char *ext2_feature_name[] = {
     "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
     "mtrr", "pge", "mca", "cmov",
     "pat", "pse36", NULL, NULL /* Linux mp */,
-    "nx" /* Intel xd */, NULL, "mmxext", "mmx",
+    "nx|xd", NULL, "mmxext", "mmx",
     "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
-    NULL, "lm" /* Intel 64 */, "3dnowext", "3dnow",
+    NULL, "lm|i64", "3dnowext", "3dnow",
 };
 static const char *ext3_feature_name[] = {
     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
-- 
1.7.3.2

[Qemu-devel] [PATCH 4/7] cpu defs: add pse36, mca, mtrr to AMD CPU definitions (v2)

[Eduardo Habkost]

This patch adds some missing flags to extfeature_edx, that were missing
according to AMD's latest CPUID document.

This is based on a previous patch from John Cooper where this was introduced
with many other changes at the same time. Original John's patch submission is
at Message-ID: <4DDAD5E7.2020002@redhat.com>, <http://marc.info/?l=qemu-devel&m=130618871926030>.

Original John's patch description was:

    cpu model bug fixes and definition corrections

    This patch was intended to address the replicated feature
    flags in cpuid 8000_0001:edx from cpuid 0000_0001:edx.
    This is due to AMD's definition where these flags are
    mostly cloned in the 8000_0001:edx cpuid function.
    qemu64 attempted to glue together the respective Intel
    and AMD nearly disjoint features and this propagated to
    the new Intel models as doing so was believed conservative
    at the time.  However after further soak and test lugging
    around this cruft doesn't provide any value, could
    conceivably confuse a guest, and has confused users trying
    to maintain/add cpu definitions.  This also caused issues
    for libvirt attempting to track this mis-encoding.

    So we've here tossed out the AMD replicated definitions
    from the Intel models, added a few replications into AMD
    definitions which were missing according to AMD's latest
    CPUID document, and reordered the config file flags to
    follow intuitive sequential bit ordering.  Also two flag
    name aliases were added for clarity to Intel models.  The
    end result being the models definitions now conform to
    their respective cpuid specifications sans x2apic which is
    emulated by kvm.

    This was tested with the following combinations:

        [Conroe, Penryn, Nehalem] x [F12-64, win64, win32] -- Intel host
        [Opteron_G1, Opteron_G2, Opteron_G3] x [F12-64, win64, win32] -- AMD host

    Yielding successful boots in all cases.

    Signed-off-by: john cooper <john.cooper@redhat.com>

Changes v1 -> v2:
 - Rebase against latest Qemu git tree

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 sysconfigs/target/target-x86_64.conf |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index 09b255e..0e57d9c 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -51,7 +51,7 @@
    stepping = "1"
    feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
    feature_ecx = "sse3"
-   extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_edx = "lm fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
 #   extfeature_ecx = ""
    xlevel = "0x80000008"
    model_id = "AMD Opteron 240 (Gen 1 Class Opteron)"
@@ -65,7 +65,7 @@
    stepping = "1"
    feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
    feature_ecx = "cx16 sse3"
-   extfeature_edx = "lm rdtscp fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
    extfeature_ecx = "svm lahf_lm"
    xlevel = "0x80000008"
    model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)"
@@ -79,7 +79,7 @@
    stepping = "1"
    feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
    feature_ecx = "popcnt cx16 monitor sse3"
-   extfeature_edx = "lm rdtscp fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
    extfeature_ecx = "misalignsse sse4a abm svm lahf_lm"
    xlevel = "0x80000008"
    model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)"
-- 
1.7.3.2

[Qemu-devel] [PATCH 5/7] cpu defs: remove replicated flags from Intel (v2)

[Eduardo Habkost]

This patch removes the replicated feature flags from cpuid 8000_0001:edx
(extfeature_edx) from Intel models, as the duplicated feature flags are present
only on AMD CPUs. On Intel models, only the i64, syscall, and xd flags are kept
on extfeature_edx.

This is based on a previous patch from John Cooper where this was introduced
with many other changes at the same time. Original John's patch submission is
at Message-ID: <4DDAD5E7.2020002@redhat.com>, <http://marc.info/?l=qemu-devel&m=130618871926030>.

Original John's patch description was:

    cpu model bug fixes and definition corrections

    This patch was intended to address the replicated feature
    flags in cpuid 8000_0001:edx from cpuid 0000_0001:edx.
    This is due to AMD's definition where these flags are
    mostly cloned in the 8000_0001:edx cpuid function.
    qemu64 attempted to glue together the respective Intel
    and AMD nearly disjoint features and this propagated to
    the new Intel models as doing so was believed conservative
    at the time.  However after further soak and test lugging
    around this cruft doesn't provide any value, could
    conceivably confuse a guest, and has confused users trying
    to maintain/add cpu definitions.  This also caused issues
    for libvirt attempting to track this mis-encoding.

    So we've here tossed out the AMD replicated definitions
    from the Intel models, added a few replications into AMD
    definitions which were missing according to AMD's latest
    CPUID document, and reordered the config file flags to
    follow intuitive sequential bit ordering.  Also two flag
    name aliases were added for clarity to Intel models.  The
    end result being the models definitions now conform to
    their respective cpuid specifications sans x2apic which is
    emulated by kvm.

    This was tested with the following combinations:

        [Conroe, Penryn, Nehalem] x [F12-64, win64, win32] -- Intel host
        [Opteron_G1, Opteron_G2, Opteron_G3] x [F12-64, win64, win32] -- AMD host

    Yielding successful boots in all cases.

    Signed-off-by: john cooper <john.cooper@redhat.com>

Changes v1 -> v2:
 - Rebase against latest Qemu git tree

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 sysconfigs/target/target-x86_64.conf |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index 0e57d9c..96e32e0 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -9,7 +9,7 @@
    stepping = "3"
    feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
    feature_ecx = "ssse3 sse3"
-   extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_edx = "i64 xd syscall"
    extfeature_ecx = "lahf_lm"
    xlevel = "0x8000000A"
    model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"
@@ -23,7 +23,7 @@
    stepping = "3"
    feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
    feature_ecx = "sse4.1 cx16 ssse3 sse3"
-   extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_edx = "i64 xd syscall"
    extfeature_ecx = "lahf_lm"
    xlevel = "0x8000000A"
    model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"
@@ -37,7 +37,7 @@
    stepping = "3"
    feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
    feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
-   extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_edx = "i64 syscall xd"
    extfeature_ecx = "lahf_lm"
    xlevel = "0x8000000A"
    model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
-- 
1.7.3.2

[Qemu-devel] [PATCH 6/7] add Westmere as a qemu cpu model (v2)

[Eduardo Habkost]

Version 1 of this patch was:

Message-Id: <1307041990-26194-11-git-send-email-ehabkost@redhat.com
http://marc.info/?l=qemu-devel&m=130704415919346

This version doesn't have the duplicate feature bits on extfeature_edx, though,
as they are being removed from the Intel models (as they are reserved bits on
Intel CPUs).

Version 1 patch description:

    This patch adds Westmere as a qemu cpu model.  The only
    additional guest visible feature of a Westmere relative
    to Nehalem is the inclusion of AES instructions.  However
    as other non-ABI visible modifications exist along with
    fabrication changes, the CPUID data of the corresponding
    deployed silicon was altered slightly to reflect this.

    We've seen isolated cases where apparently unrelated yet
    slightly incoherent CPUID data has caused problems, most
    notably during guest boot.  Providing Westmere as a
    model separate fro Nehalem allows us to more easily address
    such quirks.

    [ehabkost: edited commit message to have a better Subject line]

    Signed-off-by: john cooper <john.cooper@redhat.com>
    Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>

Changes version 1 -> version 2:
 - Remove the duplicate feature bits on extfeature_edx, that are
   reserved on Intel CPUs
 - Reorder feature flags
 - Remove x2apic from the definition because x2apic requires some fixes
   that have to be resubmitted

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 sysconfigs/target/target-x86_64.conf |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index 96e32e0..dc1a3ea 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -43,6 +43,20 @@
    model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
 
 [cpudef]
+   name = "Westmere"
+   level = "11"
+   vendor = "GenuineIntel"
+   family = "6"
+   model = "44"
+   stepping = "1"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "aes popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
+   extfeature_edx = "i64 syscall xd"
+   extfeature_ecx = "lahf_lm"
+   xlevel = "0x8000000A"
+   model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)"
+
+[cpudef]
    name = "Opteron_G1"
    level = "5"
    vendor = "AuthenticAMD"
-- 
1.7.3.2

[Qemu-devel] [PATCH 7/7] cpu defs: uncomment empty extfeatures_ecx definition for Opteron_G1 (v2)

[Eduardo Habkost]

This should have no visible effect, but it should just clean up the
config file a bit.

This is based on a previous patch from John Cooper where this was introduced
with many other changes at the same time. Original John's patch submission is
at Message-ID: <4DDAD5E7.2020002@redhat.com>, <http://marc.info/?l=qemu-devel&m=130618871926030>.

Changes v1 -> v2:
 - Rebase against latest Qemu git tree

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 sysconfigs/target/target-x86_64.conf |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index dc1a3ea..d050380 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -66,7 +66,7 @@
    feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
    feature_ecx = "sse3"
    extfeature_edx = "lm fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
-#   extfeature_ecx = ""
+   extfeature_ecx = " "
    xlevel = "0x80000008"
    model_id = "AMD Opteron 240 (Gen 1 Class Opteron)"
 
-- 
1.7.3.2

Re: [Qemu-devel] [PATCH 0/7] cpu model bug fixes and definition corrections (v3)

[Anthony Liguori]

On 02/17/2012 10:41 AM, Eduardo Habkost wrote:
> These are patches based on a series that John Cooper sent back in May 2011, and
> that I resent last June. Not all changes from that series are here, but just
> the most obvious ones.
>
> The previous submission of this series is:
> Message-Id:<1307041990-26194-1-git-send-email-ehabkost@redhat.com>
> http://marc.info/?l=qemu-devel&m=130704282917358
>
> Eduardo Habkost (7):
>    cpu models: reorder flag list to match bit order
>    cpu flags: aliases: pclmuldq|pclmulqdq and ffxsr|fxsr_opt
>    cpu defs: use Intel flag names for Intel models (v2)
>    cpu defs: add pse36, mca, mtrr to AMD CPU definitions (v2)
>    cpu defs: remove replicated flags from Intel (v2)
>    add Westmere as a qemu cpu model (v2)
>    cpu defs: uncomment empty extfeatures_ecx definition for Opteron_G1
>      (v2)
>
>   sysconfigs/target/target-x86_64.conf |   52 +++++++++++++++++++++------------
>   target-i386/cpuid.c                  |    8 ++--
>   2 files changed, 37 insertions(+), 23 deletions(-)

Applied.  Thanks.

Regards,

Anthony Liguori

>