From: Andre Przywara <andre.przywara@amd.com>
To: Prateek Sharma <prateek3.14@gmail.com>
Cc: <kvm@vger.kernel.org>
Subject: Re: AMD SVM specification
Date: Mon, 27 Feb 2012 11:43:20 +0100 [thread overview]
Message-ID: <4F4B5E48.8020607@amd.com> (raw)
In-Reply-To: <CAKwxwqwtnuFx8Cw=C3VhSKjHrNmAvk4baeg2OW6XCtQ7Xx5srg@mail.gmail.com>
On 02/27/2012 11:09 AM, Prateek Sharma wrote:
> Hello,
> I know this is not the right forum for this, but i am looking for
> the recent specification/documentation of the AMD NPT and SVM
> features. All i can find is the old pacifica document dating back to
> 2005, and only the NPT whitepaper.
The technical SVM documentation is in the AMD64 Architecture
Programmer's Manual (APM) Volume 2:
http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf
SVM is detailed in chapter 15, with appendix B & C containing the needed
bits for the data structures. Other chapters in this document contain
details about paging, though this is mostly not AMD specific.
Regards,
Andre.
> The reason i seek this documentation is that i wish to modify some
> KVM code. Specifically, i am interested in how the hardware
> sets/resets the accessed/dirty bits of the guest/nested tables
> [https://lkml.org/lkml/2011/6/22/20]
>
> Any help will be appreciated.
>
> Prateek
--
Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany
prev parent reply other threads:[~2012-02-27 10:48 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-02-27 10:09 AMD SVM specification Prateek Sharma
2012-02-27 10:43 ` Andre Przywara [this message]
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