Re: [PATCH 2/2] i2c/designware: Provide optional i2c bus recovery function

[Michael Lawnick <ml.lawnick-Mmb7MZpHnFY@public.gmane.org>]

Am 29.02.2012 05:58, schrieb Viresh Kumar:
...
> It says that the hang situation is "SDA is stuck LOW" and 9 clock pulses should
> be enough to get it out of hang (Can somebody tell me how this figure of "9"
> derived?)

After 8 data bits there is direction change and ACK/NACK sent.
AFAICS the number of clocks needed:
The situation only occurs if slave was in read mode and drives a data-0.
It will (only) see a NACK when it has driven the rest of current bits,
fall back to idle and remaining cycles will be ignored.
If master stops on first data-1 of slave, slave might ignore changes on
SDA (iow start/stop flags) as it is still in read mode, i.e. driving
actively data and not listening to SDA.

> 
> SDA will become High, but what guarantees that this will not be low immediately
> after that, while we are reading SDA line? Or Is reading SDA line after 9 pulses
> sufficient?
...

SDA may not go low while clock is high. This would be a violation of
protocol. Except start/stop flag of master SDA transitions are always
done while clock is low.


HTH
-- 
Michael