* [Qemu-devel] [PATCH 1/7] pseries: Don't try to munmap() a malloc()ed TCE table
2012-02-28 3:18 [Qemu-devel] [0/7] pseries and Power updates David Gibson
@ 2012-02-28 3:18 ` David Gibson
2012-02-28 3:18 ` [Qemu-devel] [PATCH 2/7] PPC64: Add support for ldbrx and stdbrx instructions David Gibson
` (6 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: David Gibson @ 2012-02-28 3:18 UTC (permalink / raw)
To: agraf; +Cc: qemu-ppc, qemu-devel, anthony, David Gibson
For the pseries machine, TCE (IOMMU) tables can either be directly
malloc()ed in qemu or, when running on a KVM which supports it, mmap()ed
from a KVM ioctl. The latter option is used when available, because it
allows the (frequent bottlenext) H_PUT_TCE hypercall to be KVM accelerated.
However, even when KVM is persent, TCE acceleration is not always possible.
Only KVM HV supports this ioctl(), not KVM PR, or the kernel could run out
of contiguous memory to allocate the new table. In this case we need to
fall back on the malloc()ed table.
When a device is removed, and we need to remove the TCE table, we need to
either munmap() or free() the table as appropriate for how it was
allocated. The code is supposed to do that, but we buggily fail to
initialize the tcet->fd variable in the malloc() case, which is used as a
flag to determine which is the right choice.
This patch fixes the bug, and cleans up error messages relating to this
path while we're at it.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/kvm.c | 12 ++++++++++--
1 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 50cfa02..90c6941 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -843,12 +843,18 @@ void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd)
int fd;
void *table;
+ /* Must set fd to -1 so we don't try to munmap when called for
+ * destroying the table, which the upper layers -will- do
+ */
+ *pfd = -1;
if (!cap_spapr_tce) {
return NULL;
}
fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
if (fd < 0) {
+ fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
+ liobn);
return NULL;
}
@@ -857,6 +863,8 @@ void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd)
table = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
if (table == MAP_FAILED) {
+ fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
+ liobn);
close(fd);
return NULL;
}
@@ -876,8 +884,8 @@ int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t window_size)
len = (window_size / SPAPR_VIO_TCE_PAGE_SIZE)*sizeof(VIOsPAPR_RTCE);
if ((munmap(table, len) < 0) ||
(close(fd) < 0)) {
- fprintf(stderr, "KVM: Unexpected error removing KVM SPAPR TCE "
- "table: %s", strerror(errno));
+ fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
+ strerror(errno));
/* Leak the table */
}
--
1.7.9
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH 2/7] PPC64: Add support for ldbrx and stdbrx instructions
2012-02-28 3:18 [Qemu-devel] [0/7] pseries and Power updates David Gibson
2012-02-28 3:18 ` [Qemu-devel] [PATCH 1/7] pseries: Don't try to munmap() a malloc()ed TCE table David Gibson
@ 2012-02-28 3:18 ` David Gibson
2012-02-28 3:18 ` [Qemu-devel] [PATCH 3/7] pseries: Add support for level interrupts to XICS David Gibson
` (5 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: David Gibson @ 2012-02-28 3:18 UTC (permalink / raw)
To: agraf; +Cc: David Gibson, qemu-ppc, qemu-devel, anthony, Thomas Huth
From: Thomas Huth <thuth@linux.vnet.ibm.com>
These instructions for loading and storing byte-swapped 64-bit values have
been introduced in PowerISA 2.06.
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/cpu.h | 4 ++-
target-ppc/translate.c | 52 +++++++++++++++++++++++++++++++++++-------
target-ppc/translate_init.c | 2 +-
3 files changed, 47 insertions(+), 11 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index fbcf488..036b3b6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1918,8 +1918,10 @@ enum {
PPC2_DFP = 0x0000000000000004ULL,
/* Embedded.Processor Control */
PPC2_PRCNTL = 0x0000000000000008ULL,
+ /* Byte-reversed, indexed, double-word load and store */
+ PPC2_DBRX = 0x0000000000000010ULL,
-#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL)
+#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX)
};
/*****************************************************************************/
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b2780db..2728941 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2656,7 +2656,7 @@ static void glue(gen_, name##ux)(DisasContext *ctx)
tcg_temp_free(EA); \
}
-#define GEN_LDX(name, ldop, opc2, opc3, type) \
+#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
TCGv EA; \
@@ -2666,6 +2666,8 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
tcg_temp_free(EA); \
}
+#define GEN_LDX(name, ldop, opc2, opc3, type) \
+ GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
#define GEN_LDS(name, ldop, op, type) \
GEN_LD(name, ldop, op | 0x20, type); \
@@ -2799,8 +2801,8 @@ static void glue(gen_, name##ux)(DisasContext *ctx)
tcg_temp_free(EA); \
}
-#define GEN_STX(name, stop, opc2, opc3, type) \
-static void glue(gen_, name##x)(DisasContext *ctx) \
+#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
+static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
TCGv EA; \
gen_set_access_type(ctx, ACCESS_INT); \
@@ -2809,6 +2811,8 @@ static void glue(gen_, name##x)(DisasContext *ctx)
gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
tcg_temp_free(EA); \
}
+#define GEN_STX(name, stop, opc2, opc3, type) \
+ GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
#define GEN_STS(name, stop, op, type) \
GEN_ST(name, stop, op | 0x20, type); \
@@ -2897,6 +2901,18 @@ static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
}
GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
+#if defined(TARGET_PPC64)
+/* ldbrx */
+static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
+ if (likely(!ctx->le_mode)) {
+ tcg_gen_bswap64_tl(arg1, arg1);
+ }
+}
+GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
+#endif /* TARGET_PPC64 */
+
/* sthbrx */
static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
@@ -2927,6 +2943,22 @@ static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
}
GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
+#if defined(TARGET_PPC64)
+/* stdbrx */
+static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
+{
+ if (likely(!ctx->le_mode)) {
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_bswap64_tl(t0, arg1);
+ tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
+ tcg_temp_free(t0);
+ } else {
+ tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
+ }
+}
+GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
+#endif /* TARGET_PPC64 */
+
/*** Integer load and store multiple ***/
/* lmw */
@@ -8824,7 +8856,7 @@ GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
#undef GEN_LD
#undef GEN_LDU
#undef GEN_LDUX
-#undef GEN_LDX
+#undef GEN_LDX_E
#undef GEN_LDS
#define GEN_LD(name, ldop, opc, type) \
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
@@ -8832,8 +8864,8 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
#define GEN_LDUX(name, ldop, opc2, opc3, type) \
GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
-#define GEN_LDX(name, ldop, opc2, opc3, type) \
-GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
+#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
+GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
#define GEN_LDS(name, ldop, op, type) \
GEN_LD(name, ldop, op | 0x20, type) \
GEN_LDU(name, ldop, op | 0x21, type) \
@@ -8849,6 +8881,7 @@ GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
+GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
#endif
GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
@@ -8856,7 +8889,7 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
#undef GEN_ST
#undef GEN_STU
#undef GEN_STUX
-#undef GEN_STX
+#undef GEN_STX_E
#undef GEN_STS
#define GEN_ST(name, stop, opc, type) \
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
@@ -8864,8 +8897,8 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
#define GEN_STUX(name, stop, opc2, opc3, type) \
GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
-#define GEN_STX(name, stop, opc2, opc3, type) \
-GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
+#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
+GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
#define GEN_STS(name, stop, op, type) \
GEN_ST(name, stop, op | 0x20, type) \
GEN_STU(name, stop, op | 0x21, type) \
@@ -8878,6 +8911,7 @@ GEN_STS(stw, st32, 0x04, PPC_INTEGER)
#if defined(TARGET_PPC64)
GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
+GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
#endif
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6253076..087f2f0 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6571,7 +6571,7 @@ static void init_proc_970MP (CPUPPCState *env)
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI | \
PPC_POPCNTB | PPC_POPCNTWD)
-#define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP)
+#define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP | PPC2_DBRX)
#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
--
1.7.9
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH 3/7] pseries: Add support for level interrupts to XICS
2012-02-28 3:18 [Qemu-devel] [0/7] pseries and Power updates David Gibson
2012-02-28 3:18 ` [Qemu-devel] [PATCH 1/7] pseries: Don't try to munmap() a malloc()ed TCE table David Gibson
2012-02-28 3:18 ` [Qemu-devel] [PATCH 2/7] PPC64: Add support for ldbrx and stdbrx instructions David Gibson
@ 2012-02-28 3:18 ` David Gibson
2012-03-06 23:30 ` Alexander Graf
2012-02-28 3:18 ` [Qemu-devel] [PATCH 4/7] pseries: Update SLOF firmware image David Gibson
` (4 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: David Gibson @ 2012-02-28 3:18 UTC (permalink / raw)
To: agraf; +Cc: qemu-ppc, qemu-devel, anthony, David Gibson
The pseries "xics" interrupt controller, like most interrupt
controllers can support both message (i.e. edge sensitive) interrupts
and level sensitive interrupts, but it needs to know which are which.
When I implemented the xics emulation for qemu, the only devices we
supported were the PAPR virtual IO devices. These devices only use
message interrupts, so they were the only ones I implemented in xics.
Since then, however, we have added support for PCI devices, which use
level sensitive interrupts. It turns out the message interrupt logic
still actually works most of the time for these, but there are
circumstances where we can lost interrupts due to the incorrect
interrupt logic.
This patch, therefore, implements the correct xics level-sensitive
interrupt logic. The type of the interrupt is set when a device
allocates a new xics interrupt.
Signed-off-by: David Gibson <david@gibson@.dropbear.id.au>
---
hw/spapr.c | 4 +-
hw/spapr.h | 12 +++++-
hw/spapr_pci.c | 2 +-
hw/spapr_vio.c | 2 +-
hw/xics.c | 122 +++++++++++++++++++++++++++++++++++++++++---------------
hw/xics.h | 2 +-
6 files changed, 106 insertions(+), 38 deletions(-)
diff --git a/hw/spapr.c b/hw/spapr.c
index dffb6a2..828bc53 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -83,7 +83,7 @@
sPAPREnvironment *spapr;
-qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num)
+qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num, int lsi)
{
uint32_t irq;
qemu_irq qirq;
@@ -95,7 +95,7 @@ qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num)
irq = spapr->next_irq++;
}
- qirq = xics_find_qirq(spapr->icp, irq);
+ qirq = xics_assign_irq(spapr->icp, irq, lsi);
if (!qirq) {
return NULL;
}
diff --git a/hw/spapr.h b/hw/spapr.h
index e946a34..4aae1a0 100644
--- a/hw/spapr.h
+++ b/hw/spapr.h
@@ -286,7 +286,17 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
target_ulong *args);
-qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num);
+qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num, int lsi);
+
+static inline qemu_irq spapr_allocate_msi(uint32_t hint, uint32_t *irq_num)
+{
+ return spapr_allocate_irq(hint, irq_num, 0);
+}
+
+static inline qemu_irq spapr_allocate_lsi(uint32_t hint, uint32_t *irq_num)
+{
+ return spapr_allocate_irq(hint, irq_num, 1);
+}
static inline uint32_t rtas_ld(target_ulong phys, int n)
{
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
index 1e8d03e..28a46bd 100644
--- a/hw/spapr_pci.c
+++ b/hw/spapr_pci.c
@@ -178,7 +178,7 @@ static int spapr_phb_init(SysBusDevice *s)
qemu_irq qirq;
uint32_t num;
- qirq = spapr_allocate_irq(0, &num);
+ qirq = spapr_allocate_lsi(0, &num);
if (!qirq) {
return -1;
}
diff --git a/hw/spapr_vio.c b/hw/spapr_vio.c
index ea317ef..ca0c8e7 100644
--- a/hw/spapr_vio.c
+++ b/hw/spapr_vio.c
@@ -670,7 +670,7 @@ static int spapr_vio_busdev_init(DeviceState *qdev)
dev->qdev.id = id;
}
- dev->qirq = spapr_allocate_irq(dev->vio_irq_num, &dev->vio_irq_num);
+ dev->qirq = spapr_allocate_msi(dev->vio_irq_num, &dev->vio_irq_num);
if (!dev->qirq) {
return -1;
}
diff --git a/hw/xics.c b/hw/xics.c
index 1c5eaa4..3bdff4e 100644
--- a/hw/xics.c
+++ b/hw/xics.c
@@ -132,9 +132,9 @@ static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
{
struct icp_server_state *ss = icp->ss + server;
- ics_eoi(icp->ics, xirr & XISR_MASK);
/* Send EOI -> ICS */
ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
+ ics_eoi(icp->ics, xirr & XISR_MASK);
if (!XISR(ss)) {
icp_resend(icp, server);
}
@@ -165,8 +165,9 @@ struct ics_irq_state {
int server;
uint8_t priority;
uint8_t saved_priority;
- /* int pending:1; */
- /* int presented:1; */
+ int lsi:1;
+ int asserted:1;
+ int sent:1;
int rejected:1;
int masked_pending:1;
};
@@ -185,9 +186,32 @@ static int ics_valid_irq(struct ics_state *ics, uint32_t nr)
&& (nr < (ics->offset + ics->nr_irqs));
}
-static void ics_set_irq_msi(void *opaque, int srcno, int val)
+static void resend_msi(struct ics_state *ics, int srcno)
+{
+ struct ics_irq_state *irq = ics->irqs + srcno;
+
+ /* FIXME: filter by server#? */
+ if (irq->rejected) {
+ irq->rejected = 0;
+ if (irq->priority != 0xff) {
+ icp_irq(ics->icp, irq->server, srcno + ics->offset,
+ irq->priority);
+ }
+ }
+}
+
+static void resend_lsi(struct ics_state *ics, int srcno)
+{
+ struct ics_irq_state *irq = ics->irqs + srcno;
+
+ if ((irq->priority != 0xff) && irq->asserted && !irq->sent) {
+ irq->sent = 1;
+ icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
+ }
+}
+
+static void set_irq_msi(struct ics_state *ics, int srcno, int val)
{
- struct ics_state *ics = (struct ics_state *)opaque;
struct ics_irq_state *irq = ics->irqs + srcno;
if (val) {
@@ -200,71 +224,105 @@ static void ics_set_irq_msi(void *opaque, int srcno, int val)
}
}
-static void ics_reject_msi(struct ics_state *ics, int nr)
+static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
{
- struct ics_irq_state *irq = ics->irqs + nr - ics->offset;
+ struct ics_irq_state *irq = ics->irqs + srcno;
- irq->rejected = 1;
+ irq->asserted = val;
+ resend_lsi(ics, srcno);
}
-static void ics_resend_msi(struct ics_state *ics)
+static void ics_set_irq(void *opaque, int srcno, int val)
{
- int i;
+ struct ics_state *ics = (struct ics_state *)opaque;
+ struct ics_irq_state *irq = ics->irqs + srcno;
- for (i = 0; i < ics->nr_irqs; i++) {
- struct ics_irq_state *irq = ics->irqs + i;
+ if (irq->lsi) {
+ set_irq_lsi(ics, srcno, val);
+ } else {
+ set_irq_msi(ics, srcno, val);
+ }
+}
- /* FIXME: filter by server#? */
- if (irq->rejected) {
- irq->rejected = 0;
- if (irq->priority != 0xff) {
- icp_irq(ics->icp, irq->server, i + ics->offset, irq->priority);
- }
- }
+static void write_xive_msi(struct ics_state *ics, int srcno)
+{
+ struct ics_irq_state *irq = ics->irqs + srcno;
+
+ if (!irq->masked_pending || (irq->priority == 0xff)) {
+ return;
}
+
+ irq->masked_pending = 0;
+ icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
}
-static void ics_write_xive_msi(struct ics_state *ics, int nr, int server,
- uint8_t priority)
+static void write_xive_lsi(struct ics_state *ics, int srcno)
{
- struct ics_irq_state *irq = ics->irqs + nr - ics->offset;
+ resend_lsi(ics, srcno);
+}
+
+static void ics_write_xive(struct ics_state *ics, int nr, int server,
+ uint8_t priority)
+{
+ int srcno = nr - ics->offset;
+ struct ics_irq_state *irq = ics->irqs + srcno;
irq->server = server;
irq->priority = priority;
- if (!irq->masked_pending || (priority == 0xff)) {
- return;
+ if (irq->lsi) {
+ write_xive_lsi(ics, srcno);
+ } else {
+ write_xive_msi(ics, srcno);
}
-
- irq->masked_pending = 0;
- icp_irq(ics->icp, server, nr, priority);
}
static void ics_reject(struct ics_state *ics, int nr)
{
- ics_reject_msi(ics, nr);
+ struct ics_irq_state *irq = ics->irqs + nr - ics->offset;
+
+ irq->rejected = 1; /* Irrelevant but harmless for LSI */
+ irq->sent = 0; /* Irrelevant but harmless for MSI */
}
static void ics_resend(struct ics_state *ics)
{
- ics_resend_msi(ics);
+ int i;
+
+ for (i = 0; i < ics->nr_irqs; i++) {
+ struct ics_irq_state *irq = ics->irqs + i;
+
+ /* FIXME: filter by server#? */
+ if (irq->lsi) {
+ resend_lsi(ics, i);
+ } else {
+ resend_msi(ics, i);
+ }
+ }
}
static void ics_eoi(struct ics_state *ics, int nr)
{
+ int srcno = nr - ics->offset;
+ struct ics_irq_state *irq = ics->irqs + srcno;
+
+ if (irq->lsi) {
+ irq->sent = 0;
+ }
}
/*
* Exported functions
*/
-qemu_irq xics_find_qirq(struct icp_state *icp, int irq)
+qemu_irq xics_assign_irq(struct icp_state *icp, int irq, int lsi)
{
if ((irq < icp->ics->offset)
|| (irq >= (icp->ics->offset + icp->ics->nr_irqs))) {
return NULL;
}
+ icp->ics->irqs[irq - icp->ics->offset].lsi = !!lsi;
return icp->ics->qirqs[irq - icp->ics->offset];
}
@@ -332,7 +390,7 @@ static void rtas_set_xive(sPAPREnvironment *spapr, uint32_t token,
return;
}
- ics_write_xive_msi(ics, nr, server, priority);
+ ics_write_xive(ics, nr, server, priority);
rtas_st(rets, 0, 0); /* Success */
}
@@ -477,7 +535,7 @@ struct icp_state *xics_system_init(int nr_irqs)
ics->irqs[i].saved_priority = 0xff;
}
- ics->qirqs = qemu_allocate_irqs(ics_set_irq_msi, ics, nr_irqs);
+ ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, nr_irqs);
spapr_register_hypercall(H_CPPR, h_cppr);
spapr_register_hypercall(H_IPI, h_ipi);
diff --git a/hw/xics.h b/hw/xics.h
index 83c1182..7cb2b64 100644
--- a/hw/xics.h
+++ b/hw/xics.h
@@ -31,7 +31,7 @@
struct icp_state;
-qemu_irq xics_find_qirq(struct icp_state *icp, int irq);
+qemu_irq xics_assign_irq(struct icp_state *icp, int irq, int lsi);
struct icp_state *xics_system_init(int nr_irqs);
--
1.7.9
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PATCH 3/7] pseries: Add support for level interrupts to XICS
2012-02-28 3:18 ` [Qemu-devel] [PATCH 3/7] pseries: Add support for level interrupts to XICS David Gibson
@ 2012-03-06 23:30 ` Alexander Graf
2012-03-07 5:43 ` [Qemu-devel] [Qemu-ppc] " David Gibson
0 siblings, 1 reply; 13+ messages in thread
From: Alexander Graf @ 2012-03-06 23:30 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, anthony
On 28.02.2012, at 04:18, David Gibson wrote:
> The pseries "xics" interrupt controller, like most interrupt
> controllers can support both message (i.e. edge sensitive) interrupts
> and level sensitive interrupts, but it needs to know which are which.
>
> When I implemented the xics emulation for qemu, the only devices we
> supported were the PAPR virtual IO devices. These devices only use
> message interrupts, so they were the only ones I implemented in xics.
>
> Since then, however, we have added support for PCI devices, which use
> level sensitive interrupts. It turns out the message interrupt logic
> still actually works most of the time for these, but there are
> circumstances where we can lost interrupts due to the incorrect
> interrupt logic.
>
> This patch, therefore, implements the correct xics level-sensitive
> interrupt logic. The type of the interrupt is set when a device
> allocates a new xics interrupt.
>
> Signed-off-by: David Gibson <david@gibson@.dropbear.id.au>
This looks wrong
> ---
> hw/spapr.c | 4 +-
> hw/spapr.h | 12 +++++-
> hw/spapr_pci.c | 2 +-
> hw/spapr_vio.c | 2 +-
> hw/xics.c | 122 +++++++++++++++++++++++++++++++++++++++++---------------
> hw/xics.h | 2 +-
> 6 files changed, 106 insertions(+), 38 deletions(-)
>
> diff --git a/hw/spapr.c b/hw/spapr.c
> index dffb6a2..828bc53 100644
> --- a/hw/spapr.c
> +++ b/hw/spapr.c
> @@ -83,7 +83,7 @@
>
> sPAPREnvironment *spapr;
>
> -qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num)
> +qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num, int lsi)
> {
> uint32_t irq;
> qemu_irq qirq;
> @@ -95,7 +95,7 @@ qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num)
> irq = spapr->next_irq++;
> }
>
> - qirq = xics_find_qirq(spapr->icp, irq);
> + qirq = xics_assign_irq(spapr->icp, irq, lsi);
Find becomes assign? Is this on purpose?
While at it, could you make the "lsi" thing an enum? That'd make things easier to track :).
Alex
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PATCH 3/7] pseries: Add support for level interrupts to XICS
2012-03-06 23:30 ` Alexander Graf
@ 2012-03-07 5:43 ` David Gibson
0 siblings, 0 replies; 13+ messages in thread
From: David Gibson @ 2012-03-07 5:43 UTC (permalink / raw)
To: Alexander Graf; +Cc: qemu-ppc, qemu-devel, anthony
On Wed, Mar 07, 2012 at 12:30:40AM +0100, Alexander Graf wrote:
>
> On 28.02.2012, at 04:18, David Gibson wrote:
>
> > The pseries "xics" interrupt controller, like most interrupt
> > controllers can support both message (i.e. edge sensitive) interrupts
> > and level sensitive interrupts, but it needs to know which are which.
> >
> > When I implemented the xics emulation for qemu, the only devices we
> > supported were the PAPR virtual IO devices. These devices only use
> > message interrupts, so they were the only ones I implemented in xics.
> >
> > Since then, however, we have added support for PCI devices, which use
> > level sensitive interrupts. It turns out the message interrupt logic
> > still actually works most of the time for these, but there are
> > circumstances where we can lost interrupts due to the incorrect
> > interrupt logic.
> >
> > This patch, therefore, implements the correct xics level-sensitive
> > interrupt logic. The type of the interrupt is set when a device
> > allocates a new xics interrupt.
> >
> > Signed-off-by: David Gibson <david@gibson@.dropbear.id.au>
>
> This looks wrong
Oops, I'll fix that up.
>
> > ---
> > hw/spapr.c | 4 +-
> > hw/spapr.h | 12 +++++-
> > hw/spapr_pci.c | 2 +-
> > hw/spapr_vio.c | 2 +-
> > hw/xics.c | 122 +++++++++++++++++++++++++++++++++++++++++---------------
> > hw/xics.h | 2 +-
> > 6 files changed, 106 insertions(+), 38 deletions(-)
> >
> > diff --git a/hw/spapr.c b/hw/spapr.c
> > index dffb6a2..828bc53 100644
> > --- a/hw/spapr.c
> > +++ b/hw/spapr.c
> > @@ -83,7 +83,7 @@
> >
> > sPAPREnvironment *spapr;
> >
> > -qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num)
> > +qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num, int lsi)
> > {
> > uint32_t irq;
> > qemu_irq qirq;
> > @@ -95,7 +95,7 @@ qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num)
> > irq = spapr->next_irq++;
> > }
> >
> > - qirq = xics_find_qirq(spapr->icp, irq);
> > + qirq = xics_assign_irq(spapr->icp, irq, lsi);
>
> Find becomes assign? Is this on purpose?
Yes. Previously xics_find_qirq() just returned the qmeu_irq
associated with a given xics irq number, without changing any state.
Now it also flags whether the irq is an lsi or msi, so the old name
didn't seem right any more.
> While at it, could you make the "lsi" thing an enum? That'd make
> things easier to track :).
Ok, will do.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH 4/7] pseries: Update SLOF firmware image
2012-02-28 3:18 [Qemu-devel] [0/7] pseries and Power updates David Gibson
` (2 preceding siblings ...)
2012-02-28 3:18 ` [Qemu-devel] [PATCH 3/7] pseries: Add support for level interrupts to XICS David Gibson
@ 2012-02-28 3:18 ` David Gibson
2012-02-28 3:18 ` [Qemu-devel] [PATCH 5/7] pseries: Remove unused constant from PCI code David Gibson
` (3 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: David Gibson @ 2012-02-28 3:18 UTC (permalink / raw)
To: agraf; +Cc: qemu-ppc, qemu-devel, anthony, David Gibson
This patch updates the SLOF firmware image used on the pseries
machine. The new version adds support for Cirrus VGA and virtfs, as
well as including a number of bugfixes.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
pc-bios/README | 2 +-
pc-bios/slof.bin | Bin 869584 -> 880496 bytes
roms/SLOF | 2 +-
3 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/pc-bios/README b/pc-bios/README
index 5dce355..71f4871 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -17,7 +17,7 @@
- SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
implementation for certain IBM POWER hardware. The sources are at
https://github.com/dgibson/SLOF, and the image currently in qemu is
- built from git tag qemu-slof-20120111.1.
+ built from git tag qemu-slof-20120217.
- sgabios (the Serial Graphics Adapter option ROM) provides a means for
legacy x86 software to communicate with an attached serial console as
diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin
index 8554f54b5773f0771eec28f6c3bc0dc17e063a47..449a7bb2afaf604f6c089612e99086df0800d7dc 100644
GIT binary patch
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zplZC;eI`C&kL~JS5Sn4T=!6-#NV=<g-$}n4-jLtbo$gbW&$_>G_dXN)9IN%u-`Q&~
zq;(QTTG1)K^88Eptij)rv)(^_&O|p@ea`Q&*ZQxo;HTIm?DDCv;@xAN4)1&wABuVU
zrLW{G9^d#XzQ^`>>+`ShZ#vPP@)KXl=RH0Pe$-!ocbIhbT|@dmea;MOJm4Lm&*{r{
z@|{N5!+ZH?hqrV*S&#X?ahJcynGx55iB3ABLpU>Zp!&)h*9QBVT3#FW<ZX>xTAuCV
zwD*hdCnxn|eYF9-X3(`iVM2FIH8yn55A_d|{DcWJ3jh3_0d-ipd%u2$`s*EPLKT0w
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zxY?oGK01LswEHJ0yBDrnK3W^^k96p$kFII$ScgtXnn%I@q)Si4n(uers7Zf%%nIRk
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z5u6b&Jz_fjB~^0u%aXSe$WwV0mAH>a5xkUni^`#@ns!K!<m%*)I;bxc4)LJck5ekx
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zfvFc?Y{zVM!IM+=Rl(DyCDkv!F@5HS@18d8(w^=X*_tq6uQjT6?zHcmaPpaFoOSkz
zXPj-Xy7WicLw|DVsw*;~RR`D$Vli7%neSbCN#+XTY&-688_xXeY1d8M@Y#9O{$FUr
wx>eJ@2&i9vV|xEJmtQ??!{t}^oVt3$z`W`Ibj*f#zd!xwlc!imo%h=R2awfv0{{R3
diff --git a/roms/SLOF b/roms/SLOF
index ab062ff..d153364 160000
--- a/roms/SLOF
+++ b/roms/SLOF
@@ -1 +1 @@
-Subproject commit ab062ff3b37c39649f2b0d94ed607adc6f6b3c7d
+Subproject commit d153364253548d6cd91403711f84996e6a7dab31
--
1.7.9
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH 5/7] pseries: Remove unused constant from PCI code
2012-02-28 3:18 [Qemu-devel] [0/7] pseries and Power updates David Gibson
` (3 preceding siblings ...)
2012-02-28 3:18 ` [Qemu-devel] [PATCH 4/7] pseries: Update SLOF firmware image David Gibson
@ 2012-02-28 3:18 ` David Gibson
2012-02-28 3:18 ` [Qemu-devel] [PATCH 6/7] pseries: Remove PCI device from PCI host bridge code David Gibson
` (2 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: David Gibson @ 2012-02-28 3:18 UTC (permalink / raw)
To: agraf; +Cc: Alexey Kardashevskiy, qemu-ppc, qemu-devel, anthony, David Gibson
The 'bars' constant array was used in experimental device allocation code
which is no longer necessary now that we always run the SLOF firmware.
This patch removes the now redundant variable.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/spapr_pci.c | 7 -------
1 files changed, 0 insertions(+), 7 deletions(-)
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
index 28a46bd..dafcd0e 100644
--- a/hw/spapr_pci.c
+++ b/hw/spapr_pci.c
@@ -32,13 +32,6 @@
#include "hw/pci_internals.h"
-static const uint32_t bars[] = {
- PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1,
- PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3,
- PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5
- /*, PCI_ROM_ADDRESS*/
-};
-
static PCIDevice *find_dev(sPAPREnvironment *spapr,
uint64_t buid, uint32_t config_addr)
{
--
1.7.9
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH 6/7] pseries: Remove PCI device from PCI host bridge code
2012-02-28 3:18 [Qemu-devel] [0/7] pseries and Power updates David Gibson
` (4 preceding siblings ...)
2012-02-28 3:18 ` [Qemu-devel] [PATCH 5/7] pseries: Remove unused constant from PCI code David Gibson
@ 2012-02-28 3:18 ` David Gibson
2012-02-28 3:18 ` [Qemu-devel] [PATCH 7/7] pseries: Configure PCI bridge using properties David Gibson
2012-03-06 23:35 ` [Qemu-devel] [0/7] pseries and Power updates Alexander Graf
7 siblings, 0 replies; 13+ messages in thread
From: David Gibson @ 2012-02-28 3:18 UTC (permalink / raw)
To: agraf; +Cc: Alexey Kardashevskiy, qemu-ppc, qemu-devel, anthony, David Gibson
From: Alexey Kardashevskiy <aik@ozlabs.ru>
The sPAPR PCI code defines a PCI device "spapr-pci-host-bridge-pci" which
is never used. This came over from the earlier bridge driver we used as
a template. Some other bridges appear on their own PCI bus as a device,
but that is not true of pSeries bridges, which are pure host to PCI with
no visible presence on the PCI side.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/spapr_pci.c | 20 --------------------
1 files changed, 0 insertions(+), 20 deletions(-)
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
index dafcd0e..b0254ee 100644
--- a/hw/spapr_pci.c
+++ b/hw/spapr_pci.c
@@ -183,25 +183,6 @@ static int spapr_phb_init(SysBusDevice *s)
return 0;
}
-static int spapr_main_pci_host_init(PCIDevice *d)
-{
- return 0;
-}
-
-static void spapr_main_pci_host_class_init(ObjectClass *klass, void *data)
-{
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- k->init = spapr_main_pci_host_init;
-}
-
-static TypeInfo spapr_main_pci_host_info = {
- .name = "spapr-pci-host-bridge-pci",
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PCIDevice),
- .class_init = spapr_main_pci_host_class_init,
-};
-
static void spapr_phb_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
@@ -219,7 +200,6 @@ static TypeInfo spapr_phb_info = {
static void spapr_register_types(void)
{
type_register_static(&spapr_phb_info);
- type_register_static(&spapr_main_pci_host_info);
}
type_init(spapr_register_types)
--
1.7.9
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH 7/7] pseries: Configure PCI bridge using properties
2012-02-28 3:18 [Qemu-devel] [0/7] pseries and Power updates David Gibson
` (5 preceding siblings ...)
2012-02-28 3:18 ` [Qemu-devel] [PATCH 6/7] pseries: Remove PCI device from PCI host bridge code David Gibson
@ 2012-02-28 3:18 ` David Gibson
2012-03-03 18:42 ` Andreas Färber
2012-03-06 23:35 ` [Qemu-devel] [0/7] pseries and Power updates Alexander Graf
7 siblings, 1 reply; 13+ messages in thread
From: David Gibson @ 2012-02-28 3:18 UTC (permalink / raw)
To: agraf; +Cc: Alexey Kardashevskiy, qemu-ppc, qemu-devel, anthony, David Gibson
From: Alexey Kardashevskiy <aik@ozlabs.ru>
Currently, the function spapr_create_phb() uses its parameters to
initialize the correct memory windows for the new PCI Host Bridge
(PHB). This is not the way things are supposed to be done with qdevs,
and means you can't create extra PHBs easily using -device.
Since pSeries machines can and do have many PHBs with various
configurations, this is a real limitation, not just a theoretical.
This patch, therefore, alters the PHB initialization code to use qdev
properties to set these parameters of the new bridge, moving most of
the code from spapr_create_phb() to spapr_phb_init().
While we're at it, we change the naming of each PCI bus and its
associated memory regions to be less arbitrary and make it easier to
relate the guest and qemu views of memory to each other.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/spapr.c | 2 +-
hw/spapr_pci.c | 149 ++++++++++++++++++++++++++++++-------------------------
hw/spapr_pci.h | 5 +-
3 files changed, 84 insertions(+), 72 deletions(-)
diff --git a/hw/spapr.c b/hw/spapr.c
index 828bc53..d1cb6cd 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -629,7 +629,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
}
/* Set up PCI */
- spapr_create_phb(spapr, "pci", SPAPR_PCI_BUID,
+ spapr_create_phb(spapr, SPAPR_PCI_BUID,
SPAPR_PCI_MEM_WIN_ADDR,
SPAPR_PCI_MEM_WIN_SIZE,
SPAPR_PCI_IO_WIN_ADDR);
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
index b0254ee..654cb56 100644
--- a/hw/spapr_pci.c
+++ b/hw/spapr_pci.c
@@ -161,49 +161,6 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
}
-static int spapr_phb_init(SysBusDevice *s)
-{
- sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
- int i;
-
- /* Initialize the LSI table */
- for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
- qemu_irq qirq;
- uint32_t num;
-
- qirq = spapr_allocate_lsi(0, &num);
- if (!qirq) {
- return -1;
- }
-
- phb->lsi_table[i].dt_irq = num;
- phb->lsi_table[i].qirq = qirq;
- }
-
- return 0;
-}
-
-static void spapr_phb_class_init(ObjectClass *klass, void *data)
-{
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
-
- sdc->init = spapr_phb_init;
-}
-
-static TypeInfo spapr_phb_info = {
- .name = "spapr-pci-host-bridge",
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(sPAPRPHBState),
- .class_init = spapr_phb_class_init,
-};
-
-static void spapr_register_types(void)
-{
- type_register_static(&spapr_phb_info);
-}
-
-type_init(spapr_register_types)
-
static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
@@ -241,35 +198,29 @@ static MemoryRegionOps spapr_io_ops = {
.write = spapr_io_write
};
-void spapr_create_phb(sPAPREnvironment *spapr,
- const char *busname, uint64_t buid,
- uint64_t mem_win_addr, uint64_t mem_win_size,
- uint64_t io_win_addr)
+/*
+ * PHB PCI device
+ */
+static int spapr_phb_init(SysBusDevice *s)
{
- DeviceState *dev;
- SysBusDevice *s;
- sPAPRPHBState *phb;
+ sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
+ char busname[32];
+ char namebuf[64];
+ int i;
PCIBus *bus;
- char namebuf[strlen(busname)+11];
- dev = qdev_create(NULL, "spapr-pci-host-bridge");
- qdev_init_nofail(dev);
- s = sysbus_from_qdev(dev);
- phb = FROM_SYSBUS(sPAPRPHBState, s);
+ sprintf(busname, "pci@%" PRIx64, phb->buid);
- phb->mem_win_addr = mem_win_addr;
-
- sprintf(namebuf, "%s-mem", busname);
+ /* Initialize memory regions */
+ sprintf(namebuf, "%s.mmio", busname);
memory_region_init(&phb->memspace, namebuf, INT64_MAX);
- sprintf(namebuf, "%s-memwindow", busname);
+ sprintf(namebuf, "%s.mmio-alias", busname);
memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
- SPAPR_PCI_MEM_WIN_BUS_OFFSET, mem_win_size);
- memory_region_add_subregion(get_system_memory(), mem_win_addr,
+ SPAPR_PCI_MEM_WIN_BUS_OFFSET, phb->mem_win_size);
+ memory_region_add_subregion(get_system_memory(), phb->mem_win_addr,
&phb->memwindow);
- phb->io_win_addr = io_win_addr;
-
/* On ppc, we only have MMIO no specific IO space from the CPU
* perspective. In theory we ought to be able to embed the PCI IO
* memory region direction in the system memory space. However,
@@ -278,15 +229,15 @@ void spapr_create_phb(sPAPREnvironment *spapr,
* system io address space. This hack to bounce things via
* system_io works around the problem until all the users of
* old_portion are updated */
- sprintf(namebuf, "%s-io", busname);
+ sprintf(namebuf, "%s.io", busname);
memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
/* FIXME: fix to support multiple PHBs */
memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
- sprintf(namebuf, "%s-iowindow", busname);
+ sprintf(namebuf, "%s.io-alias", busname);
memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
namebuf, SPAPR_PCI_IO_WIN_SIZE);
- memory_region_add_subregion(get_system_memory(), io_win_addr,
+ memory_region_add_subregion(get_system_memory(), phb->io_win_addr,
&phb->iowindow);
phb->host_state.bus = bus = pci_register_bus(&phb->busdev.qdev, busname,
@@ -297,14 +248,76 @@ void spapr_create_phb(sPAPREnvironment *spapr,
PCI_DEVFN(0, 0),
SPAPR_PCI_NUM_LSI);
+ QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
+
+ /* Initialize the LSI table */
+ for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
+ qemu_irq qirq;
+ uint32_t num;
+
+ qirq = spapr_allocate_lsi(0, &num);
+ if (!qirq) {
+ return -1;
+ }
+
+ phb->lsi_table[i].dt_irq = num;
+ phb->lsi_table[i].qirq = qirq;
+ }
+
+ return 0;
+}
+
+static Property spapr_phb_properties[] = {
+ DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, 0),
+ DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, 0),
+ DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 0x20000000),
+ DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, 0),
+ DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 0x10000),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void spapr_phb_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ sdc->init = spapr_phb_init;
+ dc->props = spapr_phb_properties;
+}
+
+static TypeInfo spapr_phb_info = {
+ .name = "spapr-pci-host-bridge",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(sPAPRPHBState),
+ .class_init = spapr_phb_class_init,
+};
+
+static void spapr_register_pci_type(void)
+{
+ type_register_static(&spapr_phb_info);
+
spapr_rtas_register("read-pci-config", rtas_read_pci_config);
spapr_rtas_register("write-pci-config", rtas_write_pci_config);
spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
+}
- QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
+type_init(spapr_register_pci_type)
+
+void spapr_create_phb(sPAPREnvironment *spapr, uint64_t buid,
+ uint64_t mem_win_addr, uint64_t mem_win_size,
+ uint64_t io_win_addr)
+{
+ DeviceState *dev;
- /* pci_bus_set_mem_base(bus, mem_va_start - SPAPR_PCI_MEM_BAR_START); */
+ dev = qdev_create(NULL, spapr_phb_info.name);
+
+ qdev_prop_set_uint64(dev, "buid", buid);
+ qdev_prop_set_uint64(dev, "mem_win_addr", mem_win_addr);
+ qdev_prop_set_uint64(dev, "mem_win_size", mem_win_size);
+ qdev_prop_set_uint64(dev, "io_win_addr", io_win_addr);
+
+ qdev_init_nofail(dev);
}
/* Macros to operate with address in OF binding to PCI */
diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h
index 213340c..b4b8a73 100644
--- a/hw/spapr_pci.h
+++ b/hw/spapr_pci.h
@@ -35,7 +35,7 @@ typedef struct sPAPRPHBState {
uint64_t buid;
MemoryRegion memspace, iospace;
- target_phys_addr_t mem_win_addr, io_win_addr;
+ target_phys_addr_t mem_win_addr, mem_win_size, io_win_addr, io_win_size;
MemoryRegion memwindow, iowindow;
struct {
@@ -49,8 +49,7 @@ typedef struct sPAPRPHBState {
#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
#define SPAPR_PCI_IO_WIN_SIZE 0x10000
-void spapr_create_phb(sPAPREnvironment *spapr,
- const char *busname, uint64_t buid,
+void spapr_create_phb(sPAPREnvironment *spapr, uint64_t buid,
uint64_t mem_win_addr, uint64_t mem_win_size,
uint64_t io_win_addr);
--
1.7.9
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PATCH 7/7] pseries: Configure PCI bridge using properties
2012-02-28 3:18 ` [Qemu-devel] [PATCH 7/7] pseries: Configure PCI bridge using properties David Gibson
@ 2012-03-03 18:42 ` Andreas Färber
2012-03-06 5:22 ` [Qemu-devel] [Qemu-ppc] " David Gibson
0 siblings, 1 reply; 13+ messages in thread
From: Andreas Färber @ 2012-03-03 18:42 UTC (permalink / raw)
To: David Gibson; +Cc: Alexey Kardashevskiy, qemu-ppc, agraf, anthony, qemu-devel
Am 28.02.2012 04:18, schrieb David Gibson:
> From: Alexey Kardashevskiy <aik@ozlabs.ru>
>
> Currently, the function spapr_create_phb() uses its parameters to
> initialize the correct memory windows for the new PCI Host Bridge
> (PHB). This is not the way things are supposed to be done with qdevs,
> and means you can't create extra PHBs easily using -device.
>
> Since pSeries machines can and do have many PHBs with various
> configurations, this is a real limitation, not just a theoretical.
> This patch, therefore, alters the PHB initialization code to use qdev
> properties to set these parameters of the new bridge, moving most of
> the code from spapr_create_phb() to spapr_phb_init().
>
> While we're at it, we change the naming of each PCI bus and its
> associated memory regions to be less arbitrary and make it easier to
> relate the guest and qemu views of memory to each other.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/spapr.c | 2 +-
> hw/spapr_pci.c | 149 ++++++++++++++++++++++++++++++-------------------------
> hw/spapr_pci.h | 5 +-
> 3 files changed, 84 insertions(+), 72 deletions(-)
> diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
> index b0254ee..654cb56 100644
> --- a/hw/spapr_pci.c
> +++ b/hw/spapr_pci.c
> @@ -161,49 +161,6 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
> qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
> }
>
> -static int spapr_phb_init(SysBusDevice *s)
> -{
> - sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
> - int i;
> -
> - /* Initialize the LSI table */
> - for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
> - qemu_irq qirq;
> - uint32_t num;
> -
> - qirq = spapr_allocate_lsi(0, &num);
> - if (!qirq) {
> - return -1;
> - }
> -
> - phb->lsi_table[i].dt_irq = num;
> - phb->lsi_table[i].qirq = qirq;
> - }
> -
> - return 0;
> -}
> -
> -static void spapr_phb_class_init(ObjectClass *klass, void *data)
> -{
> - SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
> -
> - sdc->init = spapr_phb_init;
> -}
> -
> -static TypeInfo spapr_phb_info = {
> - .name = "spapr-pci-host-bridge",
> - .parent = TYPE_SYS_BUS_DEVICE,
> - .instance_size = sizeof(sPAPRPHBState),
> - .class_init = spapr_phb_class_init,
> -};
> -
> -static void spapr_register_types(void)
> -{
> - type_register_static(&spapr_phb_info);
> -}
> -
> -type_init(spapr_register_types)
> -
> static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
> unsigned size)
> {
> @@ -297,14 +248,76 @@ void spapr_create_phb(sPAPREnvironment *spapr,
> PCI_DEVFN(0, 0),
> SPAPR_PCI_NUM_LSI);
>
> + QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
> +
> + /* Initialize the LSI table */
> + for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
> + qemu_irq qirq;
> + uint32_t num;
> +
> + qirq = spapr_allocate_lsi(0, &num);
> + if (!qirq) {
> + return -1;
> + }
> +
> + phb->lsi_table[i].dt_irq = num;
> + phb->lsi_table[i].qirq = qirq;
> + }
> +
> + return 0;
> +}
> +
> +static Property spapr_phb_properties[] = {
> + DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, 0),
> + DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, 0),
> + DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 0x20000000),
> + DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, 0),
> + DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 0x10000),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void spapr_phb_class_init(ObjectClass *klass, void *data)
> +{
> + SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + sdc->init = spapr_phb_init;
> + dc->props = spapr_phb_properties;
> +}
> +
> +static TypeInfo spapr_phb_info = {
> + .name = "spapr-pci-host-bridge",
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(sPAPRPHBState),
> + .class_init = spapr_phb_class_init,
> +};
> +
> +static void spapr_register_pci_type(void)
> +{
> + type_register_static(&spapr_phb_info);
> +
> spapr_rtas_register("read-pci-config", rtas_read_pci_config);
> spapr_rtas_register("write-pci-config", rtas_write_pci_config);
> spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
> spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
> +}
>
> - QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
> +type_init(spapr_register_pci_type)
Please respect the recently enforced convention of naming the function
..._register_types as before and best putting it and type_init() in the
bottom so that we don't end up with multiple ones per file.
And registering types is all such a function can safely do since the
call of these constructors is about to be moved (spapr_rtas_register
looks fishy in that aspect).
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PATCH 7/7] pseries: Configure PCI bridge using properties
2012-03-03 18:42 ` Andreas Färber
@ 2012-03-06 5:22 ` David Gibson
0 siblings, 0 replies; 13+ messages in thread
From: David Gibson @ 2012-03-06 5:22 UTC (permalink / raw)
To: Andreas Färber; +Cc: Alexey Kardashevskiy, qemu-ppc, qemu-devel, anthony
On Sat, Mar 03, 2012 at 07:42:09PM +0100, Andreas Färber wrote:
> Am 28.02.2012 04:18, schrieb David Gibson:
> > From: Alexey Kardashevskiy <aik@ozlabs.ru>
[snip]
> > - QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
> > +type_init(spapr_register_pci_type)
>
> Please respect the recently enforced convention of naming the function
> ..._register_types as before and best putting it and type_init() in the
> bottom so that we don't end up with multiple ones per file.
Now that I'm aware of the convention, sure.
> And registering types is all such a function can safely do since the
> call of these constructors is about to be moved (spapr_rtas_register
> looks fishy in that aspect).
Ok, I'll do the rename and move the rtas register calls into the
class_init function and respin.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [0/7] pseries and Power updates
2012-02-28 3:18 [Qemu-devel] [0/7] pseries and Power updates David Gibson
` (6 preceding siblings ...)
2012-02-28 3:18 ` [Qemu-devel] [PATCH 7/7] pseries: Configure PCI bridge using properties David Gibson
@ 2012-03-06 23:35 ` Alexander Graf
7 siblings, 0 replies; 13+ messages in thread
From: Alexander Graf @ 2012-03-06 23:35 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, anthony
On 28.02.2012, at 04:18, David Gibson wrote:
> This series contains a number of bugfixes and enhancements for the
> pseries machine, including a significant cleanup of the pseries PCI
> code.
>
Thanks, applied 1-2, 4-6 to ppc-next.
Alex
^ permalink raw reply [flat|nested] 13+ messages in thread