[Qemu-devel] [PATCH 0/3] Add new CPU models (v2)

[Qemu-devel] [PATCH 0/3] Add new CPU models (v2)

[Eduardo Habkost]

This series add two new CPU models to Qemu: Intel SandyBridge and AMD
Opteron_G4 (Bulldozer).

Changes v1 -> v2:
  Fixed the Opteron_G4 model to actually have the ffxsr bit disabled, as
  documented in the patch description.

Eduardo Habkost (3):
  add "tsc-deadline" flag name to feature_ecx table
  add SandyBridge CPU model
  add Opteron_G4 CPU model (v2)

 sysconfigs/target/target-x86_64.conf |   28 ++++++++++++++++++++++++++++
 target-i386/cpuid.c                  |    2 +-
 2 files changed, 29 insertions(+), 1 deletions(-)

-- 
1.7.3.2

[Qemu-devel] [PATCH 1/3] add "tsc-deadline" flag name to feature_ecx table

[Eduardo Habkost]

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 target-i386/cpuid.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c
index c2edb64..465ea15 100644
--- a/target-i386/cpuid.c
+++ b/target-i386/cpuid.c
@@ -50,7 +50,7 @@ static const char *ext_feature_name[] = {
     "fma", "cx16", "xtpr", "pdcm",
     NULL, NULL, "dca", "sse4.1|sse4_1",
     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
-    NULL, "aes", "xsave", "osxsave",
+    "tsc-deadline", "aes", "xsave", "osxsave",
     "avx", NULL, NULL, "hypervisor",
 };
 static const char *ext2_feature_name[] = {
-- 
1.7.3.2

[Qemu-devel] [PATCH 2/3] add SandyBridge CPU model

[Eduardo Habkost]

This patches add the definition of a SandyBridge CPU model.

Summary of differences:

Flags present on actual hardware, but not on the added model definition:

- pbe, tm, ht, ss, acpi, vme, xTPR, tm2, eist, smx: host-specific
  features, not exposed to guest.
- ds, ds-cpl, dtes64, pdcm: emulation not supported by KVM (although it
  may be added in the future if implementing PMU virtualization)
- pcid, vmx, monitor: not emulated by Qemu/KVM right now.
- osxsave: set by the guest OS, not by Qemu.

Flags added, that were not present on Westmere model:

- xsave: already supported by Qemu
- avx, pclmulqdq: all new state the new instructions could use is
  handled by xsave state loading/saving code.
- tsc-deadline, x2apic, rdtscp: already supported by Qemu/KVM.

Below there's a comparison of the features on the current Westmere CPU
model, and the SandyBridge CPU model.

- The "full" line contains the flags found on actual hardware.
- The "missing" line shows the flags that are present on actual
  hardware, but not on the added SandyBridge model.
- The "new" line shows the flags that were not on the Westmere model,
  but are on SandyBridge.

feature_edx:
  Westmere:                 sse2 sse fxsr mmx         clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de     fpu
  full:        pbe tm ht ss sse2 sse fxsr mmx ds acpi clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pge msr tsc pse de vme fpu
  SandyBridge:              sse2 sse fxsr mmx         clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de     fpu
  missing:     pbe tm ht ss                   ds acpi                                                                         vme

feature_ecx:
  Westmere:                      aes              popcnt        sse4.2 sse4.1                cx16 ssse3                                                  sse3
  full:        avx osxsave xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 pcid pdcm xTPR cx16 ssse3 tm2 eist smx vmx ds-cpl monitor dtes64 pclmulqdq sse3
  SandyBridge: avx         xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1                cx16 ssse3                                        pclmulqdq sse3
  missing:         osxsave                                                    pcid pdcm xTPR            tm2 eist smx vmx ds-cpl monitor dtes64
  new:         avx         xsave     tsc-deadline        x2apic                                                                                pclmulqdq

extfeature_edx:
  Westmere:    i64        nx syscall
  full:        i64 rdtscp nx syscall
  SandyBridge: i64 rdtscp nx syscall
  new:             rdtscp

extfeature_ecx:
  Westmere:    lahf_lm
  full:        lahf_lm
  SandyBridge: lahf_lm

Cc: "Dugger, Donald D" <donald.d.dugger@intel.com>
Cc: "Zhang, Xiantao" <xiantao.zhang@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 sysconfigs/target/target-x86_64.conf |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index d050380..9fecb94 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -57,6 +57,20 @@
    model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)"
 
 [cpudef]
+   name = "SandyBridge"
+   level = "0xd"
+   vendor = "GenuineIntel"
+   family = "6"
+   model = "42"
+   stepping = "1"
+   feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3"
+   extfeature_edx = "i64 rdtscp nx syscall "
+   extfeature_ecx = "lahf_lm"
+   xlevel = "0x8000000A"
+   model_id = "Intel Xeon E312xx (Sandy Bridge)"
+
+[cpudef]
    name = "Opteron_G1"
    level = "5"
    vendor = "AuthenticAMD"
-- 
1.7.3.2

[Qemu-devel] [PATCH 3/3] add Opteron_G4 CPU model (v2)

[Eduardo Habkost]

This patch addes a Bulldozer-based Opteron_G4 CPU model.

This version has the ffxsr bit actually disabled, to match what was
documented below. Thanks to Andre Przywara for spotting the bug.

I am trying to be conservative with the new model, so I am enabling only
features known to be useful to guests, and not enabling anything that
was not tested or found to be useful to a guest.

List of missing flags in comparison to real hardware:

- vme: host-specific feature.
- osxsave: it is not set here because it is set by the guest OS, not by KVM
- monitor: this is filtered out by the KVM module, so no point in
  enabling it.
- mmxext: untested, so not enabled.
- Perf*, Topology*, lwp, ibs: not emulated by KVM.
- wdt, skinit, osvw, altmovcr8, extapicspace, cmplegacy: untested,
  so not enabled.

List of new flags, in comparison to the Opteron_G3 model:

- xsave: xsave feature, already implemented by Qemu
- avx, aes, sse4.x, ssse3, pclmulqdq: all new state the new instructions
  could use is handled by the xsave state loading/saving code on Qemu.
- pdpe1gb: 1GB pages, supported by the KVM kernel module.
- ffxsr: untested, so not enabled
- fma4, xop: all new state the new instructions could use is handled by
  the xsave loading/saving code on Qemu.
- 3dnowprefetch: safe to pass through, though the flag is not used by
  Linux guests, at least.

Below is the comparison between the current Opteron_G3 model
and the new model being added.

- The "full" line contains the flags found on actual hardware.
- The "missing" line shows the flags that are present on actual
  hardware, but not on the added Opteron_G4 model.
- The "new" line shows the flags that were not on the Opteron_G3 model
  but are on Opteron_G4.

feature_edx:
  Opteron_G3: sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de     fpu
  full:       sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de vme fpu
  Opteron_G4: sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de     fpu
  missing:                                                                                              vme

feature_ecx:
  Opteron_G3:                       popcnt               cx16       monitor           sse3
  full:       avx osxsave xsave aes popcnt sse4.2 sse4.1 cx16 ssse3 monitor pclmulqdq sse3
  Opteron_G4: avx         xsave aes popcnt sse4.2 sse4.1 cx16 ssse3         pclmulqdq sse3
  missing:        osxsave                                           monitor
  new:        avx         xsave aes        sse4.2 sse4.1      ssse3         pclmulqdq

extfeature_edx:
  Opteron_G3: lm rdtscp               fxsr mmx        nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de     fpu
  full:       lm rdtscp pdpe1gb ffxsr fxsr mmx mmxext nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de vme fpu
  Opteron_G4: lm rdtscp pdpe1gb       fxsr mmx        nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de     fpu
  missing:                                     mmxext                                                                        vme
  new:                  pdpe1gb

extfeature_ecx:
  Opteron_G3:                                                                misalignsse sse4a abm                        svm           lahf_lm
  full:       Perf* Topology* fma4 lwp wdt skinit xop ibs osvw 3dnowprefetch misalignsse sse4a abm altmovcr8 extapicspace svm cmplegacy lahf_lm
  Opteron_G4:                 fma4                xop          3dnowprefetch misalignsse sse4a abm                        svm           lahf_lm
  new:                        fma4                xop          3dnowprefetch
  missing:    Perf* Topology*      lwp wdt skinit     ibs osvw                                     altmovcr8 extapicspace     cmplegacy

Changes v1 -> v2:
 - Actually disable ffxsr bit

Cc: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 sysconfigs/target/target-x86_64.conf |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index 9fecb94..cee0ea9 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -112,3 +112,17 @@
    xlevel = "0x80000008"
    model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)"
 
+[cpudef]
+   name = "Opteron_G4"
+   level = "0xd"
+   vendor = "AuthenticAMD"
+   family = "21"
+   model = "1"
+   stepping = "2"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "avx xsave aes popcnt sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3"
+   extfeature_edx = "lm rdtscp pdpe1gb fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_ecx = " fma4 xop 3dnowprefetch misalignsse sse4a abm svm lahf_lm"
+   xlevel = "0x8000001A"
+   model_id = "AMD Opteron 62xx class CPU"
+
-- 
1.7.3.2

Re: [Qemu-devel] [PATCH 2/3] add SandyBridge CPU model

[Zhang, Xiantao]

Seems fine! 
Acked-by: Xiantao Zhang <xiantao.zhang@intel.com>
Xiantao

> -----Original Message-----
> From: Eduardo Habkost [mailto:ehabkost@redhat.com]
> Sent: Wednesday, March 07, 2012 2:12 AM
> To: qemu-devel@nongnu.org
> Cc: Dugger, Donald D; Zhang, Xiantao
> Subject: [PATCH 2/3] add SandyBridge CPU model
> 
> This patches add the definition of a SandyBridge CPU model.
> 
> Summary of differences:
> 
> Flags present on actual hardware, but not on the added model definition:
> 
> - pbe, tm, ht, ss, acpi, vme, xTPR, tm2, eist, smx: host-specific
>   features, not exposed to guest.
> - ds, ds-cpl, dtes64, pdcm: emulation not supported by KVM (although it
>   may be added in the future if implementing PMU virtualization)
> - pcid, vmx, monitor: not emulated by Qemu/KVM right now.
> - osxsave: set by the guest OS, not by Qemu.
> 
> Flags added, that were not present on Westmere model:
> 
> - xsave: already supported by Qemu
> - avx, pclmulqdq: all new state the new instructions could use is
>   handled by xsave state loading/saving code.
> - tsc-deadline, x2apic, rdtscp: already supported by Qemu/KVM.
> 
> Below there's a comparison of the features on the current Westmere CPU
> model, and the SandyBridge CPU model.
> 
> - The "full" line contains the flags found on actual hardware.
> - The "missing" line shows the flags that are present on actual
>   hardware, but not on the added SandyBridge model.
> - The "new" line shows the flags that were not on the Westmere model,
>   but are on SandyBridge.
> 
> feature_edx:
>   Westmere:                 sse2 sse fxsr mmx         clflush pse36 pat cmov mca pge
> mtrr sep apic cx8 mce pae msr tsc pse de     fpu
>   full:        pbe tm ht ss sse2 sse fxsr mmx ds acpi clflush pse36 pat cmov mca
> pge mtrr sep apic cx8 mce pge msr tsc pse de vme fpu
>   SandyBridge:              sse2 sse fxsr mmx         clflush pse36 pat cmov mca pge
> mtrr sep apic cx8 mce pae msr tsc pse de     fpu
>   missing:     pbe tm ht ss                   ds acpi
> vme
> 
> feature_ecx:
>   Westmere:                      aes              popcnt        sse4.2 sse4.1                cx16 ssse3
> sse3
>   full:        avx osxsave xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 pcid
> pdcm xTPR cx16 ssse3 tm2 eist smx vmx ds-cpl monitor dtes64 pclmulqdq
> sse3
>   SandyBridge: avx         xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1
> cx16 ssse3                                        pclmulqdq sse3
>   missing:         osxsave                                                    pcid pdcm xTPR            tm2 eist
> smx vmx ds-cpl monitor dtes64
>   new:         avx         xsave     tsc-deadline        x2apic
> pclmulqdq
> 
> extfeature_edx:
>   Westmere:    i64        nx syscall
>   full:        i64 rdtscp nx syscall
>   SandyBridge: i64 rdtscp nx syscall
>   new:             rdtscp
> 
> extfeature_ecx:
>   Westmere:    lahf_lm
>   full:        lahf_lm
>   SandyBridge: lahf_lm
> 
> Cc: "Dugger, Donald D" <donald.d.dugger@intel.com>
> Cc: "Zhang, Xiantao" <xiantao.zhang@intel.com>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
>  sysconfigs/target/target-x86_64.conf |   14 ++++++++++++++
>  1 files changed, 14 insertions(+), 0 deletions(-)
> 
> diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-
> x86_64.conf
> index d050380..9fecb94 100644
> --- a/sysconfigs/target/target-x86_64.conf
> +++ b/sysconfigs/target/target-x86_64.conf
> @@ -57,6 +57,20 @@
>     model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)"
> 
>  [cpudef]
> +   name = "SandyBridge"
> +   level = "0xd"
> +   vendor = "GenuineIntel"
> +   family = "6"
> +   model = "42"
> +   stepping = "1"
> +   feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> sep apic cx8 mce pae msr tsc pse de fpu"
> +   feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1
> cx16 ssse3 pclmulqdq sse3"
> +   extfeature_edx = "i64 rdtscp nx syscall "
> +   extfeature_ecx = "lahf_lm"
> +   xlevel = "0x8000000A"
> +   model_id = "Intel Xeon E312xx (Sandy Bridge)"
> +
> +[cpudef]
>     name = "Opteron_G1"
>     level = "5"
>     vendor = "AuthenticAMD"
> --
> 1.7.3.2

Re: [Qemu-devel] [PATCH 0/3] Add new CPU models (v2)

[Anthony Liguori]

On 03/06/2012 12:11 PM, Eduardo Habkost wrote:
> This series add two new CPU models to Qemu: Intel SandyBridge and AMD
> Opteron_G4 (Bulldozer).

Applied.  Thanks.

Regards,

Anthony Liguori

>
> Changes v1 ->  v2:
>    Fixed the Opteron_G4 model to actually have the ffxsr bit disabled, as
>    documented in the patch description.
>
> Eduardo Habkost (3):
>    add "tsc-deadline" flag name to feature_ecx table
>    add SandyBridge CPU model
>    add Opteron_G4 CPU model (v2)
>
>   sysconfigs/target/target-x86_64.conf |   28 ++++++++++++++++++++++++++++
>   target-i386/cpuid.c                  |    2 +-
>   2 files changed, 29 insertions(+), 1 deletions(-)
>