From: Troy Kisky <troy.kisky@boundarydevices.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/1] MX53: DDR: Fix ZQHWCTRL field TZQ_CS
Date: Thu, 22 Mar 2012 20:25:11 -0700 [thread overview]
Message-ID: <4F6BED17.2060002@boundarydevices.com> (raw)
In-Reply-To: <4F6BD63F.2090300@boundarydevices.com>
On 3/22/2012 6:47 PM, Troy Kisky wrote:
> On 3/22/2012 3:00 PM, Troy Kisky wrote:
>> Currently, board files are setting this field to 0x01
>> which the manual says is a reserved value. Change to
>> use the default of 0x04 - 128 cycles.
> Typo, should say default of 0x02 - 128 cycles
>
Possibly the manual is wrong, and the value of 0x01 corresponds
to 64 cycles? My testing was on a DDR2 device where this field
is not relevant.
>>
>> Signed-off-by: Troy Kisky<troy.kisky@boundarydevices.com>
>> ---
>> board/freescale/mx53ard/imximage_dd3.cfg | 2 +-
>> board/freescale/mx53evk/imximage.cfg | 2 +-
>> board/freescale/mx53loco/imximage.cfg | 2 +-
>> board/freescale/mx53smd/imximage.cfg | 2 +-
>> 4 files changed, 4 insertions(+), 4 deletions(-)
>>
>>
>>
>>
>> I've tested on an mx53, but this needs much more
>> testing before being applied.
>>
>>
>
next prev parent reply other threads:[~2012-03-23 3:25 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-22 22:00 [U-Boot] [PATCH 1/1] MX53: DDR: Fix ZQHWCTRL field TZQ_CS Troy Kisky
2012-03-23 1:47 ` Troy Kisky
2012-03-23 3:25 ` Troy Kisky [this message]
2012-03-23 9:34 ` Stefano Babic
2012-03-23 16:50 ` Fabio Estevam
2012-03-28 13:10 ` Fabio Estevam
2012-03-28 13:26 ` Stefano Babic
2012-03-28 13:31 ` Fabio Estevam
2012-03-28 13:43 ` Stefano Babic
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