From: Stefano Babic <sbabic@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/1] MX53: DDR: Fix ZQHWCTRL field TZQ_CS
Date: Fri, 23 Mar 2012 10:34:18 +0100 [thread overview]
Message-ID: <4F6C439A.7080300@denx.de> (raw)
In-Reply-To: <4F6BED17.2060002@boundarydevices.com>
On 23/03/2012 04:25, Troy Kisky wrote:
> On 3/22/2012 6:47 PM, Troy Kisky wrote:
>> On 3/22/2012 3:00 PM, Troy Kisky wrote:
>>> Currently, board files are setting this field to 0x01
>>> which the manual says is a reserved value. Change to
>>> use the default of 0x04 - 128 cycles.
>> Typo, should say default of 0x02 - 128 cycles
>>
> Possibly the manual is wrong, and the value of 0x01 corresponds
> to 64 cycles? My testing was on a DDR2 device where this field
> is not relevant.
Is there someone who can answer to this question ? This patch fixes the
value according to the manual, without doubts. But if the manual is wrong...
Best regards,
Stefano Babic
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next prev parent reply other threads:[~2012-03-23 9:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-22 22:00 [U-Boot] [PATCH 1/1] MX53: DDR: Fix ZQHWCTRL field TZQ_CS Troy Kisky
2012-03-23 1:47 ` Troy Kisky
2012-03-23 3:25 ` Troy Kisky
2012-03-23 9:34 ` Stefano Babic [this message]
2012-03-23 16:50 ` Fabio Estevam
2012-03-28 13:10 ` Fabio Estevam
2012-03-28 13:26 ` Stefano Babic
2012-03-28 13:31 ` Fabio Estevam
2012-03-28 13:43 ` Stefano Babic
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