[U-Boot] [PATCH 1/5] pmic: Add support for the Dialog DA9053 PMIC

[U-Boot] [PATCH 1/5] pmic: Add support for the Dialog DA9053 PMIC

[Fabio Estevam]

Add support for the Dialog DA9053 PMIC.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 drivers/misc/Makefile      |    1 +
 drivers/misc/pmic_dialog.c |   37 +++++++++
 include/dialog_pmic.h      |  187 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 225 insertions(+), 0 deletions(-)
 create mode 100644 drivers/misc/pmic_dialog.c
 create mode 100644 include/dialog_pmic.h

diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index a709707..6511713 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_PMIC_FSL) += pmic_fsl.o
 COBJS-$(CONFIG_PMIC_I2C) += pmic_i2c.o
 COBJS-$(CONFIG_PMIC_SPI) += pmic_spi.o
 COBJS-$(CONFIG_PMIC_MAX8998) += pmic_max8998.o
+COBJS-$(CONFIG_DIALOG_PMIC) += pmic_dialog.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/misc/pmic_dialog.c b/drivers/misc/pmic_dialog.c
new file mode 100644
index 0000000..7242073
--- /dev/null
+++ b/drivers/misc/pmic_dialog.c
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2011 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <pmic.h>
+#include <dialog_pmic.h>
+
+int pmic_init(void)
+{
+	struct pmic *p = get_pmic();
+	static const char name[] = "DIALOG_PMIC";
+
+	p->name = name;
+	p->number_of_regs = PMIC_NUM_OF_REGS;
+
+	p->interface = PMIC_I2C;
+	p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR;
+	p->hw.i2c.tx_num = 1;
+	p->bus = I2C_PMIC;
+
+	return 0;
+}
diff --git a/include/dialog_pmic.h b/include/dialog_pmic.h
new file mode 100644
index 0000000..8ac9551
--- /dev/null
+++ b/include/dialog_pmic.h
@@ -0,0 +1,187 @@
+/*
+ * da9053 register declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __DIALOG_PMIC_H__
+#define __DIALOG_PMIC_H__
+
+enum {
+	DA9053_PAGECON0_REG = 0,
+	DA9053_STATUSA_REG,
+	DA9053_STATUSB_REG,
+	DA9053_STATUSC_REG,
+	DA9053_STATUSD_REG,
+	DA9053_EVENTA_REG,
+	DA9053_EVENTB_REG,
+	DA9053_EVENTC_REG,
+	DA9053_EVENTD_REG,
+	DA9053_FAULTLOG_REG,
+	DA9053_IRQMASKA_REG,
+	DA9053_IRQMASKB_REG,
+	DA9053_IRQMASKC_REG,
+	DA9053_IRQMASKD_REG,
+	DA9053_CONTROLA_REG,
+	DA9053_CONTROLB_REG,
+	DA9053_CONTROLC_REG,
+	DA9053_CONTROLD_REG,
+	DA9053_PDDIS_REG,
+	DA9053_INTERFACE_REG,
+	DA9053_RESET_REG,
+	DA9053_GPIO0001_REG,
+	DA9053_GPIO0203_REG,
+	DA9053_GPIO0405_REG,
+	DA9053_GPIO0607_REG,
+	DA9053_GPIO0809_REG,
+	DA9053_GPIO1011_REG,
+	DA9053_GPIO1213_REG,
+	DA9053_GPIO1415_REG,
+	DA9053_ID01_REG,
+	DA9053_ID23_REG,
+	DA9053_ID45_REG,
+	DA9053_ID67_REG,
+	DA9053_ID89_REG,
+	DA9053_ID1011_REG,
+	DA9053_ID1213_REG,
+	DA9053_ID1415_REG,
+	DA9053_ID1617_REG,
+	DA9053_ID1819_REG,
+	DA9053_ID2021_REG,
+	DA9053_SEQSTATUS_REG,
+	DA9053_SEQA_REG,
+	DA9053_SEQB_REG,
+	DA9053_SEQTIMER_REG,
+	DA9053_BUCKA_REG,
+	DA9053_BUCKB_REG,
+	DA9053_BUCKCORE_REG,
+	DA9053_BUCKPRO_REG,
+	DA9053_BUCKMEM_REG,
+	DA9053_BUCKPERI_REG,
+	DA9053_LDO1_REG,
+	DA9053_LDO2_REG,
+	DA9053_LDO3_REG,
+	DA9053_LDO4_REG,
+	DA9053_LDO5_REG,
+	DA9053_LDO6_REG,
+	DA9053_LDO7_REG,
+	DA9053_LDO8_REG,
+	DA9053_LDO9_REG,
+	DA9053_LDO10_REG,
+	DA9053_SUPPLY_REG,
+	DA9053_PULLDOWN_REG,
+	DA9053_CHGBUCK_REG,
+	DA9053_WAITCONT_REG,
+	DA9053_ISET_REG,
+	DA9053_BATCHG_REG,
+	DA9053_CHGCONT_REG,
+	DA9053_INPUTCONT_REG,
+	DA9053_CHGTIME_REG,
+	DA9053_BBATCONT_REG,
+	DA9053_BOOST_REG,
+	DA9053_LEDCONT_REG,
+	DA9053_LEDMIN123_REG,
+	DA9053_LED1CONF_REG,
+	DA9053_LED2CONF_REG,
+	DA9053_LED3CONF_REG,
+	DA9053_LED1CONT_REG,
+	DA9053_LED2CONT_REG,
+	DA9053_LED3CONT_REG,
+	DA9053_LED4CONT_REG,
+	DA9053_LED5CONT_REG,
+	DA9053_ADCMAN_REG,
+	DA9053_ADCCONT_REG,
+	DA9053_ADCRESL_REG,
+	DA9053_ADCRESH_REG,
+	DA9053_VDDRES_REG,
+	DA9053_VDDMON_REG,
+	DA9053_ICHGAV_REG,
+	DA9053_ICHGTHD_REG,
+	DA9053_ICHGEND_REG,
+	DA9053_TBATRES_REG,
+	DA9053_TBATHIGHP_REG,
+	DA9053_TBATHIGHIN_REG,
+	DA9053_TBATLOW_REG,
+	DA9053_TOFFSET_REG,
+	DA9053_ADCIN4RES_REG,
+	DA9053_AUTO4HIGH_REG,
+	DA9053_AUTO4LOW_REG,
+	DA9053_ADCIN5RES_REG,
+	DA9053_AUTO5HIGH_REG,
+	DA9053_AUTO5LOW_REG,
+	DA9053_ADCIN6RES_REG,
+	DA9053_AUTO6HIGH_REG,
+	DA9053_AUTO6LOW_REG,
+	DA9053_TJUNCRES_REG,
+	DA9053_TSICONTA_REG,
+	DA9053_TSICONTB_REG,
+	DA9053_TSIXMSB_REG,
+	DA9053_TSIYMSB_REG,
+	DA9053_TSILSB_REG,
+	DA9053_TSIZMSB_REG,
+	DA9053_COUNTS_REG,
+	DA9053_COUNTMI_REG,
+	DA9053_COUNTH_REG,
+	DA9053_COUNTD_REG,
+	DA9053_COUNTMO_REG,
+	DA9053_COUNTY_REG,
+	DA9053_ALARMMI_REG,
+	DA9053_ALARMH_REG,
+	DA9053_ALARMD_REG,
+	DA9053_ALARMMO_REG,
+	DA9053_ALARMY_REG,
+	DA9053_SECONDA_REG,
+	DA9053_SECONDB_REG,
+	DA9053_SECONDC_REG,
+	DA9053_SECONDD_REG,
+	DA9053_PAGECON128_REG,
+	DA9053_CHIPID_REG,
+	DA9053_CONFIGID_REG,
+	DA9053_OTPCONT_REG,
+	DA9053_OSCTRIM_REG,
+	DA9053_GPID0_REG,
+	DA9053_GPID1_REG,
+	DA9053_GPID2_REG,
+	DA9053_GPID3_REG,
+	DA9053_GPID4_REG,
+	DA9053_GPID5_REG,
+	DA9053_GPID6_REG,
+	DA9053_GPID7_REG,
+	DA9053_GPID8_REG,
+	DA9053_GPID9_REG,
+	PMIC_NUM_OF_REGS,
+};
+
+#define DA_BUCKCORE_VBCORE_1_250V		0x1E
+
+/* BUCKCORE REGISTER */
+#define DA9052_BUCKCORE_BCORECONF               (1 << 7)
+#define DA9052_BUCKCORE_BCOREEN                 (1 << 6)
+#define DA9052_BUCKCORE_VBCORE                  63
+
+/* SUPPLY REGISTER */
+#define DA9052_SUPPLY_VLOCK                     (1 << 7)
+#define DA9052_SUPPLY_VMEMSWEN                  (1 << 6)
+#define DA9052_SUPPLY_VPERISWEN                 (1 << 5)
+#define DA9052_SUPPLY_VLDO3GO                   (1 << 4)
+#define DA9052_SUPPLY_VLDO2GO                   (1 << 3)
+#define DA9052_SUPPLY_VBMEMGO                   (1 << 2)
+#define DA9052_SUPPLY_VBPROGO                   (1 << 1)
+#define DA9052_SUPPLY_VBCOREGO                  (1 << 0)
+
+#endif /* __DIALOG_PMIC_H__ */
-- 
1.7.1

[U-Boot] [PATCH 2/5] imx-common: Factor out get_ahb_clk()

[Fabio Estevam]

get_ahb_clk() is a common function between mx5 and mx6.

Place it into imx-common directory.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 arch/arm/cpu/armv7/imx-common/cpu.c                |   23 ++++++++++++++++++++
 arch/arm/cpu/armv7/mx5/clock.c                     |   17 +-------------
 arch/arm/cpu/armv7/mx6/clock.c                     |   17 ++------------
 arch/arm/include/asm/arch-mx5/sys_proto.h          |    1 +
 .../asm/arch-mx6/{ccm_regs.h => crm_regs.h}        |    2 +-
 arch/arm/include/asm/arch-mx6/sys_proto.h          |    1 +
 6 files changed, 30 insertions(+), 31 deletions(-)
 rename arch/arm/include/asm/arch-mx6/{ccm_regs.h => crm_regs.h} (99%)

diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c
index 6d7486b..62b01e7 100644
--- a/arch/arm/cpu/armv7/imx-common/cpu.c
+++ b/arch/arm/cpu/armv7/imx-common/cpu.c
@@ -29,6 +29,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
 
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
@@ -107,3 +108,25 @@ void reset_cpu(ulong addr)
 {
 	__raw_writew(4, WDOG1_BASE_ADDR);
 }
+
+static u32 __get_periph_clk(void)
+{
+	return 0;	/* clock.c will override it */
+}
+
+u32 get_periph_clk(void)
+	__attribute__((weak, alias("__get_periph_clk")));
+
+u32 get_ahb_clk(void)
+{
+	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg, ahb_podf;
+
+	reg = __raw_readl(&imx_ccm->cbcdr);
+	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
+	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+
+	return get_periph_clk() / (ahb_podf + 1);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index e92f106..a1c8411 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -30,6 +30,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <div64.h>
+#include <asm/arch/sys_proto.h>
 
 enum pll_clocks {
 	PLL1_CLOCK = 0,
@@ -213,22 +214,6 @@ static u32 get_periph_clk(void)
 }
 
 /*
- * Get the rate of ahb clock.
- */
-static u32 get_ahb_clk(void)
-{
-	uint32_t freq, div, reg;
-
-	freq = get_periph_clk();
-
-	reg = __raw_readl(&mxc_ccm->cbcdr);
-	div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
-			MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
-
-	return freq / div;
-}
-
-/*
  * Get the rate of ipg clock.
  */
 static u32 get_ipg_clk(void)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ef98563..5d42051 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -24,8 +24,9 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/ccm_regs.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
 
 enum pll_clocks {
 	PLL_SYS,	/* System PLL */
@@ -34,7 +35,7 @@ enum pll_clocks {
 	PLL_ENET,	/* ENET PLL */
 };
 
-struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
 void enable_usboh3_clk(unsigned char enable)
 {
@@ -139,18 +140,6 @@ static u32 get_periph_clk(void)
 	return freq;
 }
 
-
-static u32 get_ahb_clk(void)
-{
-	u32 reg, ahb_podf;
-
-	reg = __raw_readl(&imx_ccm->cbcdr);
-	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
-	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-
-	return get_periph_clk() / (ahb_podf + 1);
-}
-
 static u32 get_ipg_clk(void)
 {
 	u32 reg, ipg_podf;
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index 13d12ee..7250059 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -35,5 +35,6 @@ void set_chipselect_size(int const);
  */
 
 int fecmxc_initialize(bd_t *bis);
+u32 get_ahb_clk(void);
 
 #endif
diff --git a/arch/arm/include/asm/arch-mx6/ccm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
similarity index 99%
rename from arch/arm/include/asm/arch-mx6/ccm_regs.h
rename to arch/arm/include/asm/arch-mx6/crm_regs.h
index 4af0b90..0e605c2 100644
--- a/arch/arm/include/asm/arch-mx6/ccm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -20,7 +20,7 @@
 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
 
-struct imx_ccm_reg {
+struct mxc_ccm_reg {
 	u32 ccr;	/* 0x0000 */
 	u32 ccdr;
 	u32 csr;
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 668e77a..3bfc69c 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -34,5 +34,6 @@ u32 get_cpu_rev(void);
  */
 
 int fecmxc_initialize(bd_t *bis);
+u32 get_ahb_clk(void);
 
 #endif
-- 
1.7.1

[U-Boot] [PATCH 2/5] imx-common: Factor out get_ahb_clk()

[Dirk Behme]

Hi Fabio,

On 20.03.2012 22:40, Fabio Estevam wrote:
> get_ahb_clk() is a common function between mx5 and mx6.
> 
> Place it into imx-common directory.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
>  arch/arm/cpu/armv7/imx-common/cpu.c                |   23 ++++++++++++++++++++
>  arch/arm/cpu/armv7/mx5/clock.c                     |   17 +-------------
>  arch/arm/cpu/armv7/mx6/clock.c                     |   17 ++------------
>  arch/arm/include/asm/arch-mx5/sys_proto.h          |    1 +
>  .../asm/arch-mx6/{ccm_regs.h => crm_regs.h}        |    2 +-
>  arch/arm/include/asm/arch-mx6/sys_proto.h          |    1 +
>  6 files changed, 30 insertions(+), 31 deletions(-)
>  rename arch/arm/include/asm/arch-mx6/{ccm_regs.h => crm_regs.h} (99%)

We had this patch on a v2012.04.1 based test branch and it showed some 
strange issues with SD cards on i.MX6.

Depending on the SD card used (different ones) and the board (SabreLite 
and a custom one)

- the SD card just works fine as we are used to
- booting fails with "MMC init failed"
- booting fails with "Card did not respond to voltage select!"

Reverting this patch on the test branch makes all tested boards and 
tested SD cards work fine again.

I haven't looked into the details to debug the root cause, though.

So for the moment: NACK

Best regards

Dirk

> diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c
> index 6d7486b..62b01e7 100644
> --- a/arch/arm/cpu/armv7/imx-common/cpu.c
> +++ b/arch/arm/cpu/armv7/imx-common/cpu.c
> @@ -29,6 +29,7 @@
>  #include <asm/arch/imx-regs.h>
>  #include <asm/arch/clock.h>
>  #include <asm/arch/sys_proto.h>
> +#include <asm/arch/crm_regs.h>
>  
>  #ifdef CONFIG_FSL_ESDHC
>  #include <fsl_esdhc.h>
> @@ -107,3 +108,25 @@ void reset_cpu(ulong addr)
>  {
>  	__raw_writew(4, WDOG1_BASE_ADDR);
>  }
> +
> +static u32 __get_periph_clk(void)
> +{
> +	return 0;	/* clock.c will override it */
> +}
> +
> +u32 get_periph_clk(void)
> +	__attribute__((weak, alias("__get_periph_clk")));
> +
> +u32 get_ahb_clk(void)
> +{
> +	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +	u32 reg, ahb_podf;
> +
> +	reg = __raw_readl(&imx_ccm->cbcdr);
> +	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
> +	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
> +
> +	return get_periph_clk() / (ahb_podf + 1);
> +
> +	return 0;
> +}
> diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
> index e92f106..a1c8411 100644
> --- a/arch/arm/cpu/armv7/mx5/clock.c
> +++ b/arch/arm/cpu/armv7/mx5/clock.c
> @@ -30,6 +30,7 @@
>  #include <asm/arch/crm_regs.h>
>  #include <asm/arch/clock.h>
>  #include <div64.h>
> +#include <asm/arch/sys_proto.h>
>  
>  enum pll_clocks {
>  	PLL1_CLOCK = 0,
> @@ -213,22 +214,6 @@ static u32 get_periph_clk(void)
>  }
>  
>  /*
> - * Get the rate of ahb clock.
> - */
> -static u32 get_ahb_clk(void)
> -{
> -	uint32_t freq, div, reg;
> -
> -	freq = get_periph_clk();
> -
> -	reg = __raw_readl(&mxc_ccm->cbcdr);
> -	div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
> -			MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
> -
> -	return freq / div;
> -}
> -
> -/*
>   * Get the rate of ipg clock.
>   */
>  static u32 get_ipg_clk(void)
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
> index ef98563..5d42051 100644
> --- a/arch/arm/cpu/armv7/mx6/clock.c
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -24,8 +24,9 @@
>  #include <asm/io.h>
>  #include <asm/errno.h>
>  #include <asm/arch/imx-regs.h>
> -#include <asm/arch/ccm_regs.h>
> +#include <asm/arch/crm_regs.h>
>  #include <asm/arch/clock.h>
> +#include <asm/arch/sys_proto.h>
>  
>  enum pll_clocks {
>  	PLL_SYS,	/* System PLL */
> @@ -34,7 +35,7 @@ enum pll_clocks {
>  	PLL_ENET,	/* ENET PLL */
>  };
>  
> -struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
> +struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
>  
>  void enable_usboh3_clk(unsigned char enable)
>  {
> @@ -139,18 +140,6 @@ static u32 get_periph_clk(void)
>  	return freq;
>  }
>  
> -
> -static u32 get_ahb_clk(void)
> -{
> -	u32 reg, ahb_podf;
> -
> -	reg = __raw_readl(&imx_ccm->cbcdr);
> -	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
> -	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
> -
> -	return get_periph_clk() / (ahb_podf + 1);
> -}
> -
>  static u32 get_ipg_clk(void)
>  {
>  	u32 reg, ipg_podf;
> diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
> index 13d12ee..7250059 100644
> --- a/arch/arm/include/asm/arch-mx5/sys_proto.h
> +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
> @@ -35,5 +35,6 @@ void set_chipselect_size(int const);
>   */
>  
>  int fecmxc_initialize(bd_t *bis);
> +u32 get_ahb_clk(void);
>  
>  #endif
> diff --git a/arch/arm/include/asm/arch-mx6/ccm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
> similarity index 99%
> rename from arch/arm/include/asm/arch-mx6/ccm_regs.h
> rename to arch/arm/include/asm/arch-mx6/crm_regs.h
> index 4af0b90..0e605c2 100644
> --- a/arch/arm/include/asm/arch-mx6/ccm_regs.h
> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
> @@ -20,7 +20,7 @@
>  #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
>  #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
>  
> -struct imx_ccm_reg {
> +struct mxc_ccm_reg {
>  	u32 ccr;	/* 0x0000 */
>  	u32 ccdr;
>  	u32 csr;
> diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
> index 668e77a..3bfc69c 100644
> --- a/arch/arm/include/asm/arch-mx6/sys_proto.h
> +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
> @@ -34,5 +34,6 @@ u32 get_cpu_rev(void);
>   */
>  
>  int fecmxc_initialize(bd_t *bis);
> +u32 get_ahb_clk(void);
>  
>  #endif

[U-Boot] [PATCH 2/5] imx-common: Factor out get_ahb_clk()

[Fabio Estevam]

Hi Dirk,

On Thu, Apr 26, 2012 at 3:04 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote:

> We had this patch on a v2012.04.1 based test branch and it showed some
> strange issues with SD cards on i.MX6.
>
> Depending on the SD card used (different ones) and the board (SabreLite and
> a custom one)
>
> - the SD card just works fine as we are used to
> - booting fails with "MMC init failed"
> - booting fails with "Card did not respond to voltage select!"
>
> Reverting this patch on the test branch makes all tested boards and tested
> SD cards work fine again.
>
> I haven't looked into the details to debug the root cause, though.
>
> So for the moment: NACK

Thanks for testing it. I found one mistake and will submit a fix shortly.

Regards,

Fabio Estevam

[U-Boot] [PATCH 2/5] imx-common: Factor out get_ahb_clk()

[Fabio Estevam]

Dirk,

On Sun, Apr 29, 2012 at 11:54 AM, Fabio Estevam <festevam@gmail.com> wrote:

> Thanks for testing it. I found one mistake and will submit a fix shortly.

Here is one issue I found:

--- a/arch/arm/cpu/armv7/imx-common/cpu.c
+++ b/arch/arm/cpu/armv7/imx-common/cpu.c
@@ -147,6 +147,4 @@ u32 get_ahb_clk(void)
        ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;

        return get_periph_clk() / (ahb_podf + 1);
-
-       return 0;
 }

This should be fixed, but it seems it does not explain the problem you
are seeing. We need to check whether get_ahb_clk() is using the weak
definition of get_periph_clk() instead the one from clock.c.

Regards,

Fabio Estevam

[U-Boot] [PATCH 2/5] imx-common: Factor out get_ahb_clk()

[Fabio Estevam]

Dirk,

On Sun, Apr 29, 2012 at 1:26 PM, Fabio Estevam <festevam@gmail.com> wrote:

> This should be fixed, but it seems it does not explain the problem you
> are seeing. We need to check whether get_ahb_clk() is using the weak
> definition of get_periph_clk() instead the one from clock.c.

Yes, I confirmed that that get_ahb_clk was using the weak definition
of  get_periph_clk().

I removed the weak definition of get_periph_clk() and made it
non-static and now it is exported via sys_proto.h.

I sent v2 which should fix the problem you reported in v1.

Thanks,

Fabio Estevam

[U-Boot] [PATCH 2/5] imx-common: Factor out get_ahb_clk()

[Fabio Estevam]

Hi Dirk,

On Sun, Apr 29, 2012 at 3:15 PM, Fabio Estevam <festevam@gmail.com> wrote:

> I sent v2 which should fix the problem you reported in v1.

When you have a chance, could you please try this version and let us
know if it fixes the issues you reported previously?

Thanks,

Fabio Estevam

[U-Boot] [PATCH 2/5] imx-common: Factor out get_ahb_clk()

[Dirk Behme]

Hi Stefano,

On 29.04.2012 16:54, Fabio Estevam wrote:
> Hi Dirk,
>
> On Thu, Apr 26, 2012 at 3:04 AM, Dirk Behme<dirk.behme@de.bosch.com>  wrote:
>
>> We had this patch on a v2012.04.1 based test branch and it showed some
>> strange issues with SD cards on i.MX6.
>>
>> Depending on the SD card used (different ones) and the board (SabreLite and
>> a custom one)
>>
>> - the SD card just works fine as we are used to
>> - booting fails with "MMC init failed"
>> - booting fails with "Card did not respond to voltage select!"
>>
>> Reverting this patch on the test branch makes all tested boards and tested
>> SD cards work fine again.
>>
>> I haven't looked into the details to debug the root cause, though.
>>
>> So for the moment: NACK
>
> Thanks for testing it. I found one mistake and will submit a fix shortly.

I saw you have this patch already in

http://git.denx.de/?p=u-boot/u-boot-imx.git;a=shortlog;h=refs/heads/master

Do you mind to remove this?

Best regards

Dirk

[U-Boot] [PATCH 2/5] imx-common: Factor out get_ahb_clk()

[Stefano Babic]

On 29/04/2012 18:43, Dirk Behme wrote:
> Hi Stefano,
> 
> On 29.04.2012 16:54, Fabio Estevam wrote:
>> Hi Dirk,
>>
>> On Thu, Apr 26, 2012 at 3:04 AM, Dirk Behme<dirk.behme@de.bosch.com> 
>> wrote:
>>
>>> We had this patch on a v2012.04.1 based test branch and it showed some
>>> strange issues with SD cards on i.MX6.
>>>
>>> Depending on the SD card used (different ones) and the board
>>> (SabreLite and
>>> a custom one)
>>>
>>> - the SD card just works fine as we are used to
>>> - booting fails with "MMC init failed"
>>> - booting fails with "Card did not respond to voltage select!"
>>>
>>> Reverting this patch on the test branch makes all tested boards and
>>> tested
>>> SD cards work fine again.
>>>
>>> I haven't looked into the details to debug the root cause, though.
>>>
>>> So for the moment: NACK
>>
>> Thanks for testing it. I found one mistake and will submit a fix shortly.
> 
> I saw you have this patch already in
> 
> http://git.denx.de/?p=u-boot/u-boot-imx.git;a=shortlog;h=refs/heads/maste

Hi Dirk,

thanks for raise my attention on this issue. I drop the patch from
u-boot-imx

Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2] imx-common: Factor out get_ahb_clk()

[Fabio Estevam]

get_ahb_clk() is a common function between mx5 and mx6.

Place it into imx-common directory.

Cc: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1: Do not use weak definition for get_periph_clk()

 arch/arm/cpu/armv7/imx-common/cpu.c                |   13 +++++++++++++
 arch/arm/cpu/armv7/mx5/clock.c                     |   19 ++-----------------
 arch/arm/cpu/armv7/mx6/clock.c                     |   19 ++++---------------
 arch/arm/include/asm/arch-mx5/sys_proto.h          |    2 ++
 .../asm/arch-mx6/{ccm_regs.h => crm_regs.h}        |    2 +-
 arch/arm/include/asm/arch-mx6/sys_proto.h          |    3 ++-
 6 files changed, 24 insertions(+), 34 deletions(-)
 rename arch/arm/include/asm/arch-mx6/{ccm_regs.h => crm_regs.h} (99%)

diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c
index 3d58d8a..b96fa5b 100644
--- a/arch/arm/cpu/armv7/imx-common/cpu.c
+++ b/arch/arm/cpu/armv7/imx-common/cpu.c
@@ -29,6 +29,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
 
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
@@ -127,3 +128,15 @@ void reset_cpu(ulong addr)
 {
 	__raw_writew(4, WDOG1_BASE_ADDR);
 }
+
+u32 get_ahb_clk(void)
+{
+	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg, ahb_podf;
+
+	reg = __raw_readl(&imx_ccm->cbcdr);
+	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
+	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+
+	return get_periph_clk() / (ahb_podf + 1);
+}
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index d769a4d..903e207 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -30,6 +30,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <div64.h>
+#include <asm/arch/sys_proto.h>
 
 enum pll_clocks {
 	PLL1_CLOCK = 0,
@@ -192,7 +193,7 @@ u32 get_mcu_main_clk(void)
 /*
  * Get the rate of peripheral's root clock.
  */
-static u32 get_periph_clk(void)
+u32 get_periph_clk(void)
 {
 	u32 reg;
 
@@ -213,22 +214,6 @@ static u32 get_periph_clk(void)
 }
 
 /*
- * Get the rate of ahb clock.
- */
-static u32 get_ahb_clk(void)
-{
-	uint32_t freq, div, reg;
-
-	freq = get_periph_clk();
-
-	reg = __raw_readl(&mxc_ccm->cbcdr);
-	div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
-			MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
-
-	return freq / div;
-}
-
-/*
  * Get the rate of ipg clock.
  */
 static u32 get_ipg_clk(void)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ef98563..0f05432 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -24,8 +24,9 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/ccm_regs.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
 
 enum pll_clocks {
 	PLL_SYS,	/* System PLL */
@@ -34,7 +35,7 @@ enum pll_clocks {
 	PLL_ENET,	/* ENET PLL */
 };
 
-struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
 void enable_usboh3_clk(unsigned char enable)
 {
@@ -92,7 +93,7 @@ static u32 get_mcu_main_clk(void)
 	return freq / (reg + 1);
 }
 
-static u32 get_periph_clk(void)
+u32 get_periph_clk(void)
 {
 	u32 reg, freq = 0;
 
@@ -139,18 +140,6 @@ static u32 get_periph_clk(void)
 	return freq;
 }
 
-
-static u32 get_ahb_clk(void)
-{
-	u32 reg, ahb_podf;
-
-	reg = __raw_readl(&imx_ccm->cbcdr);
-	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
-	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-
-	return get_periph_clk() / (ahb_podf + 1);
-}
-
 static u32 get_ipg_clk(void)
 {
 	u32 reg, ipg_podf;
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index 13d12ee..3f10d29 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -35,5 +35,7 @@ void set_chipselect_size(int const);
  */
 
 int fecmxc_initialize(bd_t *bis);
+u32 get_ahb_clk(void);
+u32 get_periph_clk(void);
 
 #endif
diff --git a/arch/arm/include/asm/arch-mx6/ccm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
similarity index 99%
rename from arch/arm/include/asm/arch-mx6/ccm_regs.h
rename to arch/arm/include/asm/arch-mx6/crm_regs.h
index 4af0b90..0e605c2 100644
--- a/arch/arm/include/asm/arch-mx6/ccm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -20,7 +20,7 @@
 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
 
-struct imx_ccm_reg {
+struct mxc_ccm_reg {
 	u32 ccr;	/* 0x0000 */
 	u32 ccdr;
 	u32 csr;
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 668e77a..69687a8 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -34,5 +34,6 @@ u32 get_cpu_rev(void);
  */
 
 int fecmxc_initialize(bd_t *bis);
-
+u32 get_ahb_clk(void);
+u32 get_periph_clk(void);
 #endif
-- 
1.7.1

[U-Boot] [PATCH v2] imx-common: Factor out get_ahb_clk()

[Dirk Behme]

On 29.04.2012 20:11, Fabio Estevam wrote:
> get_ahb_clk() is a common function between mx5 and mx6.
> 
> Place it into imx-common directory.
> 
> Cc: Dirk Behme <dirk.behme@googlemail.com>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Booting this on the SabreLite with different SD cards looks fine. So:

Tested-by: Dirk Behme <dirk.behme@de.bosch.com>

> ---
> Changes since v1: Do not use weak definition for get_periph_clk()
> 
>  arch/arm/cpu/armv7/imx-common/cpu.c                |   13 +++++++++++++
>  arch/arm/cpu/armv7/mx5/clock.c                     |   19 ++-----------------
>  arch/arm/cpu/armv7/mx6/clock.c                     |   19 ++++---------------
>  arch/arm/include/asm/arch-mx5/sys_proto.h          |    2 ++
>  .../asm/arch-mx6/{ccm_regs.h => crm_regs.h}        |    2 +-
>  arch/arm/include/asm/arch-mx6/sys_proto.h          |    3 ++-
>  6 files changed, 24 insertions(+), 34 deletions(-)
>  rename arch/arm/include/asm/arch-mx6/{ccm_regs.h => crm_regs.h} (99%)
> 
> diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c
> index 3d58d8a..b96fa5b 100644
> --- a/arch/arm/cpu/armv7/imx-common/cpu.c
> +++ b/arch/arm/cpu/armv7/imx-common/cpu.c
> @@ -29,6 +29,7 @@
>  #include <asm/arch/imx-regs.h>
>  #include <asm/arch/clock.h>
>  #include <asm/arch/sys_proto.h>
> +#include <asm/arch/crm_regs.h>
>  
>  #ifdef CONFIG_FSL_ESDHC
>  #include <fsl_esdhc.h>
> @@ -127,3 +128,15 @@ void reset_cpu(ulong addr)
>  {
>  	__raw_writew(4, WDOG1_BASE_ADDR);
>  }
> +
> +u32 get_ahb_clk(void)
> +{
> +	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +	u32 reg, ahb_podf;
> +
> +	reg = __raw_readl(&imx_ccm->cbcdr);
> +	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
> +	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
> +
> +	return get_periph_clk() / (ahb_podf + 1);
> +}
> diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
> index d769a4d..903e207 100644
> --- a/arch/arm/cpu/armv7/mx5/clock.c
> +++ b/arch/arm/cpu/armv7/mx5/clock.c
> @@ -30,6 +30,7 @@
>  #include <asm/arch/crm_regs.h>
>  #include <asm/arch/clock.h>
>  #include <div64.h>
> +#include <asm/arch/sys_proto.h>
>  
>  enum pll_clocks {
>  	PLL1_CLOCK = 0,
> @@ -192,7 +193,7 @@ u32 get_mcu_main_clk(void)
>  /*
>   * Get the rate of peripheral's root clock.
>   */
> -static u32 get_periph_clk(void)
> +u32 get_periph_clk(void)
>  {
>  	u32 reg;
>  
> @@ -213,22 +214,6 @@ static u32 get_periph_clk(void)
>  }
>  
>  /*
> - * Get the rate of ahb clock.
> - */
> -static u32 get_ahb_clk(void)
> -{
> -	uint32_t freq, div, reg;
> -
> -	freq = get_periph_clk();
> -
> -	reg = __raw_readl(&mxc_ccm->cbcdr);
> -	div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
> -			MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
> -
> -	return freq / div;
> -}
> -
> -/*
>   * Get the rate of ipg clock.
>   */
>  static u32 get_ipg_clk(void)
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
> index ef98563..0f05432 100644
> --- a/arch/arm/cpu/armv7/mx6/clock.c
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -24,8 +24,9 @@
>  #include <asm/io.h>
>  #include <asm/errno.h>
>  #include <asm/arch/imx-regs.h>
> -#include <asm/arch/ccm_regs.h>
> +#include <asm/arch/crm_regs.h>
>  #include <asm/arch/clock.h>
> +#include <asm/arch/sys_proto.h>
>  
>  enum pll_clocks {
>  	PLL_SYS,	/* System PLL */
> @@ -34,7 +35,7 @@ enum pll_clocks {
>  	PLL_ENET,	/* ENET PLL */
>  };
>  
> -struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
> +struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
>  
>  void enable_usboh3_clk(unsigned char enable)
>  {
> @@ -92,7 +93,7 @@ static u32 get_mcu_main_clk(void)
>  	return freq / (reg + 1);
>  }
>  
> -static u32 get_periph_clk(void)
> +u32 get_periph_clk(void)
>  {
>  	u32 reg, freq = 0;
>  
> @@ -139,18 +140,6 @@ static u32 get_periph_clk(void)
>  	return freq;
>  }
>  
> -
> -static u32 get_ahb_clk(void)
> -{
> -	u32 reg, ahb_podf;
> -
> -	reg = __raw_readl(&imx_ccm->cbcdr);
> -	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
> -	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
> -
> -	return get_periph_clk() / (ahb_podf + 1);
> -}
> -
>  static u32 get_ipg_clk(void)
>  {
>  	u32 reg, ipg_podf;
> diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
> index 13d12ee..3f10d29 100644
> --- a/arch/arm/include/asm/arch-mx5/sys_proto.h
> +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
> @@ -35,5 +35,7 @@ void set_chipselect_size(int const);
>   */
>  
>  int fecmxc_initialize(bd_t *bis);
> +u32 get_ahb_clk(void);
> +u32 get_periph_clk(void);
>  
>  #endif
> diff --git a/arch/arm/include/asm/arch-mx6/ccm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
> similarity index 99%
> rename from arch/arm/include/asm/arch-mx6/ccm_regs.h
> rename to arch/arm/include/asm/arch-mx6/crm_regs.h
> index 4af0b90..0e605c2 100644
> --- a/arch/arm/include/asm/arch-mx6/ccm_regs.h
> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
> @@ -20,7 +20,7 @@
>  #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
>  #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
>  
> -struct imx_ccm_reg {
> +struct mxc_ccm_reg {
>  	u32 ccr;	/* 0x0000 */
>  	u32 ccdr;
>  	u32 csr;
> diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
> index 668e77a..69687a8 100644
> --- a/arch/arm/include/asm/arch-mx6/sys_proto.h
> +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
> @@ -34,5 +34,6 @@ u32 get_cpu_rev(void);
>   */
>  
>  int fecmxc_initialize(bd_t *bis);
> -
> +u32 get_ahb_clk(void);
> +u32 get_periph_clk(void);
>  #endif

[U-Boot] [PATCH 3/5] mx5: Add clock config interface

[Fabio Estevam]

mx5: Add clock config interface

Add clock config interface support, so that we
can configure CPU or DDR clock in the later init

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Signed-off-by: Eric Miao <eric.miao@linaro.org>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 arch/arm/cpu/armv7/mx5/clock.c           |  532 +++++++++++++++++++++++++++++-
 arch/arm/include/asm/arch-mx5/clock.h    |    4 +
 arch/arm/include/asm/arch-mx5/crm_regs.h |    6 +
 3 files changed, 537 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index a1c8411..5edf188 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -24,6 +24,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
@@ -49,6 +50,42 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
 #endif
 };
 
+#define AHB_CLK_ROOT    133333333
+#define SZ_DEC_1M       1000000
+#define PLL_PD_MAX      16      /* Actual pd+1 */
+#define PLL_MFI_MAX     15
+#define PLL_MFI_MIN     5
+#define ARM_DIV_MAX     8
+#define IPG_DIV_MAX     4
+#define AHB_DIV_MAX     8
+#define EMI_DIV_MAX     8
+#define NFC_DIV_MAX     8
+
+#define MX5_CBCMR	0x00015154
+#define MX5_CBCDR	0x02888945
+
+struct fixed_pll_mfd {
+	u32 ref_clk_hz;
+	u32 mfd;
+};
+
+const struct fixed_pll_mfd fixed_mfd[] = {
+	{CONFIG_SYS_MX5_HCLK, 24 * 16},
+};
+
+struct pll_param {
+	u32 pd;
+	u32 mfi;
+	u32 mfn;
+	u32 mfd;
+};
+
+#define PLL_FREQ_MAX(ref_clk)  (4 * (ref_clk) * PLL_MFI_MAX)
+#define PLL_FREQ_MIN(ref_clk) \
+		((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+#define MAX_DDR_CLK     420000000
+#define NFC_CLK_MAX     34000000
+
 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 
 void set_usboh3_clk(void)
@@ -291,7 +328,7 @@ static u32 get_uart_clk(void)
 /*
  * This function returns the low power audio clock.
  */
-u32 get_lp_apm(void)
+static u32 get_lp_apm(void)
 {
 	u32 ret_val = 0;
 	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
@@ -307,7 +344,7 @@ u32 get_lp_apm(void)
 /*
  * get cspi clock rate.
  */
-u32 imx_get_cspiclk(void)
+static u32 imx_get_cspiclk(void)
 {
 	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
 	u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
@@ -344,8 +381,86 @@ u32 imx_get_cspiclk(void)
 	return ret_val;
 }
 
+static u32 get_axi_a_clk(void)
+{
+	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
+	u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
+			>> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
+
+	return  get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_axi_b_clk(void)
+{
+	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
+	u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
+			>> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
+
+	return  get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_emi_slow_clk(void)
+{
+	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
+	u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
+			>> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+
+	if (emi_clk_sel)
+		return  get_ahb_clk() / (pdf + 1);
+
+	return  get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_nfc_clk(void)
+{
+	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 pdf = (cbcdr & MXC_CCM_CBCDR_NFC_PODF_MASK) \
+			>> MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+
+	return  get_emi_slow_clk() / (pdf + 1);
+}
+
+static u32 get_ddr_clk(void)
+{
+	u32 ret_val = 0;
+	u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
+	u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
+				>> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+#ifdef CONFIG_MX51
+	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
+		u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
+					MXC_CCM_CBCDR_DDR_PODF_OFFSET;
+
+		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+		ret_val /= ddr_clk_podf + 1;
+
+		return ret_val;
+	}
+#endif
+	switch (ddr_clk_sel) {
+	case 0:
+		ret_val = get_axi_a_clk();
+		break;
+	case 1:
+		ret_val = get_axi_b_clk();
+		break;
+	case 2:
+		ret_val = get_emi_slow_clk();
+		break;
+	case 3:
+		ret_val = get_ahb_clk();
+		break;
+	default:
+		break;
+	}
+
+	return ret_val;
+}
+
 /*
- * The API of get mxc clockes.
+ * The API of get mxc clocks.
  */
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
@@ -365,6 +480,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_FEC_CLK:
 		return decode_pll(mxc_plls[PLL1_CLOCK],
 				    CONFIG_SYS_MX5_HCLK);
+	case MXC_DDR_CLK:
+		return get_ddr_clk();
 	default:
 		break;
 	}
@@ -383,7 +500,412 @@ u32 imx_get_fecclk(void)
 }
 
 /*
- * Dump some core clockes.
+ * Clock config code start here
+ */
+
+/* precondition: m>0 and n>0.  Let g=gcd(m,n). */
+static int gcd(int m, int n)
+{
+	int t;
+	while (m > 0) {
+		if (n > m) {
+			t = m;
+			m = n;
+			n = t;
+		} /* swap */
+		m -= n;
+	}
+	return n;
+}
+
+/*
+ * This is to calculate various parameters based on reference clock and
+ * targeted clock based on the equation:
+ *      t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
+ * This calculation is based on a fixed MFD value for simplicity.
+ */
+static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
+{
+	u64 pd, mfi = 1, mfn, mfd, t1;
+	u32 n_target = target;
+	u32 n_ref = ref, i;
+
+	/*
+	 * Make sure targeted freq is in the valid range.
+	 * Otherwise the following calculation might be wrong!!!
+	 */
+	if (n_target < PLL_FREQ_MIN(ref) ||
+		n_target > PLL_FREQ_MAX(ref)) {
+		printf("Targeted peripheral clock should be"
+			"within [%d - %d]\n",
+			PLL_FREQ_MIN(ref) / SZ_DEC_1M,
+			PLL_FREQ_MAX(ref) / SZ_DEC_1M);
+		return -1;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
+		if (fixed_mfd[i].ref_clk_hz == ref) {
+			mfd = fixed_mfd[i].mfd;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(fixed_mfd))
+		return -1;
+
+	/* Use n_target and n_ref to avoid overflow */
+	for (pd = 1; pd <= PLL_PD_MAX; pd++) {
+		t1 = n_target * pd;
+		do_div(t1, (4 * n_ref));
+		mfi = t1;
+		if (mfi > PLL_MFI_MAX)
+			return -1;
+		else if (mfi < 5)
+			continue;
+		break;
+	}
+	/*
+	 * Now got pd and mfi already
+	 *
+	 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
+	 */
+	t1 = n_target * pd;
+	do_div(t1, 4);
+	t1 -= n_ref * mfi;
+	t1 *= mfd;
+	do_div(t1, n_ref);
+	mfn = t1;
+	debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
+		ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
+	i = 1;
+	if (mfn != 0)
+		i = gcd(mfd, mfn);
+	pll->pd = (u32)pd;
+	pll->mfi = (u32)mfi;
+	do_div(mfn, i);
+	pll->mfn = (u32)mfn;
+	do_div(mfd, i);
+	pll->mfd = (u32)mfd;
+
+	return 0;
+}
+
+#define calc_div(tgt_clk, src_clk, limit) ({		\
+		u32 v = 0;				\
+		if (((src_clk) % (tgt_clk)) <= 100)	\
+			v = (src_clk) / (tgt_clk);	\
+		else					\
+			v = ((src_clk) / (tgt_clk)) + 1;\
+		if (v > limit)				\
+			v = limit;			\
+		(v - 1);				\
+	})
+
+static u32 calc_per_cbcdr_val(u32 per_clk)
+{
+	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 tmp_clk = 0, div = 0, clk_sel = 0;
+
+	cbcdr &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
+
+	/* emi_slow_podf divider */
+	tmp_clk = get_emi_slow_clk();
+	clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
+	if (clk_sel) {
+		div = calc_div(tmp_clk, per_clk, 8);
+		cbcdr &= ~MXC_CCM_CBCDR_EMI_PODF_MASK;
+		cbcdr |= (div << MXC_CCM_CBCDR_EMI_PODF_OFFSET);
+	}
+
+	/* axi_b_podf divider */
+	tmp_clk = get_axi_b_clk();
+	div = calc_div(tmp_clk, per_clk, 8);
+	cbcdr &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK;
+	cbcdr |= (div << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET);
+
+	/* axi_b_podf divider */
+	tmp_clk = get_axi_a_clk();
+	div = calc_div(tmp_clk, per_clk, 8);
+	cbcdr &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK;
+	cbcdr |= (div << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET);
+
+	/* ahb podf divider */
+	tmp_clk = AHB_CLK_ROOT;
+	div = calc_div(tmp_clk, per_clk, 8);
+	cbcdr &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
+	cbcdr |= (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET);
+
+	return cbcdr;
+}
+
+#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
+	{	\
+		__raw_writel(0x1232, &pll->ctrl);		\
+		__raw_writel(0x2, &pll->config);		\
+		__raw_writel((((pd) - 1) << 0) | ((fi) << 4),	\
+			&pll->op);				\
+		__raw_writel(fn, &(pll->mfn));			\
+		__raw_writel((fd) - 1, &pll->mfd);		\
+		__raw_writel((((pd) - 1) << 0) | ((fi) << 4),	\
+			&pll->hfs_op);				\
+		__raw_writel(fn, &pll->hfs_mfn);		\
+		__raw_writel((fd) - 1, &pll->hfs_mfd);		\
+		__raw_writel(0x1232, &pll->ctrl);		\
+		while (!__raw_readl(&pll->ctrl) & 0x1)		\
+			;\
+	}
+
+static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
+{
+	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+	struct mxc_pll_reg *pll = mxc_plls[index];
+
+	switch (index) {
+	case PLL1_CLOCK:
+		/* Switch ARM to PLL2 clock */
+		__raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
+		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+					pll_param->mfi, pll_param->mfn,
+					pll_param->mfd);
+		/* Switch back */
+		__raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
+		break;
+	case PLL2_CLOCK:
+		/* Switch to pll2 bypass clock */
+		__raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
+		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+					pll_param->mfi, pll_param->mfn,
+					pll_param->mfd);
+		/* Switch back */
+		__raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
+		break;
+	case PLL3_CLOCK:
+		/* Switch to pll3 bypass clock */
+		__raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
+		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+					pll_param->mfi, pll_param->mfn,
+					pll_param->mfd);
+		/* Switch back */
+		__raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
+		break;
+	case PLL4_CLOCK:
+		/* Switch to pll4 bypass clock */
+		__raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
+		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+					pll_param->mfi, pll_param->mfn,
+					pll_param->mfd);
+		/* Switch back */
+		__raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
+		break;
+	default:
+		return -1;
+	}
+
+	return 0;
+}
+
+/* Config CPU clock */
+static int config_core_clk(u32 ref, u32 freq)
+{
+	int ret = 0;
+	struct pll_param pll_param;
+
+	memset(&pll_param, 0, sizeof(struct pll_param));
+
+	/* The case that periph uses PLL1 is not considered here */
+	ret = calc_pll_params(ref, freq, &pll_param);
+	if (ret != 0) {
+		printf("Error:Can't find pll parameters: %d\n", ret);
+		return ret;
+	}
+
+	return config_pll_clk(PLL1_CLOCK, &pll_param);
+}
+
+static int config_nfc_clk(u32 nfc_clk)
+{
+	u32 reg;
+	u32 parent_rate = get_emi_slow_clk();
+	u32 div = parent_rate / nfc_clk;
+
+	if (nfc_clk <= 0)
+		return -1;
+	if (div == 0)
+		div++;
+	if (parent_rate / div > NFC_CLK_MAX)
+		div++;
+	reg = __raw_readl(&mxc_ccm->cbcdr);
+	reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
+	reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+	__raw_writel(reg, &mxc_ccm->cbcdr);
+	while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+		;
+	return 0;
+}
+
+/* Config main_bus_clock for periphs */
+static int config_periph_clk(u32 ref, u32 freq)
+{
+	int ret = 0;
+	struct pll_param pll_param;
+
+	memset(&pll_param, 0, sizeof(struct pll_param));
+
+	if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+		ret = calc_pll_params(ref, freq, &pll_param);
+		if (ret != 0) {
+			printf("Error:Can't find pll parameters: %d\n",
+				ret);
+			return ret;
+		}
+		switch ((__raw_readl(&mxc_ccm->cbcmr) & \
+			MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
+			MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+		case 0:
+			return config_pll_clk(PLL1_CLOCK, &pll_param);
+			break;
+		case 1:
+			return config_pll_clk(PLL3_CLOCK, &pll_param);
+			break;
+		default:
+			return -1;
+		}
+	} else {
+		u32 old_cbcmr = __raw_readl(&mxc_ccm->cbcmr);
+		u32 new_cbcdr = calc_per_cbcdr_val(freq);
+		u32 old_nfc = get_nfc_clk();
+
+		/* Switch peripheral to PLL3 */
+		__raw_writel(MX5_CBCMR, &mxc_ccm->cbcmr);
+		__raw_writel(MX5_CBCDR, &mxc_ccm->cbcdr);
+
+		/* Make sure change is effective */
+		while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+			;
+
+		/* Setup PLL2 */
+		ret = calc_pll_params(ref, freq, &pll_param);
+		if (ret != 0) {
+			printf("Error:Can't find pll parameters: %d\n",
+				ret);
+			return ret;
+		}
+		config_pll_clk(PLL2_CLOCK, &pll_param);
+
+		/* Switch peripheral back */
+		__raw_writel(new_cbcdr, &mxc_ccm->cbcdr);
+		__raw_writel(old_cbcmr, &mxc_ccm->cbcmr);
+
+		/* Make sure change is effective */
+		while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+			;
+		/* restore to old NFC clock */
+		config_nfc_clk(old_nfc);
+	}
+
+	return 0;
+}
+
+static int config_ddr_clk(u32 emi_clk)
+{
+	u32 clk_src;
+	s32 shift = 0, clk_sel, div = 1;
+	u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
+	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+
+	if (emi_clk > MAX_DDR_CLK) {
+		printf("Warning:DDR clock should not exceed %d MHz\n",
+			MAX_DDR_CLK / SZ_DEC_1M);
+		emi_clk = MAX_DDR_CLK;
+	}
+
+	clk_src = get_periph_clk();
+	/* Find DDR clock input */
+	clk_sel = (cbcmr >> 10) & 0x3;
+	switch (clk_sel) {
+	case 0:
+		shift = 16;
+		break;
+	case 1:
+		shift = 19;
+		break;
+	case 2:
+		shift = 22;
+		break;
+	case 3:
+		shift = 10;
+		break;
+	default:
+		return -1;
+	}
+
+	if ((clk_src % emi_clk) < 10000000)
+		div = clk_src / emi_clk;
+	else
+		div = (clk_src / emi_clk) + 1;
+	if (div > 8)
+		div = 8;
+
+	cbcdr = cbcdr & ~(0x7 << shift);
+	cbcdr |= ((div - 1) << shift);
+	__raw_writel(cbcdr, &mxc_ccm->cbcdr);
+	while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+		;
+	__raw_writel(0x0, &mxc_ccm->ccdr);
+
+	return 0;
+}
+
+/*
+ * This function assumes the expected core clock has to be changed by
+ * modifying the PLL. This is NOT true always but for most of the times,
+ * it is. So it assumes the PLL output freq is the same as the expected
+ * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
+ * In the latter case, it will try to increase the presc value until
+ * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
+ * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
+ * on the targeted PLL and reference input clock to the PLL. Lastly,
+ * it sets the register based on these values along with the dividers.
+ * Note 1) There is no value checking for the passed-in divider values
+ *         so the caller has to make sure those values are sensible.
+ *      2) Also adjust the NFC divider such that the NFC clock doesn't
+ *         exceed NFC_CLK_MAX.
+ *      3) IPU HSP clock is independent of AHB clock. Even it can go up to
+ *         177MHz for higher voltage, this function fixes the max to 133MHz.
+ *      4) This function should not have allowed diag_printf() calls since
+ *         the serial driver has been stoped. But leave then here to allow
+ *         easy debugging by NOT calling the cyg_hal_plf_serial_stop().
+ */
+int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
+{
+	freq *= SZ_DEC_1M;
+
+	switch (clk) {
+	case MXC_ARM_CLK:
+		if (config_core_clk(ref, freq))
+			return -1;
+		break;
+	case MXC_PERIPH_CLK:
+		if (config_periph_clk(ref, freq))
+			return -1;
+		break;
+	case MXC_DDR_CLK:
+		if (config_ddr_clk(freq))
+			return -1;
+		break;
+	case MXC_NFC_CLK:
+		if (config_nfc_clk(freq))
+			return -1;
+		break;
+	default:
+		printf("Warning:Unsupported or invalid clock type\n");
+	}
+
+	return 0;
+}
+
+/*
+ * Dump some core clocks.
  */
 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -399,11 +921,11 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
 	printf("PLL4       %8d MHz\n", freq / 1000000);
 #endif
-
 	printf("\n");
 	printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
 	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
 	printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
+	printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
 
 	return 0;
 }
diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index ea972a3..3840975 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -32,6 +32,9 @@ enum mxc_clock {
 	MXC_UART_CLK,
 	MXC_CSPI_CLK,
 	MXC_FEC_CLK,
+	MXC_DDR_CLK,
+	MXC_NFC_CLK,
+	MXC_PERIPH_CLK,
 };
 
 unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
@@ -39,6 +42,7 @@ unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
 u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
+int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
 
 void set_usb_phy2_clk(void);
 void enable_usb_phy2_clk(unsigned char enable);
diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index bdeafbc..4e0fc1b 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -76,6 +76,9 @@ struct mxc_ccm_reg {
 	u32 CCGR4;
 	u32 CCGR5;
 	u32 CCGR6;	/* 0x0080 */
+#ifdef CONFIG_MX53
+	u32 CCGR7;      /* 0x0084 */
+#endif
 	u32 cmeor;
 };
 
@@ -84,6 +87,9 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
 
 /* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL		(0x1 << 30)
+#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
+#define MXC_CCM_CBCDR_DDR_PODF_OFFSET		27
 #define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET		22
-- 
1.7.1

[U-Boot] [PATCH 3/5] mx5: Add clock config interface

[Fabio Estevam]

Hi Stefano,

On Tue, Mar 20, 2012 at 6:40 PM, Fabio Estevam
<fabio.estevam@freescale.com> wrote:
> mx5: Add clock config interface
>
> Add clock config interface support, so that we
> can configure CPU or DDR clock in the later init
>
> Signed-off-by: Jason Liu <jason.hui@linaro.org>
> Signed-off-by: Eric Miao <eric.miao@linaro.org>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

I saw that you applied this series into your next branch.

I am observing some problems with this patch in particular and I will
have to rework it.

Please drop patches 3, 4 and 5 from the series for now.

Thanks,

Fabio Estevam

[U-Boot] [PATCH 3/5] mx5: Add clock config interface

[Stefano Babic]

On 04/04/2012 00:13, Fabio Estevam wrote:
> Hi Stefano,
> 

Hi Fabio,

> On Tue, Mar 20, 2012 at 6:40 PM, Fabio Estevam
> <fabio.estevam@freescale.com> wrote:
>> mx5: Add clock config interface
>>
>> Add clock config interface support, so that we
>> can configure CPU or DDR clock in the later init
>>
>> Signed-off-by: Jason Liu <jason.hui@linaro.org>
>> Signed-off-by: Eric Miao <eric.miao@linaro.org>
>> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> 
> I saw that you applied this series into your next branch.

Right - this patchset makes a lot of changes for the clock, and
preparing a tree gives more opportunity for other people to test ;-)

> 
> I am observing some problems with this patch in particular and I will
> have to rework it.
> 
> Please drop patches 3, 4 and 5 from the series for now.

Ok, clear. I'll remove them.

Best regards,
Stefano Babic

-- 
=====================================================================
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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 4/5] mx53loco: Allow to print CPU information at a later stage

[Fabio Estevam]

Print CPU information within board_late_init().

This is in preparation for adding 1GHz support, which requires programming a PMIC
via I2C. As I2C is only available after relocation, print the CPU information
later at board_late_init(), so that the CPU frequency can be printed correctly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 arch/arm/cpu/armv7/imx-common/cpu.c       |    2 +-
 arch/arm/include/asm/arch-mx5/sys_proto.h |    2 +-
 board/freescale/mx53loco/mx53loco.c       |   22 ++++++++++++++++++++++
 include/configs/mx53loco.h                |    1 -
 4 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c
index 62b01e7..56db462 100644
--- a/arch/arm/cpu/armv7/imx-common/cpu.c
+++ b/arch/arm/cpu/armv7/imx-common/cpu.c
@@ -35,7 +35,7 @@
 #include <fsl_esdhc.h>
 #endif
 
-static char *get_reset_cause(void)
+char *get_reset_cause(void)
 {
 	u32 cause;
 	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index 7250059..36dfe02 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -36,5 +36,5 @@ void set_chipselect_size(int const);
 
 int fecmxc_initialize(bd_t *bis);
 u32 get_ahb_clk(void);
-
+char *get_reset_cause(void);
 #endif
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index d736141..64f5b07 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -298,6 +298,28 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int print_cpuinfo(void)
+{
+	u32 cpurev;
+
+	cpurev = get_cpu_rev();
+	printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
+		(cpurev & 0xFF000) >> 12,
+		(cpurev & 0x000F0) >> 4,
+		(cpurev & 0x0000F) >> 0,
+		mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("Reset cause: %s\n", get_reset_cause());
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	print_cpuinfo();
+	return 0;
+}
+#endif
+
 int board_init(void)
 {
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 34a4edd..eaba0bb 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -27,7 +27,6 @@
 
 #define CONFIG_SYS_MX5_HCLK	24000000
 #define CONFIG_SYS_MX5_CLK32		32768
-#define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_MACH_TYPE	MACH_TYPE_MX53_LOCO
-- 
1.7.1

[U-Boot] [PATCH 5/5] mx53loco: Add support for 1GHz operation for DA9053-based boards

[Fabio Estevam]

There are two types of mx53loco boards: initial boards were built with a Dialog
DA9053 PMIC and more recent version is based on a Freescale MC34708 PMIC.

Add DA9053 PMIC support and adjust the required voltages and clocks for running
the CPU at 1GHz.

Tested on both versions of mx53loco boards.

In the case of a MC34708-based board the CPU operating voltage remains at 800MHz.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 board/freescale/mx53loco/mx53loco.c |   72 +++++++++++++++++++++++++++++++++++
 include/configs/mx53loco.h          |   14 +++++++
 2 files changed, 86 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index a979329..60555b1 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -35,6 +35,8 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <asm/gpio.h>
+#include <pmic.h>
+#include <dialog_pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -290,6 +292,72 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+static void setup_iomux_i2c(void)
+{
+	/* I2C1 SDA */
+	mxc_request_iomux(MX53_PIN_CSI0_D8,
+		IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+	mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
+		PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	/* I2C1 SCL */
+	mxc_request_iomux(MX53_PIN_CSI0_D9,
+		IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+	mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
+		PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+static int power_init(void)
+{
+	unsigned int val, ret;
+	struct pmic *p;
+
+	pmic_init();
+	p = get_pmic();
+
+	int tmp;
+	/* Set VDDA to 1.25V */
+	val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
+	ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
+
+	ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+	val |= DA9052_SUPPLY_VBCOREGO;
+	ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+
+	/* Set Vcc peripheral to 1.35V */
+	ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
+	ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+
+	return ret;
+}
+
+static void clock_1GHz(void)
+{
+	int ret;
+	u32 ref_clk = CONFIG_SYS_MX5_HCLK;
+	/*
+	 * After increasing voltage to 1.25V, we can switch
+	 * CPU clock to 1GHz and DDR to 400MHz safely
+	 */
+	ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to 1GHZ failed\n");
+
+	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to 400MHz failed\n");
+}
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -315,7 +383,11 @@ int print_cpuinfo(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
+	setup_iomux_i2c();
+	if (!power_init())
+		clock_1GHz();
 	print_cpuinfo();
+
 	return 0;
 }
 #endif
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index eaba0bb..143b078 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -41,6 +41,7 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_MXC_UART
@@ -84,6 +85,19 @@
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
 
+/* I2C Configs */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX53_PORT1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0xfe
+
+/* PMIC Controller */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_DIALOG_PMIC
+#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR	0x48
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
-- 
1.7.1