From: Steven Newbury <steve@snewbury.org.uk>
To: Steven Newbury <steve@snewbury.org.uk>
Cc: Yinghai Lu <yinghai@kernel.org>,
"Barnes, Jesse" <jesse.barnes@intel.com>,
Dave Airlie <airlied@linux.ie>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org,
DRI mailing list <dri-devel@lists.freedesktop.org>
Subject: Re: PCI resources above 4GB
Date: Sat, 14 Apr 2012 20:21:39 +0100 [thread overview]
Message-ID: <4F89CE43.7040200@snewbury.org.uk> (raw)
In-Reply-To: <4F89CB16.2000908@snewbury.org.uk>
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Hash: SHA1
On 14/04/12 20:08, Steven Newbury wrote:
> On 14/04/12 19:42, Steven Newbury wrote:
>> On 14/04/12 19:05, Steven Newbury wrote:
>>> On 14/04/12 18:37, Steven Newbury wrote:
>>>> On 12/04/12 17:40, Steven Newbury wrote:
>>>>> On Thu, 12 Apr 2012, 17:07:33 BST, Yinghai Lu
>>>>> <yinghai@kernel.org> wrote:
>
>>>>>> On Thu, Apr 12, 2012 at 4:22 AM, Steven Newbury
>>>>>> <steve@snewbury.org.uk> wrote:
>>>>>>> Thanks, that fixed it! :) I had a similar patch I've
>>>>>>> been working on but I had my fix in the wrong place!
>>>>>>>
>>>>>>> In the working case, initially the BIOS has set GMA to
>>>>>>> within the low system DRAM 0xC0000000 obviously
>>>>>>> invalid. This conflict is detected and it's
>>>>>>> relallocated to 0x12000000.
>>>>>>>
>>>>>>> I've attempted to modify probe.c to disable 64-bit
>>>>>>> BARs not allocated above 4G so they get reallocated
>>>>>>> above when possible later. It seemed to work, but
>>>>>>> again broke GMA despite the BAR originally containing
>>>>>>> an invalid address as mentioned above, it seems for
>>>>>>> some reason something is different when the conflict is
>>>>>>> detected and rellocated, compared to disabling it early
>>>>>>> then allocating a valid value..?
>>>>>>>
>>>> I've created a new quirk utilising an extra PCI resource
>>>> flag to force reallocation of the resource. It's the first
>>>> approach I've had any success at. It does work. Only
>>>> "Intel Page Flush" now gets allocated @0xe0000000!
>
>
>>> Hopefully this should fix "Intel Flush Page"
>> Need to export pci_bus_alloc_resource_fit for intel-gtt.
> Nearly worked... Or at least it should have worked, but for some
> reason the allocator failed to utilise 0xe0000000-0xefffffff for
> 04:00.0 BAR0..?
>
>
> pci 0000:03:08.0: BAR 15: can't assign mem pref (size 0x18000000)
Ah! Not enough space for the bridge window!:(
> pci 0000:03:08.0: BAR 14: assigned [mem 0xfef00000-0xfeffffff] pci
> 0000:03:08.0: BAR 13: assigned [io 0x4000-0x4fff] pci
> 0000:04:00.0: BAR 0: can't assign mem pref (size 0x10000000) pci
> 0000:04:00.0: BAR 2: assigned [mem 0xfefe0000-0xfeffffff 64bit] pci
> 0000:04:00.0: BAR 2: set to [mem 0xfefe0000-0xfeffffff 64bit] (PCI
> address [0xfefe0000-0xfeffffff]) pci 0000:04:00.0: BAR 6: assigned
> [mem 0xfefc0000-0xfefdffff pref] pci 0000:04:00.1: BAR 0: assigned
> [mem 0xfefbc000-0xfefbffff 64bit] pci 0000:04:00.1: BAR 0: set to
> [mem 0xfefbc000-0xfefbffff 64bit] (PCI address
> [0xfefbc000-0xfefbffff]) pci 0000:04:00.0: BAR 4: assigned [io
> 0x4000-0x40ff] pci 0000:04:00.0: BAR 4: set to [io 0x4000-0x40ff]
> (PCI address [0x4000-0x40ff])
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WARNING: multiple messages have this Message-ID (diff)
From: Steven Newbury <steve@snewbury.org.uk>
To: Steven Newbury <steve@snewbury.org.uk>
Cc: Yinghai Lu <yinghai@kernel.org>,
"Barnes, Jesse" <jesse.barnes@intel.com>,
Dave Airlie <airlied@linux.ie>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org,
DRI mailing list <dri-devel@lists.freedesktop.org>
Subject: Re: PCI resources above 4GB
Date: Sat, 14 Apr 2012 20:21:39 +0100 [thread overview]
Message-ID: <4F89CE43.7040200@snewbury.org.uk> (raw)
In-Reply-To: <4F89CB16.2000908@snewbury.org.uk>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 14/04/12 20:08, Steven Newbury wrote:
> On 14/04/12 19:42, Steven Newbury wrote:
>> On 14/04/12 19:05, Steven Newbury wrote:
>>> On 14/04/12 18:37, Steven Newbury wrote:
>>>> On 12/04/12 17:40, Steven Newbury wrote:
>>>>> On Thu, 12 Apr 2012, 17:07:33 BST, Yinghai Lu
>>>>> <yinghai@kernel.org> wrote:
>
>>>>>> On Thu, Apr 12, 2012 at 4:22 AM, Steven Newbury
>>>>>> <steve@snewbury.org.uk> wrote:
>>>>>>> Thanks, that fixed it! :) I had a similar patch I've
>>>>>>> been working on but I had my fix in the wrong place!
>>>>>>>
>>>>>>> In the working case, initially the BIOS has set GMA to
>>>>>>> within the low system DRAM 0xC0000000 obviously
>>>>>>> invalid. This conflict is detected and it's
>>>>>>> relallocated to 0x12000000.
>>>>>>>
>>>>>>> I've attempted to modify probe.c to disable 64-bit
>>>>>>> BARs not allocated above 4G so they get reallocated
>>>>>>> above when possible later. It seemed to work, but
>>>>>>> again broke GMA despite the BAR originally containing
>>>>>>> an invalid address as mentioned above, it seems for
>>>>>>> some reason something is different when the conflict is
>>>>>>> detected and rellocated, compared to disabling it early
>>>>>>> then allocating a valid value..?
>>>>>>>
>>>> I've created a new quirk utilising an extra PCI resource
>>>> flag to force reallocation of the resource. It's the first
>>>> approach I've had any success at. It does work. Only
>>>> "Intel Page Flush" now gets allocated @0xe0000000!
>
>
>>> Hopefully this should fix "Intel Flush Page"
>> Need to export pci_bus_alloc_resource_fit for intel-gtt.
> Nearly worked... Or at least it should have worked, but for some
> reason the allocator failed to utilise 0xe0000000-0xefffffff for
> 04:00.0 BAR0..?
>
>
> pci 0000:03:08.0: BAR 15: can't assign mem pref (size 0x18000000)
Ah! Not enough space for the bridge window!:(
> pci 0000:03:08.0: BAR 14: assigned [mem 0xfef00000-0xfeffffff] pci
> 0000:03:08.0: BAR 13: assigned [io 0x4000-0x4fff] pci
> 0000:04:00.0: BAR 0: can't assign mem pref (size 0x10000000) pci
> 0000:04:00.0: BAR 2: assigned [mem 0xfefe0000-0xfeffffff 64bit] pci
> 0000:04:00.0: BAR 2: set to [mem 0xfefe0000-0xfeffffff 64bit] (PCI
> address [0xfefe0000-0xfeffffff]) pci 0000:04:00.0: BAR 6: assigned
> [mem 0xfefc0000-0xfefdffff pref] pci 0000:04:00.1: BAR 0: assigned
> [mem 0xfefbc000-0xfefbffff 64bit] pci 0000:04:00.1: BAR 0: set to
> [mem 0xfefbc000-0xfefbffff 64bit] (PCI address
> [0xfefbc000-0xfefbffff]) pci 0000:04:00.0: BAR 4: assigned [io
> 0x4000-0x40ff] pci 0000:04:00.0: BAR 4: set to [io 0x4000-0x40ff]
> (PCI address [0x4000-0x40ff])
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next prev parent reply other threads:[~2012-04-14 19:21 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-09 10:49 PCI resources above 4GB Steven Newbury
2012-04-10 0:51 ` Bjorn Helgaas
2012-04-10 10:53 ` Steven Newbury
2012-04-10 15:16 ` Yinghai Lu
[not found] ` <4F8467AA.90305@snewbury.org.uk>
2012-04-10 17:29 ` Steven Newbury
2012-04-10 18:40 ` Yinghai Lu
2012-04-10 18:44 ` Steven Newbury
2012-04-10 19:00 ` Steven Newbury
2012-04-10 19:04 ` Steven Newbury
2012-04-10 19:16 ` Yinghai Lu
2012-04-10 19:46 ` Steven Newbury
2012-04-10 20:07 ` Yinghai Lu
2012-04-10 20:26 ` Steven Newbury
2012-04-10 20:45 ` Yinghai Lu
2012-04-10 21:19 ` Steven Newbury
2012-04-11 3:37 ` Bjorn Helgaas
2012-04-11 5:33 ` Steven Newbury
2012-04-11 9:03 ` Steven Newbury
2012-04-11 14:33 ` Steven Newbury
2012-04-11 23:59 ` Bjorn Helgaas
2012-04-12 11:39 ` Steven Newbury
2012-04-12 0:57 ` Yinghai Lu
2012-04-12 11:22 ` Steven Newbury
2012-04-12 16:07 ` Yinghai Lu
2012-04-12 16:40 ` Steven Newbury
2012-04-13 8:26 ` Yinghai Lu
2012-04-13 8:34 ` Steven Newbury
2012-04-13 11:45 ` Steven Newbury
2012-04-13 11:58 ` Steven Newbury
2012-04-13 11:58 ` Steven Newbury
2012-04-13 12:49 ` Steven Newbury
2012-04-13 12:49 ` Steven Newbury
2012-04-13 13:26 ` Steven Newbury
2012-04-13 13:26 ` Steven Newbury
2012-04-13 13:52 ` drm-next i915 regression? ( was: Re: PCI resources above 4GB) Steven Newbury
2012-04-13 14:08 ` Steven Newbury
2012-04-13 14:08 ` Steven Newbury
2012-04-13 14:13 ` Daniel Vetter
2012-04-13 14:19 ` Steven Newbury
2012-04-13 15:23 ` Steven Newbury
2012-04-13 15:23 ` Steven Newbury
2012-04-13 15:49 ` Steven Newbury
2012-04-13 16:17 ` Yinghai Lu
2012-04-13 17:12 ` btrfs oops [was Re: drm-next i915 regression? ( was: Re: PCI resources above 4GB)] Steven Newbury
2012-04-13 17:38 ` drm-next i915 regression? ( was: Re: PCI resources above 4GB) Steven Newbury
2012-04-13 18:12 ` Steven Newbury
2012-04-13 21:51 ` Btrfs corruption Oops " Steven Newbury
2012-04-14 17:37 ` PCI resources above 4GB Steven Newbury
2012-04-14 17:37 ` Steven Newbury
2012-04-14 18:05 ` Steven Newbury
2012-04-14 18:05 ` Steven Newbury
2012-04-14 18:42 ` Steven Newbury
2012-04-14 18:42 ` Steven Newbury
2012-04-14 19:08 ` Steven Newbury
2012-04-14 19:08 ` Steven Newbury
2012-04-14 19:21 ` Steven Newbury [this message]
2012-04-14 19:21 ` Steven Newbury
2012-04-14 20:48 ` Yinghai Lu
2012-04-15 10:19 ` Steven Newbury
2012-04-15 10:19 ` Steven Newbury
2012-04-15 10:20 ` Steven Newbury
2012-04-15 10:20 ` Steven Newbury
2012-04-15 11:37 ` Steven Newbury
2012-04-15 11:37 ` Steven Newbury
2012-04-15 17:25 ` Steven Newbury
2012-04-15 17:25 ` Steven Newbury
2012-04-15 17:31 ` Steven Newbury
2012-04-15 17:31 ` Steven Newbury
2012-04-15 20:05 ` Yinghai Lu
2012-04-15 20:06 ` Yinghai Lu
2012-04-16 6:54 ` Yinghai Lu
2012-04-16 7:01 ` Steven Newbury
2012-04-16 7:01 ` Steven Newbury
2012-04-16 17:29 ` Yinghai Lu
2012-04-18 7:21 ` Steven Newbury
2012-04-18 7:21 ` Steven Newbury
2012-04-24 9:49 ` Steven Newbury
2012-04-24 9:49 ` Steven Newbury
[not found] ` <4FB227D3.7090002@snewbury.org.uk>
[not found] ` <CAE9FiQX48eCS85eWMFxm6fCWgu2zwxvSywtQhsf-35WEvBfJVQ@mail.gmail.com>
2012-05-17 12:27 ` Steven Newbury
2012-05-17 12:34 ` Steven Newbury
2012-05-17 16:36 ` Yinghai Lu
2012-05-18 7:45 ` Yinghai Lu
2012-05-18 9:08 ` Yinghai Lu
2012-05-21 17:27 ` Steven Newbury
2012-05-21 17:27 ` Steven Newbury
2012-05-29 23:19 ` Bjorn Helgaas
2012-06-01 23:06 ` Bjorn Helgaas
2012-04-15 3:21 ` Yinghai Lu
2012-04-15 10:18 ` Steven Newbury
2012-04-15 10:18 ` Steven Newbury
2012-04-15 11:31 ` Steven Newbury
2012-04-15 11:31 ` Steven Newbury
2012-04-12 16:29 ` Steven Newbury
2012-04-11 11:43 ` Steven Newbury
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