From: Scott Wood <scottwood@freescale.com>
To: Simon Glass <sjg@chromium.org>
Cc: Devicetree@theia.denx.de,
Discuss <devicetree-discuss@lists.ozlabs.org>,
Jim Lin <jilin@nvidia.com>,
U-Boot Mailing List <u-boot@lists.denx.de>,
Jerry Van Baren <vanbaren@cideas.com>,
Tom Warren <twarren@nvidia.com>
Subject: Re: [PATCH v3 4/7] tegra: fdt: Add NAND controller binding and definitions
Date: Tue, 17 Apr 2012 15:49:08 -0500 [thread overview]
Message-ID: <4F8DD744.1080702@freescale.com> (raw)
In-Reply-To: <CAPnjgZ2OESUgpMb-L0AdJ3EbOzO2Y1GRykuudKpPu2Yyjsh_NA@mail.gmail.com>
On 04/17/2012 03:36 PM, Simon Glass wrote:
> Hi Scott,
>
> On Tue, Apr 17, 2012 at 1:31 PM, Scott Wood <scottwood@freescale.com> wrote:
>> On 04/17/2012 03:18 PM, Simon Glass wrote:
>>> On Tue, Apr 17, 2012 at 12:06 PM, Scott Wood <scottwood@freescale.com> wrote:
>>>> Doesn't the number of cells depend on the GPIO controller binding?
>>>
>>> Yes, but this is the binding Tegra uses.
>>
>> Still, it doesn't belong in the NAND binding. Maybe a future chip wants
>> to use this NAND binding but a different GPIO binding. If nothing else,
>> people tend to copy-and-paste such descriptions. We've still got people
>> adding bindings for Freescale devices saying interrupts are encoded as a
>> pair of cells, even though the interrupt controller now uses four cells
>> per interrupt.
>
> OK I see - are you are saying that we should just say something like:
>
> "nvidia,wp-gpios : GPIO of write-protect line, as defined by gpio bindings"
Yes. If there were more than one GPIO line, you'd specify which one is
which, similar to reg and interrupts.
-Scott
WARNING: multiple messages have this Message-ID (diff)
From: Scott Wood <scottwood@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 4/7] tegra: fdt: Add NAND controller binding and definitions
Date: Tue, 17 Apr 2012 15:49:08 -0500 [thread overview]
Message-ID: <4F8DD744.1080702@freescale.com> (raw)
In-Reply-To: <CAPnjgZ2OESUgpMb-L0AdJ3EbOzO2Y1GRykuudKpPu2Yyjsh_NA@mail.gmail.com>
On 04/17/2012 03:36 PM, Simon Glass wrote:
> Hi Scott,
>
> On Tue, Apr 17, 2012 at 1:31 PM, Scott Wood <scottwood@freescale.com> wrote:
>> On 04/17/2012 03:18 PM, Simon Glass wrote:
>>> On Tue, Apr 17, 2012 at 12:06 PM, Scott Wood <scottwood@freescale.com> wrote:
>>>> Doesn't the number of cells depend on the GPIO controller binding?
>>>
>>> Yes, but this is the binding Tegra uses.
>>
>> Still, it doesn't belong in the NAND binding. Maybe a future chip wants
>> to use this NAND binding but a different GPIO binding. If nothing else,
>> people tend to copy-and-paste such descriptions. We've still got people
>> adding bindings for Freescale devices saying interrupts are encoded as a
>> pair of cells, even though the interrupt controller now uses four cells
>> per interrupt.
>
> OK I see - are you are saying that we should just say something like:
>
> "nvidia,wp-gpios : GPIO of write-protect line, as defined by gpio bindings"
Yes. If there were more than one GPIO line, you'd specify which one is
which, similar to reg and interrupts.
-Scott
next prev parent reply other threads:[~2012-04-17 20:49 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-17 18:50 [U-Boot] [PATCH v3 0/7] tegra: Add NAND flash support Simon Glass
2012-04-17 18:50 ` [U-Boot] [PATCH v3 1/7] nand: Try to align the default buffers Simon Glass
2012-04-17 18:50 ` [PATCH v3 2/7] fdt: Add debugging to fdtdec_get_int/addr() Simon Glass
2012-04-17 18:50 ` [U-Boot] " Simon Glass
2012-04-17 18:50 ` [U-Boot] [PATCH v3 3/7] tegra: Add NAND support to funcmux Simon Glass
2012-04-17 18:50 ` [PATCH v3 4/7] tegra: fdt: Add NAND controller binding and definitions Simon Glass
2012-04-17 18:50 ` [U-Boot] " Simon Glass
2012-04-17 19:06 ` Scott Wood
2012-04-17 19:06 ` [U-Boot] " Scott Wood
2012-04-17 20:18 ` Simon Glass
2012-04-17 20:18 ` [U-Boot] " Simon Glass
2012-04-17 20:31 ` Scott Wood
2012-04-17 20:31 ` [U-Boot] " Scott Wood
2012-04-17 20:36 ` Simon Glass
2012-04-17 20:36 ` [U-Boot] " Simon Glass
2012-04-17 20:49 ` Scott Wood [this message]
2012-04-17 20:49 ` Scott Wood
[not found] ` <1334688614-4977-1-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2012-04-17 18:50 ` [PATCH v3 5/7] tegra: fdt: Add NAND definitions to fdt Simon Glass
2012-04-17 18:50 ` [U-Boot] " Simon Glass
2012-04-17 18:50 ` [U-Boot] [PATCH v3 6/7] tegra: nand: Add Tegra NAND driver Simon Glass
2012-04-25 22:17 ` Scott Wood
[not found] ` <4B9C9637D5087840A465BDCB251780E9E2D5582388@HKMAIL02.nvidia.com>
2012-05-21 15:47 ` Scott Wood
2012-05-22 20:04 ` Simon Glass
2012-05-22 20:06 ` Scott Wood
2012-05-22 20:24 ` Simon Glass
2012-05-22 20:29 ` Scott Wood
[not found] ` <4B9C9637D5087840A465BDCB251780E9E2D6EDA3FA@HKMAIL02.nvidia.com>
2012-07-06 1:28 ` Scott Wood
2012-07-06 15:40 ` Stephen Warren
2012-04-17 18:50 ` [U-Boot] [PATCH v3 7/7] tegra: Enable NAND on Seaboard Simon Glass
2012-04-26 10:50 ` [U-Boot] [PATCH v3 0/7] tegra: Add NAND flash support Thierry Reding
2012-04-26 15:13 ` Stephen Warren
2012-04-26 18:32 ` Thierry Reding
2012-04-26 19:20 ` Stephen Warren
2012-04-27 5:10 ` Thierry Reding
2012-04-27 15:37 ` Stephen Warren
2012-04-28 11:39 ` Thierry Reding
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