* [PATCH 1/2] KVM: PPC: bookehv: Fix r8/r13 storing in level exception handler @ 2012-04-16 14:08 ` Mihai Caraman 0 siblings, 0 replies; 12+ messages in thread From: Mihai Caraman @ 2012-04-16 14:08 UTC (permalink / raw) To: kvm-ppc; +Cc: kvm, Mihai Caraman Guest r8 register is held in the scratch register and stored correctly, so remove the instruction that clobbers it. Guest r13 was missing from vcpu, store it there. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> --- arch/powerpc/kvm/bookehv_interrupts.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index 0d04bc9..0ca987d 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -264,10 +264,10 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1) mfspr r6, \srr1 PPC_LL r4, GPR11(r8) PPC_STL r7, VCPU_GPR(r7)(r11) - PPC_STL r8, VCPU_GPR(r8)(r11) PPC_STL r3, VCPU_GPR(r10)(r11) mfctr r7 PPC_STL r12, VCPU_GPR(r12)(r11) + PPC_STL r13, VCPU_GPR(r13)(r11) PPC_STL r4, VCPU_GPR(r11)(r11) PPC_STL r7, VCPU_CTR(r11) mr r4, r11 -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/2] KVM: PPC: bookehv: Fix r8/r13 storing in level exception handler @ 2012-04-16 14:08 ` Mihai Caraman 0 siblings, 0 replies; 12+ messages in thread From: Mihai Caraman @ 2012-04-16 14:08 UTC (permalink / raw) To: kvm-ppc; +Cc: kvm, Mihai Caraman Guest r8 register is held in the scratch register and stored correctly, so remove the instruction that clobbers it. Guest r13 was missing from vcpu, store it there. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> --- arch/powerpc/kvm/bookehv_interrupts.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index 0d04bc9..0ca987d 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -264,10 +264,10 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1) mfspr r6, \srr1 PPC_LL r4, GPR11(r8) PPC_STL r7, VCPU_GPR(r7)(r11) - PPC_STL r8, VCPU_GPR(r8)(r11) PPC_STL r3, VCPU_GPR(r10)(r11) mfctr r7 PPC_STL r12, VCPU_GPR(r12)(r11) + PPC_STL r13, VCPU_GPR(r13)(r11) PPC_STL r4, VCPU_GPR(r11)(r11) PPC_STL r7, VCPU_CTR(r11) mr r4, r11 -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] KVM: PPC: bookehv: Use lwz/stw instead of PPC_LL/PPC_STL for 32-bit fields 2012-04-16 14:08 ` Mihai Caraman @ 2012-04-16 14:08 ` Mihai Caraman -1 siblings, 0 replies; 12+ messages in thread From: Mihai Caraman @ 2012-04-16 14:08 UTC (permalink / raw) To: kvm-ppc; +Cc: kvm, Mihai Caraman Interrupt code used PPC_LL/PPC_STL macros to load/store some of u32 fields which led to memory overflow on 64-bit. Use lwz/stw instead. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> --- arch/powerpc/kvm/bookehv_interrupts.S | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index 0ca987d..e351c53 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -95,9 +95,9 @@ mfspr r8, SPRN_TBRL mfspr r9, SPRN_TBRU cmpw r9, r7 - PPC_STL r8, VCPU_TIMING_EXIT_TBL(r4) + stw r8, VCPU_TIMING_EXIT_TBL(r4) bne- 1b - PPC_STL r9, VCPU_TIMING_EXIT_TBU(r4) + stw r9, VCPU_TIMING_EXIT_TBU(r4) #endif oris r8, r6, MSR_CE@h @@ -228,7 +228,7 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1) PPC_STL r4, VCPU_GPR(r4)(r11) PPC_LL r4, THREAD_NORMSAVE(0)(r10) PPC_STL r5, VCPU_GPR(r5)(r11) - PPC_STL r13, VCPU_CR(r11) + stw r13, VCPU_CR(r11) mfspr r5, \srr0 PPC_STL r3, VCPU_GPR(r10)(r11) PPC_LL r3, THREAD_NORMSAVE(2)(r10) @@ -255,7 +255,7 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1) PPC_STL r4, VCPU_GPR(r4)(r11) PPC_LL r4, GPR9(r8) PPC_STL r5, VCPU_GPR(r5)(r11) - PPC_STL r9, VCPU_CR(r11) + stw r9, VCPU_CR(r11) mfspr r5, \srr0 PPC_STL r3, VCPU_GPR(r8)(r11) PPC_LL r3, GPR10(r8) @@ -327,7 +327,7 @@ _GLOBAL(kvmppc_resume_host) mfspr r6, SPRN_SPRG4 PPC_STL r5, VCPU_LR(r4) mfspr r7, SPRN_SPRG5 - PPC_STL r3, VCPU_VRSAVE(r4) + stw r3, VCPU_VRSAVE(r4) PPC_STD(r6, VCPU_SHARED_SPRG4, r11) mfspr r8, SPRN_SPRG6 PPC_STD(r7, VCPU_SHARED_SPRG5, r11) @@ -571,7 +571,7 @@ lightweight_exit: PPC_LL r3, VCPU_LR(r4) PPC_LL r5, VCPU_XER(r4) PPC_LL r6, VCPU_CTR(r4) - PPC_LL r7, VCPU_CR(r4) + lwz r7, VCPU_CR(r4) PPC_LL r8, VCPU_PC(r4) #ifdef CONFIG_64BIT ld r9, (VCPU_SHARED_MSR)(r11) @@ -598,9 +598,9 @@ lightweight_exit: mfspr r9, SPRN_TBRL mfspr r8, SPRN_TBRU cmpw r8, r6 - PPC_STL r9, VCPU_TIMING_LAST_ENTER_TBL(r4) + stw r9, VCPU_TIMING_LAST_ENTER_TBL(r4) bne 1b - PPC_STL r8, VCPU_TIMING_LAST_ENTER_TBU(r4) + stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4) #endif /* -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] KVM: PPC: bookehv: Use lwz/stw instead of PPC_LL/PPC_STL for 32-bit fields @ 2012-04-16 14:08 ` Mihai Caraman 0 siblings, 0 replies; 12+ messages in thread From: Mihai Caraman @ 2012-04-16 14:08 UTC (permalink / raw) To: kvm-ppc; +Cc: kvm, Mihai Caraman Interrupt code used PPC_LL/PPC_STL macros to load/store some of u32 fields which led to memory overflow on 64-bit. Use lwz/stw instead. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> --- arch/powerpc/kvm/bookehv_interrupts.S | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index 0ca987d..e351c53 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -95,9 +95,9 @@ mfspr r8, SPRN_TBRL mfspr r9, SPRN_TBRU cmpw r9, r7 - PPC_STL r8, VCPU_TIMING_EXIT_TBL(r4) + stw r8, VCPU_TIMING_EXIT_TBL(r4) bne- 1b - PPC_STL r9, VCPU_TIMING_EXIT_TBU(r4) + stw r9, VCPU_TIMING_EXIT_TBU(r4) #endif oris r8, r6, MSR_CE@h @@ -228,7 +228,7 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1) PPC_STL r4, VCPU_GPR(r4)(r11) PPC_LL r4, THREAD_NORMSAVE(0)(r10) PPC_STL r5, VCPU_GPR(r5)(r11) - PPC_STL r13, VCPU_CR(r11) + stw r13, VCPU_CR(r11) mfspr r5, \srr0 PPC_STL r3, VCPU_GPR(r10)(r11) PPC_LL r3, THREAD_NORMSAVE(2)(r10) @@ -255,7 +255,7 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1) PPC_STL r4, VCPU_GPR(r4)(r11) PPC_LL r4, GPR9(r8) PPC_STL r5, VCPU_GPR(r5)(r11) - PPC_STL r9, VCPU_CR(r11) + stw r9, VCPU_CR(r11) mfspr r5, \srr0 PPC_STL r3, VCPU_GPR(r8)(r11) PPC_LL r3, GPR10(r8) @@ -327,7 +327,7 @@ _GLOBAL(kvmppc_resume_host) mfspr r6, SPRN_SPRG4 PPC_STL r5, VCPU_LR(r4) mfspr r7, SPRN_SPRG5 - PPC_STL r3, VCPU_VRSAVE(r4) + stw r3, VCPU_VRSAVE(r4) PPC_STD(r6, VCPU_SHARED_SPRG4, r11) mfspr r8, SPRN_SPRG6 PPC_STD(r7, VCPU_SHARED_SPRG5, r11) @@ -571,7 +571,7 @@ lightweight_exit: PPC_LL r3, VCPU_LR(r4) PPC_LL r5, VCPU_XER(r4) PPC_LL r6, VCPU_CTR(r4) - PPC_LL r7, VCPU_CR(r4) + lwz r7, VCPU_CR(r4) PPC_LL r8, VCPU_PC(r4) #ifdef CONFIG_64BIT ld r9, (VCPU_SHARED_MSR)(r11) @@ -598,9 +598,9 @@ lightweight_exit: mfspr r9, SPRN_TBRL mfspr r8, SPRN_TBRU cmpw r8, r6 - PPC_STL r9, VCPU_TIMING_LAST_ENTER_TBL(r4) + stw r9, VCPU_TIMING_LAST_ENTER_TBL(r4) bne 1b - PPC_STL r8, VCPU_TIMING_LAST_ENTER_TBU(r4) + stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4) #endif /* -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] KVM: PPC: bookehv: Use lwz/stw instead of PPC_LL/PPC_STL for 32-bit fields 2012-04-16 14:08 ` Mihai Caraman @ 2012-04-26 11:40 ` Alexander Graf -1 siblings, 0 replies; 12+ messages in thread From: Alexander Graf @ 2012-04-26 11:40 UTC (permalink / raw) To: Mihai Caraman; +Cc: kvm-ppc, kvm On 16.04.2012, at 16:08, Mihai Caraman wrote: > Interrupt code used PPC_LL/PPC_STL macros to load/store some of u32 fields > which led to memory overflow on 64-bit. Use lwz/stw instead. Phew, pretty ugly :). Applied to kvm-ppc-next. Alex ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] KVM: PPC: bookehv: Use lwz/stw instead of PPC_LL/PPC_STL for 32-bit fields @ 2012-04-26 11:40 ` Alexander Graf 0 siblings, 0 replies; 12+ messages in thread From: Alexander Graf @ 2012-04-26 11:40 UTC (permalink / raw) To: Mihai Caraman; +Cc: kvm-ppc, kvm On 16.04.2012, at 16:08, Mihai Caraman wrote: > Interrupt code used PPC_LL/PPC_STL macros to load/store some of u32 fields > which led to memory overflow on 64-bit. Use lwz/stw instead. Phew, pretty ugly :). Applied to kvm-ppc-next. Alex ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] KVM: PPC: bookehv: Fix r8/r13 storing in level exception handler 2012-04-16 14:08 ` Mihai Caraman @ 2012-04-26 11:36 ` Alexander Graf -1 siblings, 0 replies; 12+ messages in thread From: Alexander Graf @ 2012-04-26 11:36 UTC (permalink / raw) To: Mihai Caraman; +Cc: kvm-ppc, kvm On 16.04.2012, at 16:08, Mihai Caraman wrote: > Guest r8 register is held in the scratch register and stored correctly, > so remove the instruction that clobbers it. Guest r13 was missing from vcpu, > store it there. > > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> > --- > arch/powerpc/kvm/bookehv_interrupts.S | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S > index 0d04bc9..0ca987d 100644 > --- a/arch/powerpc/kvm/bookehv_interrupts.S > +++ b/arch/powerpc/kvm/bookehv_interrupts.S > @@ -264,10 +264,10 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1) > mfspr r6, \srr1 > PPC_LL r4, GPR11(r8) > PPC_STL r7, VCPU_GPR(r7)(r11) > - PPC_STL r8, VCPU_GPR(r8)(r11) I'm not sure I can follow you here. The code that leads up to this is: #define NORMAL_EXCEPTION_PROLOG(intno) \ mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ mfspr r10, SPRN_SPRG_THREAD; \ stw r11, THREAD_NORMSAVE(0)(r10); \ stw r13, THREAD_NORMSAVE(2)(r10); \ mfcr r13; /* save CR in r13 for now */\ mfspr r11, SPRN_SRR1; \ DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \ [...] .macro DO_KVM intno srr1 #ifdef CONFIG_KVM_BOOKE_HV BEGIN_FTR_SECTION mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */ bf 3, kvmppc_resume_\intno\()_\srr1 b kvmppc_handler_\intno\()_\srr1 kvmppc_resume_\intno\()_\srr1: END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) #endif .endm [...] So where is r8 held in a scratch register here? The only registers that I can see stored in scratch registers are r10, r11, r13 > PPC_STL r3, VCPU_GPR(r10)(r11) > mfctr r7 > PPC_STL r12, VCPU_GPR(r12)(r11) > + PPC_STL r13, VCPU_GPR(r13)(r11) r13 however is in a scratch register / scratch memory location according to the code above :). Alex ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] KVM: PPC: bookehv: Fix r8/r13 storing in level exception handler @ 2012-04-26 11:36 ` Alexander Graf 0 siblings, 0 replies; 12+ messages in thread From: Alexander Graf @ 2012-04-26 11:36 UTC (permalink / raw) To: Mihai Caraman; +Cc: kvm-ppc, kvm On 16.04.2012, at 16:08, Mihai Caraman wrote: > Guest r8 register is held in the scratch register and stored correctly, > so remove the instruction that clobbers it. Guest r13 was missing from vcpu, > store it there. > > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> > --- > arch/powerpc/kvm/bookehv_interrupts.S | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S > index 0d04bc9..0ca987d 100644 > --- a/arch/powerpc/kvm/bookehv_interrupts.S > +++ b/arch/powerpc/kvm/bookehv_interrupts.S > @@ -264,10 +264,10 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1) > mfspr r6, \srr1 > PPC_LL r4, GPR11(r8) > PPC_STL r7, VCPU_GPR(r7)(r11) > - PPC_STL r8, VCPU_GPR(r8)(r11) I'm not sure I can follow you here. The code that leads up to this is: #define NORMAL_EXCEPTION_PROLOG(intno) \ mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ mfspr r10, SPRN_SPRG_THREAD; \ stw r11, THREAD_NORMSAVE(0)(r10); \ stw r13, THREAD_NORMSAVE(2)(r10); \ mfcr r13; /* save CR in r13 for now */\ mfspr r11, SPRN_SRR1; \ DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \ [...] .macro DO_KVM intno srr1 #ifdef CONFIG_KVM_BOOKE_HV BEGIN_FTR_SECTION mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */ bf 3, kvmppc_resume_\intno\()_\srr1 b kvmppc_handler_\intno\()_\srr1 kvmppc_resume_\intno\()_\srr1: END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) #endif .endm [...] So where is r8 held in a scratch register here? The only registers that I can see stored in scratch registers are r10, r11, r13 > PPC_STL r3, VCPU_GPR(r10)(r11) > mfctr r7 > PPC_STL r12, VCPU_GPR(r12)(r11) > + PPC_STL r13, VCPU_GPR(r13)(r11) r13 however is in a scratch register / scratch memory location according to the code above :). Alex ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] KVM: PPC: bookehv: Fix r8/r13 storing in level exception handler 2012-04-26 11:36 ` Alexander Graf @ 2012-04-26 17:43 ` Scott Wood -1 siblings, 0 replies; 12+ messages in thread From: Scott Wood @ 2012-04-26 17:43 UTC (permalink / raw) To: Alexander Graf; +Cc: Mihai Caraman, kvm-ppc, kvm On 04/26/2012 06:36 AM, Alexander Graf wrote: > > On 16.04.2012, at 16:08, Mihai Caraman wrote: > >> Guest r8 register is held in the scratch register and stored correctly, >> so remove the instruction that clobbers it. Guest r13 was missing from vcpu, >> store it there. >> >> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> >> --- >> arch/powerpc/kvm/bookehv_interrupts.S | 2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S >> index 0d04bc9..0ca987d 100644 >> --- a/arch/powerpc/kvm/bookehv_interrupts.S >> +++ b/arch/powerpc/kvm/bookehv_interrupts.S >> @@ -264,10 +264,10 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1) >> mfspr r6, \srr1 >> PPC_LL r4, GPR11(r8) >> PPC_STL r7, VCPU_GPR(r7)(r11) >> - PPC_STL r8, VCPU_GPR(r8)(r11) > > I'm not sure I can follow you here. The code that leads up to this is: > > #define NORMAL_EXCEPTION_PROLOG(intno) \ > mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ > mfspr r10, SPRN_SPRG_THREAD; \ > stw r11, THREAD_NORMSAVE(0)(r10); \ > stw r13, THREAD_NORMSAVE(2)(r10); \ > mfcr r13; /* save CR in r13 for now */\ > mfspr r11, SPRN_SRR1; \ > DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \ See the subject line -- this is for level exceptions (EXC_LEVEL_EXCEPTION_PROLOG), not normal exceptions. -Scott ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] KVM: PPC: bookehv: Fix r8/r13 storing in level exception handler @ 2012-04-26 17:43 ` Scott Wood 0 siblings, 0 replies; 12+ messages in thread From: Scott Wood @ 2012-04-26 17:43 UTC (permalink / raw) To: Alexander Graf; +Cc: Mihai Caraman, kvm-ppc, kvm On 04/26/2012 06:36 AM, Alexander Graf wrote: > > On 16.04.2012, at 16:08, Mihai Caraman wrote: > >> Guest r8 register is held in the scratch register and stored correctly, >> so remove the instruction that clobbers it. Guest r13 was missing from vcpu, >> store it there. >> >> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> >> --- >> arch/powerpc/kvm/bookehv_interrupts.S | 2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S >> index 0d04bc9..0ca987d 100644 >> --- a/arch/powerpc/kvm/bookehv_interrupts.S >> +++ b/arch/powerpc/kvm/bookehv_interrupts.S >> @@ -264,10 +264,10 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1) >> mfspr r6, \srr1 >> PPC_LL r4, GPR11(r8) >> PPC_STL r7, VCPU_GPR(r7)(r11) >> - PPC_STL r8, VCPU_GPR(r8)(r11) > > I'm not sure I can follow you here. The code that leads up to this is: > > #define NORMAL_EXCEPTION_PROLOG(intno) \ > mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ > mfspr r10, SPRN_SPRG_THREAD; \ > stw r11, THREAD_NORMSAVE(0)(r10); \ > stw r13, THREAD_NORMSAVE(2)(r10); \ > mfcr r13; /* save CR in r13 for now */\ > mfspr r11, SPRN_SRR1; \ > DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \ See the subject line -- this is for level exceptions (EXC_LEVEL_EXCEPTION_PROLOG), not normal exceptions. -Scott ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] KVM: PPC: bookehv: Fix r8/r13 storing in level exception handler 2012-04-26 17:43 ` Scott Wood @ 2012-05-02 11:12 ` Alexander Graf -1 siblings, 0 replies; 12+ messages in thread From: Alexander Graf @ 2012-05-02 11:12 UTC (permalink / raw) To: Scott Wood; +Cc: Mihai Caraman, kvm-ppc, kvm On 04/26/2012 07:43 PM, Scott Wood wrote: > On 04/26/2012 06:36 AM, Alexander Graf wrote: >> On 16.04.2012, at 16:08, Mihai Caraman wrote: >> >>> Guest r8 register is held in the scratch register and stored correctly, >>> so remove the instruction that clobbers it. Guest r13 was missing from vcpu, >>> store it there. >>> >>> Signed-off-by: Mihai Caraman<mihai.caraman@freescale.com> >>> --- >>> arch/powerpc/kvm/bookehv_interrupts.S | 2 +- >>> 1 files changed, 1 insertions(+), 1 deletions(-) >>> >>> diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S >>> index 0d04bc9..0ca987d 100644 >>> --- a/arch/powerpc/kvm/bookehv_interrupts.S >>> +++ b/arch/powerpc/kvm/bookehv_interrupts.S >>> @@ -264,10 +264,10 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1) >>> mfspr r6, \srr1 >>> PPC_LL r4, GPR11(r8) >>> PPC_STL r7, VCPU_GPR(r7)(r11) >>> - PPC_STL r8, VCPU_GPR(r8)(r11) >> I'm not sure I can follow you here. The code that leads up to this is: >> >> #define NORMAL_EXCEPTION_PROLOG(intno) \ >> mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ >> mfspr r10, SPRN_SPRG_THREAD; \ >> stw r11, THREAD_NORMSAVE(0)(r10); \ >> stw r13, THREAD_NORMSAVE(2)(r10); \ >> mfcr r13; /* save CR in r13 for now */\ >> mfspr r11, SPRN_SRR1; \ >> DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \ > See the subject line -- this is for level exceptions > (EXC_LEVEL_EXCEPTION_PROLOG), not normal exceptions. Ah, my bad. Sorry. Thanks, applied to kvm-ppc-next. Alex ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] KVM: PPC: bookehv: Fix r8/r13 storing in level exception handler @ 2012-05-02 11:12 ` Alexander Graf 0 siblings, 0 replies; 12+ messages in thread From: Alexander Graf @ 2012-05-02 11:12 UTC (permalink / raw) To: Scott Wood; +Cc: Mihai Caraman, kvm-ppc, kvm On 04/26/2012 07:43 PM, Scott Wood wrote: > On 04/26/2012 06:36 AM, Alexander Graf wrote: >> On 16.04.2012, at 16:08, Mihai Caraman wrote: >> >>> Guest r8 register is held in the scratch register and stored correctly, >>> so remove the instruction that clobbers it. Guest r13 was missing from vcpu, >>> store it there. >>> >>> Signed-off-by: Mihai Caraman<mihai.caraman@freescale.com> >>> --- >>> arch/powerpc/kvm/bookehv_interrupts.S | 2 +- >>> 1 files changed, 1 insertions(+), 1 deletions(-) >>> >>> diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S >>> index 0d04bc9..0ca987d 100644 >>> --- a/arch/powerpc/kvm/bookehv_interrupts.S >>> +++ b/arch/powerpc/kvm/bookehv_interrupts.S >>> @@ -264,10 +264,10 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1) >>> mfspr r6, \srr1 >>> PPC_LL r4, GPR11(r8) >>> PPC_STL r7, VCPU_GPR(r7)(r11) >>> - PPC_STL r8, VCPU_GPR(r8)(r11) >> I'm not sure I can follow you here. The code that leads up to this is: >> >> #define NORMAL_EXCEPTION_PROLOG(intno) \ >> mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ >> mfspr r10, SPRN_SPRG_THREAD; \ >> stw r11, THREAD_NORMSAVE(0)(r10); \ >> stw r13, THREAD_NORMSAVE(2)(r10); \ >> mfcr r13; /* save CR in r13 for now */\ >> mfspr r11, SPRN_SRR1; \ >> DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \ > See the subject line -- this is for level exceptions > (EXC_LEVEL_EXCEPTION_PROLOG), not normal exceptions. Ah, my bad. Sorry. Thanks, applied to kvm-ppc-next. Alex ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2012-05-02 11:12 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2012-04-16 14:08 [PATCH 1/2] KVM: PPC: bookehv: Fix r8/r13 storing in level exception handler Mihai Caraman 2012-04-16 14:08 ` Mihai Caraman 2012-04-16 14:08 ` [PATCH 2/2] KVM: PPC: bookehv: Use lwz/stw instead of PPC_LL/PPC_STL for 32-bit fields Mihai Caraman 2012-04-16 14:08 ` Mihai Caraman 2012-04-26 11:40 ` Alexander Graf 2012-04-26 11:40 ` Alexander Graf 2012-04-26 11:36 ` [PATCH 1/2] KVM: PPC: bookehv: Fix r8/r13 storing in level exception handler Alexander Graf 2012-04-26 11:36 ` Alexander Graf 2012-04-26 17:43 ` Scott Wood 2012-04-26 17:43 ` Scott Wood 2012-05-02 11:12 ` Alexander Graf 2012-05-02 11:12 ` Alexander Graf
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