* [PATCH V2 02/14] MIPS: pci: parse memory ranges from devicetree
2012-05-02 12:27 [PATCH V2 01/14] MIPS: make oprofile use cp0_perfcount_irq if it is set John Crispin
@ 2012-05-02 12:27 ` John Crispin
2012-05-02 18:12 ` Sergei Shtylyov
2012-05-02 12:27 ` [PATCH V2 04/14] MIPS: Add helper function to allow platforms to point at a DTB John Crispin
` (5 subsequent siblings)
6 siblings, 1 reply; 9+ messages in thread
From: John Crispin @ 2012-05-02 12:27 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips@linux-mips.org, John Crispin
Implement pci_load_of_ranges on MIPS. Due to lack of test hardware only 32bit
bus width is supported. This function is based on the implementation found on
powerpc.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
Changes in V2
* remove some #ifdefs
* rename to pci_load_of_ranges
arch/mips/include/asm/pci.h | 6 ++++
arch/mips/pci/pci.c | 55 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index fcd4060..90bf3b3 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -17,6 +17,7 @@
*/
#include <linux/ioport.h>
+#include <linux/of.h>
/*
* Each pci channel is a top-level PCI bus seem by CPU. A machine with
@@ -26,6 +27,7 @@
struct pci_controller {
struct pci_controller *next;
struct pci_bus *bus;
+ struct device_node *of_node;
struct pci_ops *pci_ops;
struct resource *mem_resource;
@@ -142,4 +144,8 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
extern char * (*pcibios_plat_setup)(char *str);
+/* this function parses memory ranges from a device node */
+extern void __devinit pci_load_of_ranges(struct pci_controller *hose,
+ struct device_node *node);
+
#endif /* _ASM_PCI_H */
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 0514866..4d8a1b6 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -16,6 +16,7 @@
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
+#include <linux/of_address.h>
#include <asm/cpu-info.h>
@@ -114,9 +115,63 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
pci_bus_assign_resources(bus);
pci_enable_bridges(bus);
}
+ bus->dev.of_node = hose->of_node;
}
}
+#ifdef CONFIG_OF
+void __devinit pci_load_of_ranges(struct pci_controller *hose,
+ struct device_node *node)
+{
+ const __be32 *ranges;
+ int rlen;
+ int pna = of_n_addr_cells(node);
+ int np = pna + 5;
+
+ pr_info("PCI host bridge %s ranges:\n", node->full_name);
+ ranges = of_get_property(node, "ranges", &rlen);
+ if (ranges == NULL)
+ return;
+ hose->of_node = node;
+
+ while ((rlen -= np * 4) >= 0) {
+ u32 pci_space;
+ struct resource *res = 0;
+ unsigned long long addr, size;
+
+ pci_space = ranges[0];
+ addr = of_translate_address(node, ranges + 3);
+ size = of_read_number(ranges + pna + 3, 2);
+ ranges += np;
+ switch ((pci_space >> 24) & 0x3) {
+ case 1: /* PCI IO space */
+ pr_info(" IO 0x%016llx..0x%016llx\n",
+ addr, addr + size - 1);
+ hose->io_map_base =
+ (unsigned long)ioremap(addr, size);
+ res = hose->io_resource;
+ res->flags = IORESOURCE_IO;
+ break;
+ case 2: /* PCI Memory space */
+ case 3: /* PCI 64 bits Memory space */
+ pr_info(" MEM 0x%016llx..0x%016llx\n",
+ addr, addr + size - 1);
+ res = hose->mem_resource;
+ res->flags = IORESOURCE_MEM;
+ break;
+ }
+ if (res != NULL) {
+ res->start = addr;
+ res->name = node->full_name;
+ res->end = res->start + size - 1;
+ res->parent = NULL;
+ res->sibling = NULL;
+ res->child = NULL;
+ }
+ }
+}
+#endif
+
static DEFINE_MUTEX(pci_scan_mutex);
void __devinit register_pci_controller(struct pci_controller *hose)
--
1.7.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH V2 02/14] MIPS: pci: parse memory ranges from devicetree
2012-05-02 12:27 ` [PATCH V2 02/14] MIPS: pci: parse memory ranges from devicetree John Crispin
@ 2012-05-02 18:12 ` Sergei Shtylyov
0 siblings, 0 replies; 9+ messages in thread
From: Sergei Shtylyov @ 2012-05-02 18:12 UTC (permalink / raw)
To: John Crispin; +Cc: Ralf Baechle, linux-mips@linux-mips.org
Hello.
On 05/02/2012 04:27 PM, John Crispin wrote:
> Implement pci_load_of_ranges on MIPS. Due to lack of test hardware only 32bit
> bus width is supported. This function is based on the implementation found on
> powerpc.
> Signed-off-by: John Crispin<blogic@openwrt.org>
> ---
> Changes in V2
> * remove some #ifdefs
> * rename to pci_load_of_ranges
> arch/mips/include/asm/pci.h | 6 ++++
> arch/mips/pci/pci.c | 55 +++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 61 insertions(+), 0 deletions(-)
[...]
> diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
> index 0514866..4d8a1b6 100644
> --- a/arch/mips/pci/pci.c
> +++ b/arch/mips/pci/pci.c
[...]
> @@ -114,9 +115,63 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
[...]
> +#ifdef CONFIG_OF
> +void __devinit pci_load_of_ranges(struct pci_controller *hose,
> + struct device_node *node)
> +{
> + const __be32 *ranges;
> + int rlen;
> + int pna = of_n_addr_cells(node);
> + int np = pna + 5;
> +
> + pr_info("PCI host bridge %s ranges:\n", node->full_name);
> + ranges = of_get_property(node, "ranges",&rlen);
> + if (ranges == NULL)
> + return;
> + hose->of_node = node;
> +
> + while ((rlen -= np * 4)>= 0) {
> + u32 pci_space;
> + struct resource *res = 0;
s/0/NULL/ to avoid the warning (from sparse?).
WBR, Sergei
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH V2 04/14] MIPS: Add helper function to allow platforms to point at a DTB.
2012-05-02 12:27 [PATCH V2 01/14] MIPS: make oprofile use cp0_perfcount_irq if it is set John Crispin
2012-05-02 12:27 ` [PATCH V2 02/14] MIPS: pci: parse memory ranges from devicetree John Crispin
@ 2012-05-02 12:27 ` John Crispin
2012-05-02 12:27 ` [PATCH V2 05/14] MIPS: parse chosen node on boot John Crispin
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: John Crispin @ 2012-05-02 12:27 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips@linux-mips.org, John Crispin
Add __dt_setup_arch() that can be called to load a builtin DT.
Additionally we add a macro to allow loading a specific symbol
from the __dtb_* section.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
Changes in V2
* remove unused size variable
arch/mips/include/asm/prom.h | 11 +++++++++++
arch/mips/kernel/prom.c | 11 +++++++++++
2 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index 40ed259..7206d44 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -36,6 +36,17 @@ static inline unsigned long pci_address_to_pio(phys_addr_t address)
}
#define pci_address_to_pio pci_address_to_pio
+struct boot_param_header;
+
+extern void __dt_setup_arch(struct boot_param_header *bph);
+
+#define dt_setup_arch(sym) \
+({ \
+ extern struct boot_param_header __dtb_##sym##_begin; \
+ \
+ __dt_setup_arch(&__dtb_##sym##_begin); \
+})
+
#else /* CONFIG_OF */
static inline void device_tree_init(void) { }
#endif /* CONFIG_OF */
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index 558b539..4c788d2 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -95,3 +95,14 @@ void __init device_tree_init(void)
/* free the space reserved for the dt blob */
free_mem_mach(base, size);
}
+
+void __init __dt_setup_arch(struct boot_param_header *bph)
+{
+ if (be32_to_cpu(bph->magic) != OF_DT_HEADER) {
+ pr_err("DTB has bad magic, ignoring builtin OF DTB\n");
+
+ return;
+ }
+
+ initial_boot_params = bph;
+}
--
1.7.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH V2 05/14] MIPS: parse chosen node on boot
2012-05-02 12:27 [PATCH V2 01/14] MIPS: make oprofile use cp0_perfcount_irq if it is set John Crispin
2012-05-02 12:27 ` [PATCH V2 02/14] MIPS: pci: parse memory ranges from devicetree John Crispin
2012-05-02 12:27 ` [PATCH V2 04/14] MIPS: Add helper function to allow platforms to point at a DTB John Crispin
@ 2012-05-02 12:27 ` John Crispin
2012-05-02 12:27 ` [PATCH V2 08/14] MIPS: lantiq: clear all irqs properly " John Crispin
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: John Crispin @ 2012-05-02 12:27 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips@linux-mips.org, John Crispin
Call early_init_devtree from inside __dt_setup_arch to allow parsing of the
chosen node.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
Changes in V2
* rebase on previous patch
arch/mips/kernel/prom.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index 4c788d2..f11b2bb 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -105,4 +105,6 @@ void __init __dt_setup_arch(struct boot_param_header *bph)
}
initial_boot_params = bph;
+
+ early_init_devtree(initial_boot_params);
}
--
1.7.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH V2 08/14] MIPS: lantiq: clear all irqs properly on boot
2012-05-02 12:27 [PATCH V2 01/14] MIPS: make oprofile use cp0_perfcount_irq if it is set John Crispin
` (2 preceding siblings ...)
2012-05-02 12:27 ` [PATCH V2 05/14] MIPS: parse chosen node on boot John Crispin
@ 2012-05-02 12:27 ` John Crispin
2012-05-02 12:27 ` [PATCH V2 09/14] MIPS: lantiq: enable oprofile support on lantiq targets John Crispin
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: John Crispin @ 2012-05-02 12:27 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips@linux-mips.org, John Crispin
Due to missing brackets, the irq modules were not properly reset on boot.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
Changes in V2
* make the commit message accurate
arch/mips/lantiq/irq.c | 11 ++++++-----
1 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index d673731..b6b1c72 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -271,12 +271,13 @@ void __init arch_init_irq(void)
if (!ltq_eiu_membase)
panic("Failed to remap eiu memory");
- /* make sure all irqs are turned off by default */
- for (i = 0; i < 5; i++)
+ /* turn off all irqs by default */
+ for (i = 0; i < 5; i++) {
+ /* make sure all irqs are turned off by default */
ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
-
- /* clear all possibly pending interrupts */
- ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
+ /* clear all possibly pending interrupts */
+ ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
+ }
mips_cpu_irq_init();
--
1.7.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH V2 09/14] MIPS: lantiq: enable oprofile support on lantiq targets
2012-05-02 12:27 [PATCH V2 01/14] MIPS: make oprofile use cp0_perfcount_irq if it is set John Crispin
` (3 preceding siblings ...)
2012-05-02 12:27 ` [PATCH V2 08/14] MIPS: lantiq: clear all irqs properly " John Crispin
@ 2012-05-02 12:27 ` John Crispin
2012-05-02 12:27 ` [PATCH V2 11/14] MIPS: lantiq: fix early printk John Crispin
2012-05-02 12:27 ` [PATCH V2 12/14] MIPS: lantiq: fix cmdline parsing John Crispin
6 siblings, 0 replies; 9+ messages in thread
From: John Crispin @ 2012-05-02 12:27 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips@linux-mips.org, John Crispin
This patch sets the performance counters irq on Lantiq SoCs.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
Changes in V2
* HAVE_OPROFILE was redundant
arch/mips/lantiq/irq.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index b6b1c72..bfd4ad1 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -40,6 +40,9 @@
#define MAX_EIU 6
+/* the performance counter */
+#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
+
/* irqs generated by device attached to the EBU need to be acked in
* a special manner
*/
@@ -316,6 +319,9 @@ void __init arch_init_irq(void)
set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#endif
+
+ /* tell oprofile which irq to use */
+ cp0_perfcount_irq = LTQ_PERF_IRQ;
}
unsigned int __cpuinit get_c0_compare_int(void)
--
1.7.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH V2 11/14] MIPS: lantiq: fix early printk
2012-05-02 12:27 [PATCH V2 01/14] MIPS: make oprofile use cp0_perfcount_irq if it is set John Crispin
` (4 preceding siblings ...)
2012-05-02 12:27 ` [PATCH V2 09/14] MIPS: lantiq: enable oprofile support on lantiq targets John Crispin
@ 2012-05-02 12:27 ` John Crispin
2012-05-02 12:27 ` [PATCH V2 12/14] MIPS: lantiq: fix cmdline parsing John Crispin
6 siblings, 0 replies; 9+ messages in thread
From: John Crispin @ 2012-05-02 12:27 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips@linux-mips.org, Thomas Langer, John Crispin
From: Thomas Langer <thomas.langer@lantiq.com>
The code was using a 32bit write operations in the early_printk code. This
resulted in 3 zero bytes also being written to the serial port. This patch
changes the memory access to 8bit.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
Changes in V2
* set Author to Thomas
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 6 ++++++
arch/mips/lantiq/early_printk.c | 17 ++++++++---------
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 8a3c6be..8bc9030 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -34,6 +34,12 @@
#define LTQ_ASC1_BASE_ADDR 0x1E100C00
#define LTQ_ASC_SIZE 0x400
+/*
+ * during early_printk no ioremap is possible
+ * lets use KSEG1 instead
+ */
+#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
+
/* RCU - reset control unit */
#define LTQ_RCU_BASE_ADDR 0x1F203000
#define LTQ_RCU_SIZE 0x1000
diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c
index 972e05f..9b28d09 100644
--- a/arch/mips/lantiq/early_printk.c
+++ b/arch/mips/lantiq/early_printk.c
@@ -6,17 +6,16 @@
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
-#include <linux/init.h>
#include <linux/cpu.h>
-
-#include <lantiq.h>
#include <lantiq_soc.h>
-/* no ioremap possible at this early stage, lets use KSEG1 instead */
-#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
#define ASC_BUF 1024
-#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048))
-#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020))
+#define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048))
+#ifdef __BIG_ENDIAN
+#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3))
+#else
+#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020))
+#endif
#define TXMASK 0x3F00
#define TXOFFSET 8
@@ -27,7 +26,7 @@ void prom_putchar(char c)
local_irq_save(flags);
do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET);
if (c == '\n')
- ltq_w32('\r', LTQ_ASC_TBUF);
- ltq_w32(c, LTQ_ASC_TBUF);
+ ltq_w8('\r', LTQ_ASC_TBUF);
+ ltq_w8(c, LTQ_ASC_TBUF);
local_irq_restore(flags);
}
--
1.7.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH V2 12/14] MIPS: lantiq: fix cmdline parsing
2012-05-02 12:27 [PATCH V2 01/14] MIPS: make oprofile use cp0_perfcount_irq if it is set John Crispin
` (5 preceding siblings ...)
2012-05-02 12:27 ` [PATCH V2 11/14] MIPS: lantiq: fix early printk John Crispin
@ 2012-05-02 12:27 ` John Crispin
6 siblings, 0 replies; 9+ messages in thread
From: John Crispin @ 2012-05-02 12:27 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips@linux-mips.org, Thomas Langer, John Crispin
From: Thomas Langer <thomas.langer@lantiq.com>
The code tested if the KSEG1 mapped address of argv was != 0. We need to use
CPHYSADDR instead to make the conditional actually work.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
Changes in V2
* set Author to Thomas
arch/mips/lantiq/prom.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 664b7b7..cd56892 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -45,10 +45,12 @@ static void __init prom_init_cmdline(void)
char **argv = (char **) KSEG1ADDR(fw_arg1);
int i;
+ arcs_cmdline[0] = '\0';
+
for (i = 0; i < argc; i++) {
- char *p = (char *) KSEG1ADDR(argv[i]);
+ char *p = (char *) KSEG1ADDR(argv[i]);
- if (p && *p) {
+ if (CPHYSADDR(p) && *p) {
strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
}
--
1.7.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread