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* [PATCH v2,1/5] MIPS: Add support for the 1074K core.
@ 2012-05-10 21:13 Steven J. Hill
  2012-05-12 12:09 ` Sergei Shtylyov
  0 siblings, 1 reply; 3+ messages in thread
From: Steven J. Hill @ 2012-05-10 21:13 UTC (permalink / raw)
  To: linux-mips, ralf; +Cc: Steven J. Hill

From: "Steven J. Hill" <sjhill@mips.com>

This patch adds support for detecting and using 1074K cores.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
---
 arch/mips/include/asm/cpu.h          |    1 +
 arch/mips/kernel/cpu-probe.c         |    4 ++++
 arch/mips/mm/c-r4k.c                 |   24 +++++++++++++++++++++---
 arch/mips/oprofile/op_model_mipsxx.c |    6 ------
 4 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index f9fa2a4..9f8feeb 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -94,6 +94,7 @@
 #define PRID_IMP_24KE		0x9600
 #define PRID_IMP_74K		0x9700
 #define PRID_IMP_1004K		0x9900
+#define PRID_IMP_1074K		0x9a00
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5099201..4b5c7d6 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -835,6 +835,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 		c->cputype = CPU_1004K;
 		__cpu_name[cpu] = "MIPS 1004Kc";
 		break;
+	case PRID_IMP_1074K:
+		c->cputype = CPU_74K;
+		__cpu_name[cpu] = "MIPS 1074Kc";
+		break;
 	}
 
 	spram_config();
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index bda8eb2..c646a79 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void)
 			c->icache.linesz = 2 << lsize;
 		else
 			c->icache.linesz = lsize;
-		c->icache.sets = 64 << ((config1 >> 22) & 7);
+		c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
 		c->icache.ways = 1 + ((config1 >> 16) & 7);
 
 		icache_size = c->icache.sets *
@@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void)
 			c->dcache.linesz = 2 << lsize;
 		else
 			c->dcache.linesz= lsize;
-		c->dcache.sets = 64 << ((config1 >> 13) & 7);
+		c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
 		c->dcache.ways = 1 + ((config1 >> 7) & 7);
 
 		dcache_size = c->dcache.sets *
@@ -1051,9 +1051,26 @@ static void __cpuinit probe_pcache(void)
 	case CPU_R14000:
 		break;
 
+	case CPU_74K:
+		/*
+		 * Early versions of the 74k do not update
+		 * the cache tags on a vtag miss/ptag hit
+		 * which can occur in the case of KSEG0/KUSEG aliases
+		 * In this case it is better to treat the cache as always
+		 * having aliases
+		 */
+		if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
+			c->dcache.flags |= MIPS_CACHE_VTAG;
+		if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
+			write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+		if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
+		   ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
+			c->dcache.flags |= MIPS_CACHE_VTAG;
+			write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+		}
+		/* fall through */
 	case CPU_24K:
 	case CPU_34K:
-	case CPU_74K:
 	case CPU_1004K:
 		if ((read_c0_config7() & (1 << 16))) {
 			/* effectively physically indexed dcache,
@@ -1061,6 +1078,7 @@ static void __cpuinit probe_pcache(void)
 			c->dcache.flags |= MIPS_CACHE_PINDEX;
 			break;
 		}
+		/* fall through */
 	default:
 		if (c->dcache.waysize > PAGE_SIZE)
 			c->dcache.flags |= MIPS_CACHE_ALIASES;
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 54759f1..53bbe55 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -330,12 +330,6 @@ static int __init mipsxx_init(void)
 		break;
 
 	case CPU_1004K:
-#if 0
-		/* FIXME: report as 34K for now */
-		op_model_mipsxx_ops.cpu_type = "mips/1004K";
-		break;
-#endif
-
 	case CPU_34K:
 		op_model_mipsxx_ops.cpu_type = "mips/34K";
 		break;
-- 
1.7.10

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH v2,1/5] MIPS: Add support for the 1074K core.
  2012-05-10 21:13 [PATCH v2,1/5] MIPS: Add support for the 1074K core Steven J. Hill
@ 2012-05-12 12:09 ` Sergei Shtylyov
  2012-05-21 15:38   ` Hill, Steven
  0 siblings, 1 reply; 3+ messages in thread
From: Sergei Shtylyov @ 2012-05-12 12:09 UTC (permalink / raw)
  To: Steven J. Hill; +Cc: linux-mips, ralf

Hello.

On 11-05-2012 1:13, Steven J. Hill wrote:

> From: "Steven J. Hill"<sjhill@mips.com>

> This patch adds support for detecting and using 1074K cores.

> Signed-off-by: Steven J. Hill<sjhill@mips.com>
[...]

> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index bda8eb2..c646a79 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void)
>   			c->icache.linesz = 2<<  lsize;
>   		else
>   			c->icache.linesz = lsize;
> -		c->icache.sets = 64<<  ((config1>>  22)&  7);
> +		c->icache.sets = 32<<  (((config1>>  22) + 1)&  7);
>   		c->icache.ways = 1 + ((config1>>  16)&  7);
>
>   		icache_size = c->icache.sets *
> @@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void)
>   			c->dcache.linesz = 2<<  lsize;
>   		else
>   			c->dcache.linesz= lsize;
> -		c->dcache.sets = 64<<  ((config1>>  13)&  7);
> +		c->dcache.sets = 32<<  (((config1>>  13) + 1)&  7);
>   		c->dcache.ways = 1 + ((config1>>  7)&  7);

    Are these related changes? They seem common, no 1074K specific...

> @@ -1051,9 +1051,26 @@ static void __cpuinit probe_pcache(void)
>   	case CPU_R14000:
>   		break;
>
> +	case CPU_74K:
> +		/*
> +		 * Early versions of the 74k do not update

    Early versions of 74K and 1074K? Shouldn't this be a sperate patch?

> +		 * the cache tags on a vtag miss/ptag hit
> +		 * which can occur in the case of KSEG0/KUSEG aliases
> +		 * In this case it is better to treat the cache as always
> +		 * having aliases
> +		 */
> +		if ((c->processor_id&  0xff)<= PRID_REV_ENCODE_332(2, 4, 0))
> +			c->dcache.flags |= MIPS_CACHE_VTAG;
> +		if ((c->processor_id&  0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> +			write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> +		if (((c->processor_id&  0xff00) == PRID_IMP_1074K)&&
> +		   ((c->processor_id&  0xff)<= PRID_REV_ENCODE_332(1, 1, 0))) {
> +			c->dcache.flags |= MIPS_CACHE_VTAG;
> +			write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> +		}
> +		/* fall through */
>   	case CPU_24K:
>   	case CPU_34K:
> -	case CPU_74K:
>   	case CPU_1004K:
>   		if ((read_c0_config7()&  (1<<  16))) {
>   			/* effectively physically indexed dcache,
> diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
> index 54759f1..53bbe55 100644
> --- a/arch/mips/oprofile/op_model_mipsxx.c
> +++ b/arch/mips/oprofile/op_model_mipsxx.c
> @@ -330,12 +330,6 @@ static int __init mipsxx_init(void)
>   		break;
>
>   	case CPU_1004K:
> -#if 0
> -		/* FIXME: report as 34K for now */
> -		op_model_mipsxx_ops.cpu_type = "mips/1004K";
> -		break;
> -#endif
> -

    Unrelated change.

WBR, Sergei

^ permalink raw reply	[flat|nested] 3+ messages in thread

* RE: [PATCH v2,1/5] MIPS: Add support for the 1074K core.
  2012-05-12 12:09 ` Sergei Shtylyov
@ 2012-05-21 15:38   ` Hill, Steven
  0 siblings, 0 replies; 3+ messages in thread
From: Hill, Steven @ 2012-05-21 15:38 UTC (permalink / raw)
  To: Sergei Shtylyov; +Cc: linux-mips@linux-mips.org

I have cleaned up this patch for 1074K change only. The code that is refactored for 74K is part of the 1074K support. 1074K is a multi-cored 74K and thus the changes are necessary.

-Steve

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2012-05-21 15:38 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2012-05-10 21:13 [PATCH v2,1/5] MIPS: Add support for the 1074K core Steven J. Hill
2012-05-12 12:09 ` Sergei Shtylyov
2012-05-21 15:38   ` Hill, Steven

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