Re: [PATCH 04 of 10] xenalyze: update trace.h to match xen-unstable

[George Dunlap <george.dunlap@eu.citrix.com>]

On 31/05/12 12:16, David Vrabel wrote:
> Update trace.h to the version in xen-unstable (plus my PV_HYPERCALL_*
> patches).
>
> Signed-off-by: David Vrabel<david.vrabel@citrix.com>
Acked-by: George Dunlap <george.dunlap@eu.citrix.com>
> ---
>
> diff --git a/trace.h b/trace.h
> --- a/trace.h
> +++ b/trace.h
> @@ -57,6 +57,7 @@
>   #define TRC_SCHED_CLASS     0x00022000   /* Scheduler-specific    */
>   #define TRC_SCHED_VERBOSE   0x00028000   /* More inclusive scheduling */
>
> +/* Trace classes for Hardware */
>   #define TRC_HW_PM           0x00801000   /* Power management traces */
>   #define TRC_HW_IRQ          0x00802000   /* Traces relating to the handling of IRQs */
>
> @@ -93,20 +94,51 @@
>   #define TRC_MEM_POD_ZERO_RECLAIM    (TRC_MEM + 17)
>   #define TRC_MEM_POD_SUPERPAGE_SPLINTER (TRC_MEM + 18)
>
> +#define TRC_PV_ENTRY   0x00201000 /* Hypervisor entry points for PV guests. */
> +#define TRC_PV_SUBCALL 0x00202000 /* Sub-call in a multicall hypercall */
>
> -#define TRC_PV_HYPERCALL             (TRC_PV +  1)
> -#define TRC_PV_TRAP                  (TRC_PV +  3)
> -#define TRC_PV_PAGE_FAULT            (TRC_PV +  4)
> -#define TRC_PV_FORCED_INVALID_OP     (TRC_PV +  5)
> -#define TRC_PV_EMULATE_PRIVOP        (TRC_PV +  6)
> -#define TRC_PV_EMULATE_4GB           (TRC_PV +  7)
> -#define TRC_PV_MATH_STATE_RESTORE    (TRC_PV +  8)
> -#define TRC_PV_PAGING_FIXUP          (TRC_PV +  9)
> -#define TRC_PV_GDT_LDT_MAPPING_FAULT (TRC_PV + 10)
> -#define TRC_PV_PTWR_EMULATION        (TRC_PV + 11)
> -#define TRC_PV_PTWR_EMULATION_PAE    (TRC_PV + 12)
> -  /* Indicates that addresses in trace record are 64 bits */
> -#define TRC_64_FLAG               (0x100)
> +#define TRC_PV_HYPERCALL             (TRC_PV_ENTRY +  1)
> +#define TRC_PV_TRAP                  (TRC_PV_ENTRY +  3)
> +#define TRC_PV_PAGE_FAULT            (TRC_PV_ENTRY +  4)
> +#define TRC_PV_FORCED_INVALID_OP     (TRC_PV_ENTRY +  5)
> +#define TRC_PV_EMULATE_PRIVOP        (TRC_PV_ENTRY +  6)
> +#define TRC_PV_EMULATE_4GB           (TRC_PV_ENTRY +  7)
> +#define TRC_PV_MATH_STATE_RESTORE    (TRC_PV_ENTRY +  8)
> +#define TRC_PV_PAGING_FIXUP          (TRC_PV_ENTRY +  9)
> +#define TRC_PV_GDT_LDT_MAPPING_FAULT (TRC_PV_ENTRY + 10)
> +#define TRC_PV_PTWR_EMULATION        (TRC_PV_ENTRY + 11)
> +#define TRC_PV_PTWR_EMULATION_PAE    (TRC_PV_ENTRY + 12)
> +#define TRC_PV_HYPERCALL_V2          (TRC_PV_ENTRY + 13)
> +#define TRC_PV_HYPERCALL_SUBCALL     (TRC_PV_SUBCALL + 14)
> +
> +/*
> + * TRC_PV_HYPERCALL_V2 format
> + *
> + * Only some of the hypercall argument are recorded. Bit fields A0 to
> + * A5 in the first extra word are set if the argument is present and
> + * the arguments themselves are packed sequentially in the following
> + * words.
> + *
> + * The TRC_64_FLAG bit is not set for these events (even if there are
> + * 64-bit arguments in the record).
> + *
> + * Word
> + * 0    bit 31 30|29 28|27 26|25 24|23 22|21 20|19 ... 0
> + *          A5   |A4   |A3   |A2   |A1   |A0   |Hypercall op
> + * 1    First 32 bit (or low word of first 64 bit) arg in record
> + * 2    Second 32 bit (or high word of first 64 bit) arg in record
> + * ...
> + *
> + * A0-A5 bitfield values:
> + *
> + *   00b  Argument not present
> + *   01b  32-bit argument present
> + *   10b  64-bit argument present
> + *   11b  Reserved
> + */
> +#define TRC_PV_HYPERCALL_V2_ARG_32(i) (0x1<<  (20 + 2*(i)))
> +#define TRC_PV_HYPERCALL_V2_ARG_64(i) (0x2<<  (20 + 2*(i)))
> +#define TRC_PV_HYPERCALL_V2_ARG_MASK  (0xfff00000)
>
>   #define TRC_SHADOW_NOT_SHADOW                 (TRC_SHADOW +  1)
>   #define TRC_SHADOW_FAST_PROPAGATE             (TRC_SHADOW +  2)
> @@ -125,6 +157,7 @@
>   #define TRC_SHADOW_RESYNC_ONLY                (TRC_SHADOW + 15)
>
>   /* trace events per subclass */
> +#define TRC_HVM_NESTEDFLAG      (0x400)
>   #define TRC_HVM_VMENTRY         (TRC_HVM_ENTRYEXIT + 0x01)
>   #define TRC_HVM_VMEXIT          (TRC_HVM_ENTRYEXIT + 0x02)
>   #define TRC_HVM_VMEXIT64        (TRC_HVM_ENTRYEXIT + TRC_64_FLAG + 0x02)
> @@ -165,6 +198,7 @@
>   #define TRC_HVM_REALMODE_EMULATE (TRC_HVM_HANDLER + 0x22)
>   #define TRC_HVM_TRAP             (TRC_HVM_HANDLER + 0x23)
>   #define TRC_HVM_TRAP_DEBUG       (TRC_HVM_HANDLER + 0x24)
> +#define TRC_HVM_VLAPIC           (TRC_HVM_HANDLER + 0x25)
>
>   #define TRC_HVM_IOPORT_WRITE    (TRC_HVM_HANDLER + 0x216)
>   #define TRC_HVM_IOMEM_WRITE     (TRC_HVM_HANDLER + 0x217)
> @@ -172,8 +206,9 @@
>   /* trace events for per class */
>   #define TRC_PM_FREQ_CHANGE      (TRC_HW_PM + 0x01)
>   #define TRC_PM_IDLE_ENTRY       (TRC_HW_PM + 0x02)
> -#define TRC_PM_IDLE_EXIT        (TRC_HW_PM  + 0x03)
> +#define TRC_PM_IDLE_EXIT        (TRC_HW_PM + 0x03)
>
> +/* Trace events for IRQs */
>   #define TRC_HW_IRQ_MOVE_CLEANUP_DELAY (TRC_HW_IRQ + 0x1)
>   #define TRC_HW_IRQ_MOVE_CLEANUP       (TRC_HW_IRQ + 0x2)
>   #define TRC_HW_IRQ_BIND_VECTOR        (TRC_HW_IRQ + 0x3)
> @@ -182,12 +217,15 @@
>   #define TRC_HW_IRQ_ASSIGN_VECTOR      (TRC_HW_IRQ + 0x6)
>   #define TRC_HW_IRQ_UNMAPPED_VECTOR    (TRC_HW_IRQ + 0x7)
>   #define TRC_HW_IRQ_HANDLED            (TRC_HW_IRQ + 0x8)
> -#define TRC_HW_IRQ_MSI_WRITE          (TRC_HW_IRQ + 0x9)
> -#define TRC_HW_IRQ_MAP_PIRQ_MSI       (TRC_HW_IRQ + 0xa)
> -#define TRC_HW_IRQ_MAP_PIRQ_GSI       (TRC_HW_IRQ + 0xb)
> -#define TRC_HW_IRQ_MSI_SET_AFFINITY   (TRC_HW_IRQ + 0x10)
> -#define TRC_HW_IRQ_SET_DESC_AFFINITY  (TRC_HW_IRQ + 0x11)
> -#define TRC_HW_IRQ_IOMMU_AMD_IRE      (TRC_HW_IRQ + 0x12)
> +
> +/*
> + * Event Flags
> + *
> + * Some events (e.g, TRC_PV_TRAP and TRC_HVM_IOMEM_READ) have multiple
> + * record formats.  These event flags distinguish between the
> + * different formats.
> + */
> +#define TRC_64_FLAG 0x100 /* Addresses are 64 bits (instead of 32 bits) */
>
>   /* This structure represents a single trace buffer record. */
>   struct t_rec {
> @@ -205,6 +243,34 @@ struct t_rec {
>       } u;
>   };
>
> +/*
> + * This structure contains the metadata for a single trace buffer.  The head
> + * field, indexes into an array of struct t_rec's.
> + */
> +struct t_buf {
> +    /* Assume the data buffer size is X.  X is generally not a power of 2.
> +     * CONS and PROD are incremented modulo (2*X):
> +     *     0<= cons<  2*X
> +     *     0<= prod<  2*X
> +     * This is done because addition modulo X breaks at 2^32 when X is not a
> +     * power of 2:
> +     *     (((2^32 - 1) % X) + 1) % X != (2^32) % X
> +     */
> +    uint32_t cons;   /* Offset of next item to be consumed by control tools. */
> +    uint32_t prod;   /* Offset of next item to be produced by Xen.           */
> +    /*  Records follow immediately after the meta-data header.    */
> +};
> +
> +/* Structure used to pass MFNs to the trace buffers back to trace consumers.
> + * Offset is an offset into the mapped structure where the mfn list will be held.
> + * MFNs will be at ((unsigned long *)(t_info))+(t_info->cpu_offset[cpu]).
> + */
> +struct t_info {
> +    uint16_t tbuf_size; /* Size in pages of each trace buffer */
> +    uint16_t mfn_offset[];  /* Offset within t_info structure of the page list per cpu */
> +    /* MFN lists immediately after the header */
> +};
> +
>   #endif /* __XEN_PUBLIC_TRACE_H__ */
>
>   /*