From: rnayak@ti.com (Rajendra Nayak)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] clk: Add support for rate table based dividers
Date: Wed, 27 Jun 2012 16:40:57 +0530 [thread overview]
Message-ID: <4FEAEA41.7070502@ti.com> (raw)
In-Reply-To: <4FEAE89D.3090702@pengutronix.de>
On Wednesday 27 June 2012 04:33 PM, Marc Kleine-Budde wrote:
> On 06/27/2012 01:01 PM, Rajendra Nayak wrote:
>> Some divider clks do not have any obvious relationship
>> between the divider and the value programmed in the
>> register. For instance, say a value of 1 could signify divide
>> by 6 and a value of 2 could signify divide by 4 etc.
>> Also there are dividers where not all values possible
>> based on the bitfield width are valid. For instance
>> a 3 bit wide bitfield can be used to program a value
>> from 0 to 7. However its possible that only 0 to 4
>> are valid values.
>>
>> All these cases need the platform code to pass a simple
>> table of divider/value tuple, so the framework knows
>> the exact value to be written based on the divider
>> calculation and can also do better error checking.
>>
>> This patch adds support for such rate table based
>> dividers.
>>
>> Also since this means adding a new parameter to the
>> clk_register_divider(), update all existing users of
>> it.
>>
>> Signed-off-by: Rajendra Nayak<rnayak@ti.com>
>> Cc: Sascha Hauer<kernel@pengutronix.de>
>> Cc: Viresh Kumar<viresh.linux@gmail.com>
>> ---
>> arch/arm/mach-imx/clk.h | 2 +-
>> drivers/clk/clk-divider.c | 67 ++++++++++++++++++++++++++++++++++--
>> drivers/clk/spear/spear3xx_clock.c | 4 +-
>> drivers/clk/spear/spear6xx_clock.c | 4 +-
>> include/linux/clk-private.h | 3 +-
>> include/linux/clk-provider.h | 10 +++++-
>> 6 files changed, 80 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
>> index 1bf64fe..8cb6f97 100644
>> --- a/arch/arm/mach-imx/clk.h
>> +++ b/arch/arm/mach-imx/clk.h
>> @@ -56,7 +56,7 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
>> void __iomem *reg, u8 shift, u8 width)
>> {
>> return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
>> - reg, shift, width, 0,&imx_ccm_lock);
>> + reg, shift, width, 0, , NULL,&imx_ccm_lock);
> ^^^^^
>
> Is this valid C-Syntax?
Nope, its not. Thanks for catching. Will built test with imx and spear
configs before the next spin.
>
> Marc
>
WARNING: multiple messages have this Message-ID (diff)
From: Rajendra Nayak <rnayak@ti.com>
To: Marc Kleine-Budde <mkl@pengutronix.de>
Cc: mturquette@ti.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Sascha Hauer <kernel@pengutronix.de>,
Viresh Kumar <viresh.linux@gmail.com>
Subject: Re: [PATCH v2] clk: Add support for rate table based dividers
Date: Wed, 27 Jun 2012 16:40:57 +0530 [thread overview]
Message-ID: <4FEAEA41.7070502@ti.com> (raw)
In-Reply-To: <4FEAE89D.3090702@pengutronix.de>
On Wednesday 27 June 2012 04:33 PM, Marc Kleine-Budde wrote:
> On 06/27/2012 01:01 PM, Rajendra Nayak wrote:
>> Some divider clks do not have any obvious relationship
>> between the divider and the value programmed in the
>> register. For instance, say a value of 1 could signify divide
>> by 6 and a value of 2 could signify divide by 4 etc.
>> Also there are dividers where not all values possible
>> based on the bitfield width are valid. For instance
>> a 3 bit wide bitfield can be used to program a value
>> from 0 to 7. However its possible that only 0 to 4
>> are valid values.
>>
>> All these cases need the platform code to pass a simple
>> table of divider/value tuple, so the framework knows
>> the exact value to be written based on the divider
>> calculation and can also do better error checking.
>>
>> This patch adds support for such rate table based
>> dividers.
>>
>> Also since this means adding a new parameter to the
>> clk_register_divider(), update all existing users of
>> it.
>>
>> Signed-off-by: Rajendra Nayak<rnayak@ti.com>
>> Cc: Sascha Hauer<kernel@pengutronix.de>
>> Cc: Viresh Kumar<viresh.linux@gmail.com>
>> ---
>> arch/arm/mach-imx/clk.h | 2 +-
>> drivers/clk/clk-divider.c | 67 ++++++++++++++++++++++++++++++++++--
>> drivers/clk/spear/spear3xx_clock.c | 4 +-
>> drivers/clk/spear/spear6xx_clock.c | 4 +-
>> include/linux/clk-private.h | 3 +-
>> include/linux/clk-provider.h | 10 +++++-
>> 6 files changed, 80 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
>> index 1bf64fe..8cb6f97 100644
>> --- a/arch/arm/mach-imx/clk.h
>> +++ b/arch/arm/mach-imx/clk.h
>> @@ -56,7 +56,7 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
>> void __iomem *reg, u8 shift, u8 width)
>> {
>> return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
>> - reg, shift, width, 0,&imx_ccm_lock);
>> + reg, shift, width, 0, , NULL,&imx_ccm_lock);
> ^^^^^
>
> Is this valid C-Syntax?
Nope, its not. Thanks for catching. Will built test with imx and spear
configs before the next spin.
>
> Marc
>
next prev parent reply other threads:[~2012-06-27 11:10 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-27 11:01 [PATCH v2] clk: Add support for rate table based dividers Rajendra Nayak
2012-06-27 11:01 ` Rajendra Nayak
2012-06-27 11:03 ` Marc Kleine-Budde
2012-06-27 11:03 ` Marc Kleine-Budde
2012-06-27 11:10 ` Rajendra Nayak [this message]
2012-06-27 11:10 ` Rajendra Nayak
2012-06-27 16:28 ` Sascha Hauer
2012-06-27 16:28 ` Sascha Hauer
2012-06-27 18:06 ` Mike Turquette
2012-06-27 18:06 ` Mike Turquette
2012-06-29 6:31 ` Rajendra Nayak
2012-06-29 6:31 ` Rajendra Nayak
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