Re: [PATCH] i2c i.MX: Fix divider table

[Troy Kisky <troy.kisky-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>]

On 7/11/2012 11:38 AM, Sascha Hauer wrote:
> Hi Richard,
>
> On Wed, Jul 11, 2012 at 02:01:21PM +0800, Richard Zhao wrote:
>> IC guys confirmed that the spec is right:
>>
>> This an adaptive feature of our I2C module may apply to all IMX chips.
>> No mistake in the table of RMs.
>>
>> The divider is designed to guarantee SCL high level and low level last
>> time. Divider will hold when SCL transition from 1 to 0 or 0 to 1, if
>> the transition time is longer than 1 internal pre-divided clock cycle.
>> The pre-divided clock is divided from I2C module clock, used for
>> generating SCL. So you will see SCL clock cycle is some way longer than
>> calculated value using IFDR.
>>
>> Transition time will different from rising or falling edge, different
>> pull-up resistors, and different SCL loading.
>>
>> This feature make sure transition time won’t eat both level time of SCL.
> Thanks for clarification. Does this mean that this feature is used to
> synchronize between the bus clock and and bitclock?
>
> I'll send a documentation patch for this next week to make this clear.
>
> Sascha
>
How does this explain why column 2 matched your measurements, but 1, 3, 
and 4 didn't.
And you tested on 2 different boards.
Something doesn't smell right.

Just my 2cents
Troy