Re: [PATCH 2/2] arm64: dts: socfpga: agilex7-gen2: Add initial device tree

["Nazle Asmade, Muhammad Nazim Amirul" <muhammad.nazim.amirul.nazle.asmade@altera.com>]

On 24/6/2026 3:57 pm, Krzysztof Kozlowski wrote:
> On Tue, Jun 23, 2026 at 04:17:16AM -0700, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>> +
>> +	psci {
>> +		compatible = "arm,psci-0.2";
>> +		method = "smc";
>> +	};
>> +
>> +	intc: interrupt-controller@7000000 {
> 
> MMIO goes to MMIO, please read writing bindings and submitting patches docs in DT dir.
> 
> I think this also fails tests (W=1). If that is true, then review should
> finish here, because instead of using machine to find issues you use
> community.
> 
>> +		compatible = "arm,gic-v3";
>> +		reg = <0x0 0x7000000 0x0 0x10000>,
>> +		      <0x0 0x7080000 0x0 0x100000>;
>> +		ranges;
>> +		#interrupt-cells = <3>;
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		interrupt-controller;
>> +		#redistributor-regions = <1>;
>> +		redistributor-stride = <0x0 0x40000>;
>> +
>> +		its: msi-controller@7040000 {
>> +			compatible = "arm,gic-v3-its";
>> +			reg = <0x0 0x7040000 0x0 0x20000>;
>> +			msi-controller;
>> +			#msi-cells = <1>;
>> +		};
>> +	};
>> +
>> +	soc: soc@0 {
>> +		compatible = "simple-bus";
>> +		ranges = <0 0 0 0xffffffff>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		device_type = "soc";
>> +		interrupt-parent = <&intc>;
>> +
>> +		smmu: iommu@c100000 {
>> +			compatible = "arm,smmu-v3";
>> +			reg = <0x0c100000 0x30000>;
>> +			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>;
>> +			interrupt-names = "eventq", "gerror", "priq";
>> +			dma-coherent;
>> +			#iommu-cells = <1>;
>> +		};
>> +
>> +		ocram: sram@0 {
>> +			compatible = "mmio-sram";
>> +			reg = <0x00000000 0x80000>;
>> +			ranges = <0 0 0x80000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
> 
> SoC without any interface, serial or storage or network, is close to
> useless one.
> 
> I don't see a point in having it in mainline. Serial is usually ABSOLUTE
> minimum.
> 
> Best regards,
> Krzysztof
> 
Hi Krzysztof,

Thank you for the review and fast response!

I ran both dt_binding_check and dtbs_check (with CHECK_DTBS=y) locally — 
both passed without errors. Could you clarify which specific test you 
believe is failing?

Regarding "MMIO goes to MMIO" — are you referring to the GIC 
(interrupt-controller@7000000) being placed at the root level instead of 
under the soc bus node?

Regarding the serial console — the platform clock driver is not yet 
upstream, so the UART depends on clkmgr. Would adding the UART with 
clock-frequency be acceptable as an interim solution?

BR,
Nazim