From: Roger Quadros <rogerq@kernel.org>
To: Siddharth Vadapalli <s-vadapalli@ti.com>,
vkoul@kernel.org, kishon@kernel.org, sjakhade@cadence.com,
thomas.richard@bootlin.com, christophe.jaillet@wanadoo.fr,
u.kleine-koenig@baylibre.com, eballetb@redhat.com
Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, srk@ti.com
Subject: Re: [PATCH v3 2/2] phy: cadence-torrent: Add PCIe multilink + USB with same SSC register config for 100 MHz refclk
Date: Thu, 9 Jan 2025 18:37:29 +0200 [thread overview]
Message-ID: <4c6dba11-91c6-4251-9153-6461a4da42e7@kernel.org> (raw)
In-Reply-To: <20250109121614.754466-3-s-vadapalli@ti.com>
On 09/01/2025 14:16, Siddharth Vadapalli wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Add register sequences and support for PCIe multilink + USB configuration
> for 100MHz reference clock. The same SSC is used for both PCIe and USB.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Co-developed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Roger Quadros <rogerq@kernel.org>
To: Siddharth Vadapalli <s-vadapalli@ti.com>,
vkoul@kernel.org, kishon@kernel.org, sjakhade@cadence.com,
thomas.richard@bootlin.com, christophe.jaillet@wanadoo.fr,
u.kleine-koenig@baylibre.com, eballetb@redhat.com
Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, srk@ti.com
Subject: Re: [PATCH v3 2/2] phy: cadence-torrent: Add PCIe multilink + USB with same SSC register config for 100 MHz refclk
Date: Thu, 9 Jan 2025 18:37:29 +0200 [thread overview]
Message-ID: <4c6dba11-91c6-4251-9153-6461a4da42e7@kernel.org> (raw)
In-Reply-To: <20250109121614.754466-3-s-vadapalli@ti.com>
On 09/01/2025 14:16, Siddharth Vadapalli wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Add register sequences and support for PCIe multilink + USB configuration
> for 100MHz reference clock. The same SSC is used for both PCIe and USB.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Co-developed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
--
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next prev parent reply other threads:[~2025-01-09 16:39 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-09 12:16 [PATCH v3 0/2] Enable PCIe Multilink and USB support in Cadence Torrent SERDES driver Siddharth Vadapalli
2025-01-09 12:16 ` Siddharth Vadapalli
2025-01-09 12:16 ` [PATCH v3 1/2] phy: cadence-torrent: Add PCIe multilink configuration for 100 MHz refclk Siddharth Vadapalli
2025-01-09 12:16 ` Siddharth Vadapalli
2025-01-09 16:35 ` Roger Quadros
2025-01-09 16:35 ` Roger Quadros
2025-06-12 8:48 ` Enric Balletbo i Serra
2025-06-12 8:48 ` Enric Balletbo i Serra
2025-06-12 10:04 ` Siddharth Vadapalli
2025-06-12 10:04 ` Siddharth Vadapalli
2025-06-15 14:10 ` Vinod Koul
2025-06-15 14:10 ` Vinod Koul
2025-06-16 6:13 ` Siddharth Vadapalli
2025-06-16 6:13 ` Siddharth Vadapalli
2025-01-09 12:16 ` [PATCH v3 2/2] phy: cadence-torrent: Add PCIe multilink + USB with same SSC register config " Siddharth Vadapalli
2025-01-09 12:16 ` Siddharth Vadapalli
2025-01-09 16:37 ` Roger Quadros [this message]
2025-01-09 16:37 ` Roger Quadros
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