From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: <linux-kernel@vger.kernel.org>, <x86@kernel.org>,
<tglx@linutronix.de>, <mingo@redhat.com>,
<dave.hansen@linux.intel.com>, <chao.gao@intel.com>,
<abusse@amazon.de>
Subject: Re: [PATCH v5 5/7] x86/microcode/intel: Implement staging handler
Date: Wed, 10 Sep 2025 14:31:55 -0700 [thread overview]
Message-ID: <4ed4c815-12ca-48e5-a6fe-a2f2dd367730@intel.com> (raw)
In-Reply-To: <20250910183325.GEaMHEdavbE56NiDUF@fat_crate.local>
[-- Attachment #1: Type: text/plain, Size: 1898 bytes --]
On 9/10/2025 11:33 AM, Borislav Petkov wrote:
> On Sat, Aug 23, 2025 at 08:52:08AM -0700, Chang S. Bae wrote:
>> diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
>> index 3ca22457d839..a1b13202330d 100644
>> --- a/arch/x86/kernel/cpu/microcode/intel.c
>> +++ b/arch/x86/kernel/cpu/microcode/intel.c
>> @@ -20,6 +20,8 @@
>> #include <linux/cpu.h>
>> #include <linux/uio.h>
>> #include <linux/mm.h>
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>
> You do see those are sorted by header name length in a reverse order, right?
Okay, fixed -- and I adjusted patch6 as well:
#include <linux/initrd.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/cpu.h>
#include <linux/uio.h>
>> +/* Defines for the microcode staging mailbox interface */
>> +
>
> ^ Superfluous newline.
Dropped.
>> +/*
>> + * Return PAGE_SIZE, or remaining bytes if this is the final chunk
>> + */
>> +static inline unsigned int calc_next_chunk_size(unsigned int ucode_len, unsigned int offset)
>> +{
>> + return min(PAGE_SIZE, ucode_len - offset);
>> +}
>
> That oneliner looks useless - sticking a comment over tne min() and putting it
> at the single callsite below is good enough.
Agreed -- removed the helper and moved them.
>> +/*
>> + * Update the chunk size and decide whether another chunk can be sent.
>> + * This accounts for remaining data and retry limits.
>> + */
>> +static bool can_send_next_chunk(struct staging_state *ss)
>> +{
>> + ss->chunk_size = calc_next_chunk_size(ss->ucode_len, ss->offset);
>> + /*
>> + * Each microcode image is divided into chunks, each at most
>> + * one page size. A 10-chunk image would typically require 10
> ^^^^
Fixed.
Just to make sure, include the diff here.
Thanks for the careful review and for sticking with this set.
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diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index c7a75afd2b9a..4d663cab4f48 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -12,16 +12,16 @@
*/
#define pr_fmt(fmt) "microcode: " fmt
#include <linux/earlycpio.h>
+#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/uaccess.h>
#include <linux/initrd.h>
+#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/cpu.h>
#include <linux/uio.h>
#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/io.h>
#include <asm/cpu_device_id.h>
#include <asm/processor.h>
@@ -36,7 +36,6 @@ static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin";
#define UCODE_BSP_LOADED ((struct microcode_intel *)0x1UL)
/* Defines for the microcode staging mailbox interface */
-
#define MBOX_REG_NUM 4
#define MBOX_REG_SIZE sizeof(u32)
@@ -344,24 +343,18 @@ static void init_stage(struct staging_state *ss)
writel(MASK_MBOX_CTRL_ABORT, ss->mmio_base + MBOX_CONTROL_OFFSET);
}
-/*
- * Return PAGE_SIZE, or remaining bytes if this is the final chunk
- */
-static inline unsigned int calc_next_chunk_size(unsigned int ucode_len, unsigned int offset)
-{
- return min(PAGE_SIZE, ucode_len - offset);
-}
-
/*
* Update the chunk size and decide whether another chunk can be sent.
* This accounts for remaining data and retry limits.
*/
static bool can_send_next_chunk(struct staging_state *ss, int *err)
{
- ss->chunk_size = calc_next_chunk_size(ss->ucode_len, ss->offset);
+ /* a page size or remaining bytes if this is the final chunk */
+ ss->chunk_size = min(PAGE_SIZE, ss->ucode_len - ss->offset);
+
/*
* Each microcode image is divided into chunks, each at most
- * one page size. A 10-chunk image would typically require 10
+ * one page size. A 10-chunk image would typically require 10
* transactions.
*
* However, the hardware managing the mailbox has limited
next prev parent reply other threads:[~2025-09-10 21:32 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-20 23:40 [PATCH v2 0/6] x86: Support for Intel Microcode Staging Feature Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 1/6] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 2/6] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 3/6] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-03-21 21:18 ` [PATCH v2a " Chang S. Bae
2025-03-26 7:35 ` Chao Gao
2025-03-26 18:43 ` Chang S. Bae
2025-03-27 1:44 ` Chao Gao
2025-03-28 14:12 ` Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 4/6] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-03-21 0:15 ` Dave Hansen
2025-03-21 21:19 ` [PATCH v2a " Chang S. Bae
2025-03-26 8:34 ` Chao Gao
2025-03-26 18:43 ` Chang S. Bae
2025-03-21 21:19 ` [PATCH v2 " Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 5/6] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-03-21 21:19 ` [PATCH v2a " Chang S. Bae
2025-03-27 3:32 ` [PATCH v2 " Chao Gao
2025-03-27 14:11 ` Chang S. Bae
2025-03-31 19:16 ` Dave Hansen
2025-03-20 23:40 ` [PATCH v2 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 0/6] x86: Support for Intel Microcode Staging Feature Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 1/6] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 2/6] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 3/6] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 4/6] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 5/6] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-04-16 14:14 ` Chao Gao
2025-04-16 17:22 ` Chang S. Bae
2025-04-16 17:37 ` Dave Hansen
2025-04-09 23:27 ` [PATCH v3 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 0/6] x86: Support for Intel Microcode Staging Feature Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 1/6] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-08-18 7:45 ` Chao Gao
2025-08-13 17:26 ` [PATCH v4 2/6] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-08-13 18:21 ` Dave Hansen
2025-08-13 20:46 ` Chang S. Bae
2025-08-13 20:55 ` Dave Hansen
2025-08-14 18:30 ` Chang S. Bae
2025-08-22 22:39 ` [PATCH] x86/cpu/topology: Make primary thread mask available with SMP=n Chang S. Bae
2025-08-23 16:05 ` Chang S. Bae
2025-08-22 22:39 ` [PATCH v4a 2/6] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-08-22 23:34 ` Dave Hansen
2025-08-13 17:26 ` [PATCH v4 3/6] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-08-13 18:25 ` Dave Hansen
2025-08-22 22:39 ` [PATCH v4a " Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 4/6] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-08-13 18:44 ` Dave Hansen
2025-08-22 22:39 ` [PATCH v4a " Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 5/6] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-08-13 19:07 ` Dave Hansen
2025-08-22 22:40 ` [PATCH v4a " Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-08-18 8:35 ` Chao Gao
2025-08-22 22:42 ` Chang S. Bae
2025-08-13 19:08 ` [PATCH v4 0/6] x86: Support for Intel Microcode Staging Feature Dave Hansen
2025-08-23 15:52 ` [PATCH v5 0/7] " Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 1/7] x86/cpu/topology: Make primary thread mask available with SMP=n Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 2/7] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-09-04 12:08 ` Borislav Petkov
2025-09-05 0:06 ` Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 3/7] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-09-04 12:13 ` Borislav Petkov
2025-09-05 0:04 ` Chang S. Bae
2025-09-05 11:13 ` Borislav Petkov
2025-09-05 16:31 ` Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 4/7] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-09-04 13:48 ` Borislav Petkov
2025-09-05 0:05 ` Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 5/7] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-09-10 18:33 ` Borislav Petkov
2025-09-10 21:31 ` Chang S. Bae [this message]
2025-08-23 15:52 ` [PATCH v5 6/7] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-09-12 16:34 ` Borislav Petkov
2025-09-13 0:51 ` Chang S. Bae
2025-09-13 19:01 ` Borislav Petkov
2025-08-23 15:52 ` [PATCH v5 7/7] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-08-26 22:13 ` [PATCH v5 0/7] x86: Support for Intel Microcode Staging Feature Luck, Tony
2025-08-26 22:15 ` Chang S. Bae
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