[PATCH v2 0/6] Add initial support for IPQ9574 based boards

[PATCH v2 0/6] Add initial support for IPQ9574 based boards

[Varadarajan Narayanan]

These patches introduce the initial support code needed
for the QTI IPQ9574 SoC and RDP433 board.

	SoC	: Qualcomm IPQ9574
	RAM	: 2GB DDR4
	Flash	: eMMC 8GB
	WiFi	: 1 x 2.4GHz, 1 x 5GHz, 1 x 6GHz

Thanks
Varada

v2: Have tried to address the issues raised in v1
    * Use the upstream kernel dts itself
    * Dropped linker script changes
    * Break up the patches in clock, pinctrl and defconfig subsets
    * Dropped ipq9574 specific files and use existing mach-snapdragon
      infrastructure itself
    * Dropped SMEM related changes. Will have them in a separate
      series
    * Use reset_get_by_index instead of reset_get_by_name

v1: https://lore.kernel.org/u-boot/20240226100807.1095607-1-quic_varada@quicinc.com/
Varadarajan Narayanan (6):
  dts: ipq9574-rdp433-u-boot: add override dtsi
  clk/qcom: add initial clock driver for ipq9574
  pinctrl: qcom: Add ipq9574 pinctrl driver
  mmc: msm_sdhci: Reset clocks before reconfiguration
  qcom_defconfig: enable ipq9574 clock & pinctrl driver
  configs: add ipq9574_defconfig

 arch/arm/dts/ipq9574-rdp433-u-boot.dtsi |  19 ++
 configs/ipq9574_defconfig               | 111 ++++++++++++
 configs/qcom_defconfig                  |   2 +
 drivers/clk/qcom/Kconfig                |   8 +
 drivers/clk/qcom/Makefile               |   1 +
 drivers/clk/qcom/clock-ipq9574.c        | 100 +++++++++++
 drivers/clk/qcom/clock-qcom.h           |   1 +
 drivers/mmc/msm_sdhci.c                 |  10 ++
 drivers/pinctrl/qcom/Kconfig            |   7 +
 drivers/pinctrl/qcom/Makefile           |   1 +
 drivers/pinctrl/qcom/pinctrl-ipq9574.c  | 226 ++++++++++++++++++++++++
 11 files changed, 486 insertions(+)
 create mode 100644 arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
 create mode 100644 configs/ipq9574_defconfig
 create mode 100644 drivers/clk/qcom/clock-ipq9574.c
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c


base-commit: a2b489b170f8382f746202c36616eaf2bc38fe86
-- 
2.34.1

[PATCH v2 1/6] dts: ipq9574-rdp433-u-boot: add override dtsi

[Varadarajan Narayanan]

Add initial support for the IPQ9574 MMC based RDP platforms.
Define memory layout statically.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Use upstream and override DT instead of own DT
---
 arch/arm/dts/ipq9574-rdp433-u-boot.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 arch/arm/dts/ipq9574-rdp433-u-boot.dtsi

diff --git a/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi b/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
new file mode 100644
index 0000000000..71832d350b
--- /dev/null
+++ b/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+	/* Will be removed when bootloader updates later */
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x0 0x40000000>,
+		      <0x0 0x4a500000 0x0 0x00100000>;
+	};
+};
+
+&sdhc_1 {
+	sdhci-caps-mask = <0x0 0x04000000>;
+	sdhci-caps = <0x0 0x04000000>;
+	resets = <&gcc GCC_SDCC_BCR>;
+};
-- 
2.34.1

[PATCH v2 2/6] clk/qcom: add initial clock driver for ipq9574

[Varadarajan Narayanan]

Add initial set of clocks and resets for enabling U-Boot on ipq9574
based RDP platforms.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Combined driver file and makefile/kconfig changes into one patch
---
 drivers/clk/qcom/Kconfig         |   8 +++
 drivers/clk/qcom/Makefile        |   1 +
 drivers/clk/qcom/clock-ipq9574.c | 100 +++++++++++++++++++++++++++++++
 drivers/clk/qcom/clock-qcom.h    |   1 +
 4 files changed, 110 insertions(+)
 create mode 100644 drivers/clk/qcom/clock-ipq9574.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index cb867acc48..3ea01f3c96 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -31,6 +31,14 @@ config CLK_QCOM_IPQ4019
 	  on the Snapdragon IPQ4019 SoC. This driver supports the clocks
 	  and resets exposed by the GCC hardware block.
 
+config CLK_QCOM_IPQ9574
+	bool "Qualcomm IPQ9574 GCC"
+	select CLK_QCOM
+	help
+	  Say Y here to enable support for the Global Clock Controller
+	  on the Snapdragon IPQ9574 SoC. This driver supports the clocks
+	  and resets exposed by the GCC hardware block.
+
 config CLK_QCOM_QCM2290
 	bool "Qualcomm QCM2290 GCC"
 	select CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1bc0f15005..e13fc8c107 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o
 obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
 obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
 obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
+obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
 obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
 obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
 obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
diff --git a/drivers/clk/qcom/clock-ipq9574.c b/drivers/clk/qcom/clock-ipq9574.c
new file mode 100644
index 0000000000..06f2d2dd45
--- /dev/null
+++ b/drivers/clk/qcom/clock-ipq9574.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock drivers for Qualcomm ipq9574
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ */
+
+#include <linux/types.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+
+#include "clock-qcom.h"
+
+#define GCC_BLSP1_AHB_CBCR			0x1004
+#define GCC_BLSP1_UART3_APPS_CMD_RCGR		0x402C
+#define GCC_BLSP1_UART3_APPS_CBCR		0x4054
+
+#define GCC_SDCC1_APPS_CBCR			0x3302C
+#define GCC_SDCC1_AHB_CBCR			0x33034
+#define GCC_SDCC1_APPS_CMD_RCGR			0x33004
+#define GCC_SDCC1_ICE_CORE_CBCR			0x33030
+
+static ulong ipq9574_set_rate(struct clk *clk, ulong rate)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case GCC_BLSP1_UART3_APPS_CLK:
+		clk_rcg_set_rate_mnd(priv->base, GCC_BLSP1_UART3_APPS_CMD_RCGR,
+				     0, 144, 15625, CFG_CLK_SRC_GPLL0, 16);
+		return rate;
+	case GCC_SDCC1_APPS_CLK:
+		clk_rcg_set_rate_mnd(priv->base, GCC_SDCC1_APPS_CMD_RCGR,
+				     11, 0, 0, CFG_CLK_SRC_GPLL2, 16);
+		return rate;
+	default:
+		return -EINVAL;
+	}
+}
+
+static int ipq9574_enable(struct clk *clk)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	//printk("--> %s: %d\n", __func__, clk->id);
+	switch (clk->id) {
+	case GCC_BLSP1_UART3_APPS_CLK:
+		clk_enable_cbc(priv->base + GCC_BLSP1_UART3_APPS_CBCR);
+		break;
+	case GCC_BLSP1_AHB_CLK:
+		clk_enable_cbc(priv->base + GCC_BLSP1_AHB_CBCR);
+		break;
+	case GCC_SDCC1_AHB_CLK:
+		clk_enable_cbc(priv->base + GCC_SDCC1_AHB_CBCR);
+		break;
+	case GCC_SDCC1_APPS_CLK:
+		clk_enable_cbc(priv->base + GCC_SDCC1_APPS_CBCR);
+		break;
+	case GCC_SDCC1_ICE_CORE_CLK:
+		clk_enable_cbc(priv->base + GCC_SDCC1_ICE_CORE_CBCR);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct qcom_reset_map ipq9574_gcc_resets[] = {
+	[GCC_SDCC_BCR] = { 0x33000 },
+};
+
+static struct msm_clk_data ipq9574_gcc_data = {
+	.resets = ipq9574_gcc_resets,
+	.num_resets = ARRAY_SIZE(ipq9574_gcc_resets),
+	.enable = ipq9574_enable,
+	.set_rate = ipq9574_set_rate,
+};
+
+static const struct udevice_id gcc_ipq9574_of_match[] = {
+	{
+		.compatible = "qcom,ipq9574-gcc",
+		.data = (ulong)&ipq9574_gcc_data,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(gcc_ipq9574) = {
+	.name		= "gcc_ipq9574",
+	.id		= UCLASS_NOP,
+	.of_match	= gcc_ipq9574_of_match,
+	.bind		= qcom_cc_bind,
+	.flags		= DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index ff336dea39..e038dc421e 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -11,6 +11,7 @@
 #define CFG_CLK_SRC_CXO   (0 << 8)
 #define CFG_CLK_SRC_GPLL0 (1 << 8)
 #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
+#define CFG_CLK_SRC_GPLL2 (2 << 8)
 #define CFG_CLK_SRC_GPLL9 (2 << 8)
 #define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
 #define CFG_CLK_SRC_GPLL6 (4 << 8)
-- 
2.34.1

[PATCH v2 3/6] pinctrl: qcom: Add ipq9574 pinctrl driver

[Varadarajan Narayanan]

Add pinctrl driver for the TLMM block found in the ipq9574 SoC.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 drivers/pinctrl/qcom/Kconfig           |   7 +
 drivers/pinctrl/qcom/Makefile          |   1 +
 drivers/pinctrl/qcom/pinctrl-ipq9574.c | 226 +++++++++++++++++++++++++
 3 files changed, 234 insertions(+)
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index d3eb699855..26ef59b938 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -27,6 +27,13 @@ config PINCTRL_QCOM_IPQ4019
 	  Say Y here to enable support for pinctrl on the IPQ4019 SoC,
 	  as well as the associated GPIO driver.
 
+config PINCTRL_QCOM_IPQ9574
+	bool "Qualcomm IPQ9574 Pinctrl"
+	select PINCTRL_QCOM
+	help
+	  Say Y here to enable support for pinctrl on the IPQ9574 SoC,
+	  as well as the associated GPIO driver.
+
 config PINCTRL_QCOM_QCM2290
 	bool "Qualcomm QCM2290 GCC"
 	select PINCTRL_QCOM
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 06d3c95f93..0253687fab 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o
 obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o
 obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
+obj-$(CONFIG_PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o
 obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
 obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
 obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
new file mode 100644
index 0000000000..5d3d23374d
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock drivers for Qualcomm ipq9574
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+enum ipq9574_functions {
+	msm_mux_blsp0_spi,
+	msm_mux_blsp0_uart,
+	msm_mux_blsp1_i2c,
+	msm_mux_blsp1_spi,
+	msm_mux_blsp1_uart,
+	msm_mux_blsp2_i2c,
+	msm_mux_blsp2_spi,
+	msm_mux_blsp2_uart,
+	msm_mux_blsp3_i2c,
+	msm_mux_blsp3_spi,
+	msm_mux_blsp3_uart,
+	msm_mux_blsp4_i2c,
+	msm_mux_blsp4_spi,
+	msm_mux_blsp4_uart,
+	msm_mux_blsp5_i2c,
+	msm_mux_blsp5_uart,
+	msm_mux_gpio,
+	msm_mux_mdc,
+	msm_mux_mdio,
+	msm_mux_pcie0_clk,
+	msm_mux_pcie0_wake,
+	msm_mux_pcie1_clk,
+	msm_mux_pcie1_wake,
+	msm_mux_pcie2_clk,
+	msm_mux_pcie2_wake,
+	msm_mux_pcie3_clk,
+	msm_mux_pcie3_wake,
+	msm_mux_qspi_data,
+	msm_mux_qspi_clk,
+	msm_mux_qspi_cs,
+	msm_mux_sdc_data,
+	msm_mux_sdc_clk,
+	msm_mux_sdc_cmd,
+	msm_mux_sdc_rclk,
+	msm_mux_NA,
+};
+
+#define MSM_PIN_FUNCTION(fname)				\
+	[msm_mux_##fname] = {#fname, msm_mux_##fname}
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	MSM_PIN_FUNCTION(blsp0_spi),
+	MSM_PIN_FUNCTION(blsp0_uart),
+	MSM_PIN_FUNCTION(blsp1_i2c),
+	MSM_PIN_FUNCTION(blsp1_spi),
+	MSM_PIN_FUNCTION(blsp1_uart),
+	MSM_PIN_FUNCTION(blsp2_i2c),
+	MSM_PIN_FUNCTION(blsp2_spi),
+	MSM_PIN_FUNCTION(blsp2_uart),
+	MSM_PIN_FUNCTION(blsp3_i2c),
+	MSM_PIN_FUNCTION(blsp3_spi),
+	MSM_PIN_FUNCTION(blsp3_uart),
+	MSM_PIN_FUNCTION(blsp4_i2c),
+	MSM_PIN_FUNCTION(blsp4_spi),
+	MSM_PIN_FUNCTION(blsp4_uart),
+	MSM_PIN_FUNCTION(blsp5_i2c),
+	MSM_PIN_FUNCTION(blsp5_uart),
+	MSM_PIN_FUNCTION(gpio),
+	MSM_PIN_FUNCTION(mdc),
+	MSM_PIN_FUNCTION(mdio),
+	MSM_PIN_FUNCTION(pcie0_clk),
+	MSM_PIN_FUNCTION(pcie0_wake),
+	MSM_PIN_FUNCTION(pcie1_clk),
+	MSM_PIN_FUNCTION(pcie1_wake),
+	MSM_PIN_FUNCTION(pcie2_clk),
+	MSM_PIN_FUNCTION(pcie2_wake),
+	MSM_PIN_FUNCTION(pcie3_clk),
+	MSM_PIN_FUNCTION(pcie3_wake),
+	MSM_PIN_FUNCTION(qspi_data),
+	MSM_PIN_FUNCTION(qspi_clk),
+	MSM_PIN_FUNCTION(qspi_cs),
+	MSM_PIN_FUNCTION(sdc_data),
+	MSM_PIN_FUNCTION(sdc_clk),
+	MSM_PIN_FUNCTION(sdc_cmd),
+	MSM_PIN_FUNCTION(sdc_rclk),
+};
+
+typedef unsigned int msm_pin_function[10];
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+	[id] = {        msm_mux_gpio, /* gpio mode */	\
+			msm_mux_##f1,			\
+			msm_mux_##f2,			\
+			msm_mux_##f3,			\
+			msm_mux_##f4,			\
+			msm_mux_##f5,			\
+			msm_mux_##f6,			\
+			msm_mux_##f7,			\
+			msm_mux_##f8,			\
+			msm_mux_##f9,			\
+	}
+
+static const msm_pin_function ipq9574_pin_functions[] = {
+	PINGROUP(0, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(1, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(2, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(3, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(4, sdc_cmd, qspi_cs, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(5, sdc_clk, qspi_clk, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(6, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(7, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(8, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(9, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(10, sdc_rclk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(11, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(12, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(13, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(14, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
+	PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
+	PINGROUP(17, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(18, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(19, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(20, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(21, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(22, pcie0_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(24, pcie0_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(25, pcie1_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(27, pcie1_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(28, pcie2_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(30, pcie2_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(31, pcie3_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(33, pcie3_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
+	PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
+	PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(38, mdc, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(39, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(47, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(48, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(49, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(52, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(53, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(54, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(55, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(56, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(57, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(58, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(61, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(62, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(63, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(64, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+};
+
+static const char *ipq9574_get_function_name(struct udevice *dev,
+					     unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *ipq9574_get_pin_name(struct udevice *dev,
+					unsigned int selector)
+{
+	snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+	return pin_name;
+}
+
+static unsigned int ipq9574_get_function_mux(unsigned int pin,
+					     unsigned int selector)
+{
+	unsigned int i;
+	const msm_pin_function *func = ipq9574_pin_functions + pin;
+
+	for (i = 0; i < 10; i++)
+		if ((*func)[i] == selector)
+			return i;
+
+	pr_err("Can't find requested function for pin %u pin\n", pin);
+	return -EINVAL;
+}
+
+static const struct msm_pinctrl_data ipq9574_data = {
+	.pin_data = {
+		.pin_count = 65,
+		.special_pins_start = 65, /* There are no special pins */
+	},
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = ipq9574_get_function_name,
+	.get_function_mux = ipq9574_get_function_mux,
+	.get_pin_name = ipq9574_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{ .compatible = "qcom,ipq9574-tlmm", .data = (ulong)&ipq9574_data },
+	{ /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_ipq9574) = {
+	.name		= "pinctrl_ipq9574",
+	.id		= UCLASS_NOP,
+	.of_match	= msm_pinctrl_ids,
+	.ops		= &msm_pinctrl_ops,
+	.bind		= msm_pinctrl_bind,
+	.flags = DM_FLAG_PRE_RELOC,
+};
-- 
2.34.1

[PATCH v2 4/6] mmc: msm_sdhci: Reset clocks before reconfiguration

[Varadarajan Narayanan]

U-Boot has to reconfigure the clocks that were set in the boot
loaders. However, in IPQ9574, the clocks have to be reset before
they can be reconfigured. Hence add code to do the relevant
resets.

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 drivers/mmc/msm_sdhci.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 27bb7052fc..ac77fb06bf 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -10,6 +10,7 @@
 #include <clk.h>
 #include <dm.h>
 #include <malloc.h>
+#include <reset.h>
 #include <sdhci.h>
 #include <wait_bit.h>
 #include <asm/global_data.h>
@@ -153,9 +154,18 @@ static int msm_sdc_probe(struct udevice *dev)
 	const struct msm_sdhc_variant_info *var_info;
 	struct sdhci_host *host = &prv->host;
 	u32 core_version, core_minor, core_major;
+	struct reset_ctl bcr_rst;
 	u32 caps;
 	int ret;
 
+	ret = reset_get_by_index(dev, 0, &bcr_rst);
+	if (!ret) {
+		reset_assert(&bcr_rst);
+		udelay(200);
+		reset_deassert(&bcr_rst);
+		udelay(200);
+	}
+
 	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
 
 	host->max_clk = 0;
-- 
2.34.1

[PATCH v2 5/6] qcom_defconfig: enable ipq9574 clock & pinctrl driver

[Varadarajan Narayanan]

Enable the IPQ9574 clock & pinctrl driver in the Qualcomm defconfig.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 configs/qcom_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index e4abfdf16b..865381f75d 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -47,6 +47,7 @@ CONFIG_BUTTON_QCOM_PMIC=y
 CONFIG_CLK=y
 CONFIG_CLK_QCOM_APQ8016=y
 CONFIG_CLK_QCOM_APQ8096=y
+CONFIG_CLK_QCOM_IPQ9574=y
 CONFIG_CLK_QCOM_QCM2290=y
 CONFIG_CLK_QCOM_QCS404=y
 CONFIG_CLK_QCOM_SA8775P=y
@@ -94,6 +95,7 @@ CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_QCOM_APQ8016=y
 CONFIG_PINCTRL_QCOM_APQ8096=y
+CONFIG_PINCTRL_QCOM_IPQ9574=y
 CONFIG_PINCTRL_QCOM_QCM2290=y
 CONFIG_PINCTRL_QCOM_QCS404=y
 CONFIG_PINCTRL_QCOM_SDM845=y
-- 
2.34.1

[PATCH v2 6/6] configs: add ipq9574_mmc_defconfig

[Varadarajan Narayanan]

Introduce a defconfig for the Qualcomm IPQ9574 SoC based RDPs.
Presently supports eMMC.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 configs/ipq9574_mmc_defconfig | 111 ++++++++++++++++++++++++++++++++++
 1 file changed, 111 insertions(+)
 create mode 100644 configs/ipq9574_mmc_defconfig

diff --git a/configs/ipq9574_mmc_defconfig b/configs/ipq9574_mmc_defconfig
new file mode 100644
index 0000000000..62201d7948
--- /dev/null
+++ b/configs/ipq9574_mmc_defconfig
@@ -0,0 +1,111 @@
+#include "qcom_defconfig"
+
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_BASE=0x78b1000
+CONFIG_DEBUG_UART_MSM=y
+CONFIG_DEBUG_UART_CLOCK=1843200
+# Address where U-Boot will be loaded
+CONFIG_TEXT_BASE=0x4A240000
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_DEFAULT_DEVICE_TREE="qcom/ipq9574-rdp433"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTDELAY=2
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1024
+CONFIG_OF_LIVE=y
+CONFIG_MSM_GPIO=y
+CONFIG_CLK_QCOM_IPQ9574=y
+CONFIG_PINCTRL_QCOM_IPQ9574=y
+CONFIG_MSM_SERIAL=y
+CONFIG_DM_EVENT=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0
+CONFIG_PARTITIONS=y
+CONFIG_PARTITION_UUIDS=y
+CONFIG_MTD=y
+CONFIG_MTD_PARTS=y
+
+#
+# Turning off many options so that u-boot size is less
+# than 756KB.
+#
+# CONFIG_BOOTP_PXE is not set
+# CONFIG_BUTTON_KEYBOARD is not set
+# CONFIG_CLK_QCOM_APQ8016 is not set
+# CONFIG_CLK_QCOM_APQ8096 is not set
+# CONFIG_CLK_QCOM_QCM2290 is not set
+# CONFIG_CLK_QCOM_QCS404 is not set
+# CONFIG_CLK_QCOM_SC7280 is not set
+# CONFIG_CLK_QCOM_SDM845 is not set
+# CONFIG_CLK_QCOM_SM6115 is not set
+# CONFIG_CLK_QCOM_SM8150 is not set
+# CONFIG_CLK_QCOM_SM8250 is not set
+# CONFIG_CLK_QCOM_SM8550 is not set
+# CONFIG_CLK_QCOM_SM8650 is not set
+# CONFIG_CMD_BOOTP is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_I2C is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_PING is not set
+# CONFIG_CMD_PINMUX is not set
+# CONFIG_CMD_PXE is not set
+# CONFIG_CMD_RNG is not set
+# CONFIG_CMD_TFTPBOOT is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DM_ETH is not set
+# CONFIG_DM_I2C is not set
+# CONFIG_DM_KEYBOARD is not set
+# CONFIG_DM_MDIO is not set
+# CONFIG_DM_PMIC is not set
+# CONFIG_DM_REGULATOR_COMMON is not set
+# CONFIG_DM_REGULATOR_FIXED is not set
+# CONFIG_DM_REGULATOR is not set
+# CONFIG_DM_REGULATOR_QCOM_RPMH is not set
+# CONFIG_DM_USB is not set
+# CONFIG_ETH is not set
+# CONFIG_FS_EXT4 is not set
+# CONFIG_FS_FAT is not set
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+# CONFIG_IOMMU is not set
+# CONFIG_LEGACY_CRYPTO_BASIC is not set
+# CONFIG_LEGACY_CRYPTO_CERT is not set
+# CONFIG_LEGACY_CRYPTO is not set
+# CONFIG_LIB_RAND is not set
+# CONFIG_MD5_LEGACY is not set
+# CONFIG_MISC is not set
+# CONFIG_MMC_HS200_SUPPORT is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_NVMEM is not set
+# CONFIG_PHY_GIGE is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_PINCTRL_QCOM_APQ8016 is not set
+# CONFIG_PINCTRL_QCOM_APQ8096 is not set
+# CONFIG_PINCTRL_QCOM_IPQ4019 is not set
+# CONFIG_PINCTRL_QCOM_QCM2290 is not set
+# CONFIG_PINCTRL_QCOM_QCS404 is not set
+# CONFIG_PINCTRL_QCOM_SDM845 is not set
+# CONFIG_PINCTRL_QCOM_SM6115 is not set
+# CONFIG_PINCTRL_QCOM_SM8150 is not set
+# CONFIG_PINCTRL_QCOM_SM8250 is not set
+# CONFIG_PINCTRL_QCOM_SM8550 is not set
+# CONFIG_PINCTRL_QCOM_SM8650 is not set
+# CONFIG_PMIC_CHILDREN is not set
+# CONFIG_PMIC_QCOM is not set
+# CONFIG_POWER_DOMAIN is not set
+# CONFIG_PXE_UTILS is not set
+# CONFIG_QCOM_HYP_SMMU is not set
+# CONFIG_REGEX is not set
+# CONFIG_RGMII is not set
+# CONFIG_SHA1_LEGACY is not set
+# CONFIG_SHA256_LEGACY is not set
+# CONFIG_UFS is not set
+# CONFIG_USB is not set
+# CONFIG_VIDEO is not set
-- 
2.34.1

Re: [PATCH v2 1/6] dts: ipq9574-rdp433-u-boot: add override dtsi

[Caleb Connolly]

Hi Varadarajan,

Sorry for the not getting to this sooner!

On 1/30/25 05:37, Varadarajan Narayanan wrote:
> Add initial support for the IPQ9574 MMC based RDP platforms.
> Define memory layout statically.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v2: Use upstream and override DT instead of own DT
> ---
>   arch/arm/dts/ipq9574-rdp433-u-boot.dtsi | 19 +++++++++++++++++++
>   1 file changed, 19 insertions(+)
>   create mode 100644 arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
> 
> diff --git a/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi b/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
> new file mode 100644
> index 0000000000..71832d350b
> --- /dev/null
> +++ b/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/ {
> +	/* Will be removed when bootloader updates later */

Could you elaborate a little here? Are you referring to when SMEM 
parsing is supported in U-Boot? Or some change in a prior boot stage?
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x40000000 0x0 0x40000000>,
> +		      <0x0 0x4a500000 0x0 0x00100000>;
> +	};
> +};
> +
> +&sdhc_1 {
> +	sdhci-caps-mask = <0x0 0x04000000>;
> +	sdhci-caps = <0x0 0x04000000>;
Please annotate this

> +	resets = <&gcc GCC_SDCC_BCR>;

A comment here explaining why this isn't in the upstream DT would also 
be good.

Kind regards,
> +};

-- 
Caleb (they/them)

Re: [PATCH v2 2/6] clk/qcom: add initial clock driver for ipq9574

[Caleb Connolly]

On 1/30/25 05:37, Varadarajan Narayanan wrote:
> Add initial set of clocks and resets for enabling U-Boot on ipq9574
> based RDP platforms.

What is RDP?
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v2: Combined driver file and makefile/kconfig changes into one patch
> ---
>   drivers/clk/qcom/Kconfig         |   8 +++
>   drivers/clk/qcom/Makefile        |   1 +
>   drivers/clk/qcom/clock-ipq9574.c | 100 +++++++++++++++++++++++++++++++
>   drivers/clk/qcom/clock-qcom.h    |   1 +
>   4 files changed, 110 insertions(+)
>   create mode 100644 drivers/clk/qcom/clock-ipq9574.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index cb867acc48..3ea01f3c96 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -31,6 +31,14 @@ config CLK_QCOM_IPQ4019
>   	  on the Snapdragon IPQ4019 SoC. This driver supports the clocks
>   	  and resets exposed by the GCC hardware block.
>   
> +config CLK_QCOM_IPQ9574
> +	bool "Qualcomm IPQ9574 GCC"
> +	select CLK_QCOM
> +	help
> +	  Say Y here to enable support for the Global Clock Controller
> +	  on the Snapdragon IPQ9574 SoC. This driver supports the clocks
> +	  and resets exposed by the GCC hardware block.
> +
>   config CLK_QCOM_QCM2290
>   	bool "Qualcomm QCM2290 GCC"
>   	select CLK_QCOM
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 1bc0f15005..e13fc8c107 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o
>   obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
>   obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
>   obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
> +obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
>   obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
>   obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
>   obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
> diff --git a/drivers/clk/qcom/clock-ipq9574.c b/drivers/clk/qcom/clock-ipq9574.c
> new file mode 100644
> index 0000000000..06f2d2dd45
> --- /dev/null
> +++ b/drivers/clk/qcom/clock-ipq9574.c
> @@ -0,0 +1,100 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Clock drivers for Qualcomm ipq9574
> + *
> + * (C) Copyright 2024 Linaro Ltd.
> + */
> +
> +#include <linux/types.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <linux/delay.h>
> +#include <asm/io.h>
> +#include <linux/bug.h>
> +#include <linux/bitops.h>
> +#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> +#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> +
> +#include "clock-qcom.h"
> +
> +#define GCC_BLSP1_AHB_CBCR			0x1004
> +#define GCC_BLSP1_UART3_APPS_CMD_RCGR		0x402C
> +#define GCC_BLSP1_UART3_APPS_CBCR		0x4054
> +
> +#define GCC_SDCC1_APPS_CBCR			0x3302C
> +#define GCC_SDCC1_AHB_CBCR			0x33034
> +#define GCC_SDCC1_APPS_CMD_RCGR			0x33004
> +#define GCC_SDCC1_ICE_CORE_CBCR			0x33030
> +
> +static ulong ipq9574_set_rate(struct clk *clk, ulong rate)
> +{
> +	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> +	switch (clk->id) {
> +	case GCC_BLSP1_UART3_APPS_CLK:
> +		clk_rcg_set_rate_mnd(priv->base, GCC_BLSP1_UART3_APPS_CMD_RCGR,
> +				     0, 144, 15625, CFG_CLK_SRC_GPLL0, 16);
> +		return rate;
> +	case GCC_SDCC1_APPS_CLK:
> +		clk_rcg_set_rate_mnd(priv->base, GCC_SDCC1_APPS_CMD_RCGR,
> +				     11, 0, 0, CFG_CLK_SRC_GPLL2, 16);
> +		return rate;
> +	default:
> +		return -EINVAL;
> +	}
> +}
> +
> +static int ipq9574_enable(struct clk *clk)
> +{
> +	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> +	//printk("--> %s: %d\n", __func__, clk->id);

Remove or demote to debug, with gate_clk you can include the clock name 
as well.
> +	switch (clk->id) {
> +	case GCC_BLSP1_UART3_APPS_CLK:
> +		clk_enable_cbc(priv->base + GCC_BLSP1_UART3_APPS_CBCR);
> +		break;
> +	case GCC_BLSP1_AHB_CLK:
> +		clk_enable_cbc(priv->base + GCC_BLSP1_AHB_CBCR);
> +		break;
> +	case GCC_SDCC1_AHB_CLK:
> +		clk_enable_cbc(priv->base + GCC_SDCC1_AHB_CBCR);
> +		break;
> +	case GCC_SDCC1_APPS_CLK:
> +		clk_enable_cbc(priv->base + GCC_SDCC1_APPS_CBCR);
> +		break;
> +	case GCC_SDCC1_ICE_CORE_CLK:
> +		clk_enable_cbc(priv->base + GCC_SDCC1_ICE_CORE_CBCR);
> +		break;
> +	default:
> +		return -EINVAL;
> +	}

Please use the gate_clk API for these, refer to clock-sdm845.c for 
reference.

With that:

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>

Kind regards,
> +
> +	return 0;
> +}
> +
> +static const struct qcom_reset_map ipq9574_gcc_resets[] = {
> +	[GCC_SDCC_BCR] = { 0x33000 },
> +};
> +
> +static struct msm_clk_data ipq9574_gcc_data = {
> +	.resets = ipq9574_gcc_resets,
> +	.num_resets = ARRAY_SIZE(ipq9574_gcc_resets),
> +	.enable = ipq9574_enable,
> +	.set_rate = ipq9574_set_rate,
> +};
> +
> +static const struct udevice_id gcc_ipq9574_of_match[] = {
> +	{
> +		.compatible = "qcom,ipq9574-gcc",
> +		.data = (ulong)&ipq9574_gcc_data,
> +	},
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(gcc_ipq9574) = {
> +	.name		= "gcc_ipq9574",
> +	.id		= UCLASS_NOP,
> +	.of_match	= gcc_ipq9574_of_match,
> +	.bind		= qcom_cc_bind,
> +	.flags		= DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
> +};
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index ff336dea39..e038dc421e 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -11,6 +11,7 @@
>   #define CFG_CLK_SRC_CXO   (0 << 8)
>   #define CFG_CLK_SRC_GPLL0 (1 << 8)
>   #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
> +#define CFG_CLK_SRC_GPLL2 (2 << 8)
>   #define CFG_CLK_SRC_GPLL9 (2 << 8)
>   #define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
>   #define CFG_CLK_SRC_GPLL6 (4 << 8)

-- 
Caleb (they/them)

Re: [PATCH v2 3/6] pinctrl: qcom: Add ipq9574 pinctrl driver

[Caleb Connolly]

On 1/30/25 05:37, Varadarajan Narayanan wrote:
> Add pinctrl driver for the TLMM block found in the ipq9574 SoC.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
>   drivers/pinctrl/qcom/Kconfig           |   7 +
>   drivers/pinctrl/qcom/Makefile          |   1 +
>   drivers/pinctrl/qcom/pinctrl-ipq9574.c | 226 +++++++++++++++++++++++++
>   3 files changed, 234 insertions(+)
>   create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c
> 
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index d3eb699855..26ef59b938 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -27,6 +27,13 @@ config PINCTRL_QCOM_IPQ4019
>   	  Say Y here to enable support for pinctrl on the IPQ4019 SoC,
>   	  as well as the associated GPIO driver.
>   
> +config PINCTRL_QCOM_IPQ9574
> +	bool "Qualcomm IPQ9574 Pinctrl"
> +	select PINCTRL_QCOM
> +	help
> +	  Say Y here to enable support for pinctrl on the IPQ9574 SoC,
> +	  as well as the associated GPIO driver.
> +
>   config PINCTRL_QCOM_QCM2290
>   	bool "Qualcomm QCM2290 GCC"
>   	select PINCTRL_QCOM
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 06d3c95f93..0253687fab 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -5,6 +5,7 @@
>   obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o
>   obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o
>   obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
> +obj-$(CONFIG_PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o
>   obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
>   obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
>   obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
> new file mode 100644
> index 0000000000..5d3d23374d
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
> @@ -0,0 +1,226 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Clock drivers for Qualcomm ipq9574

pinctrl driver
> + *
> + * (C) Copyright 2024 Linaro Ltd.
> + */
> +
> +#include <dm.h>
> +
> +#include "pinctrl-qcom.h"
> +
> +#define MAX_PIN_NAME_LEN 32
> +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
> +
> +enum ipq9574_functions {
> +	msm_mux_blsp0_spi,
> +	msm_mux_blsp0_uart,
> +	msm_mux_blsp1_i2c,
> +	msm_mux_blsp1_spi,
> +	msm_mux_blsp1_uart,
> +	msm_mux_blsp2_i2c,
> +	msm_mux_blsp2_spi,
> +	msm_mux_blsp2_uart,
> +	msm_mux_blsp3_i2c,
> +	msm_mux_blsp3_spi,
> +	msm_mux_blsp3_uart,
> +	msm_mux_blsp4_i2c,
> +	msm_mux_blsp4_spi,
> +	msm_mux_blsp4_uart,
> +	msm_mux_blsp5_i2c,
> +	msm_mux_blsp5_uart,
> +	msm_mux_gpio,
> +	msm_mux_mdc,
> +	msm_mux_mdio,
> +	msm_mux_pcie0_clk,
> +	msm_mux_pcie0_wake,
> +	msm_mux_pcie1_clk,
> +	msm_mux_pcie1_wake,
> +	msm_mux_pcie2_clk,
> +	msm_mux_pcie2_wake,
> +	msm_mux_pcie3_clk,
> +	msm_mux_pcie3_wake,
> +	msm_mux_qspi_data,
> +	msm_mux_qspi_clk,
> +	msm_mux_qspi_cs,
> +	msm_mux_sdc_data,
> +	msm_mux_sdc_clk,
> +	msm_mux_sdc_cmd,
> +	msm_mux_sdc_rclk,
> +	msm_mux_NA,
> +};
> +
> +#define MSM_PIN_FUNCTION(fname)				\
> +	[msm_mux_##fname] = {#fname, msm_mux_##fname}
> +
> +static const struct pinctrl_function msm_pinctrl_functions[] = {
> +	MSM_PIN_FUNCTION(blsp0_spi),
> +	MSM_PIN_FUNCTION(blsp0_uart),
> +	MSM_PIN_FUNCTION(blsp1_i2c),
> +	MSM_PIN_FUNCTION(blsp1_spi),
> +	MSM_PIN_FUNCTION(blsp1_uart),
> +	MSM_PIN_FUNCTION(blsp2_i2c),
> +	MSM_PIN_FUNCTION(blsp2_spi),
> +	MSM_PIN_FUNCTION(blsp2_uart),
> +	MSM_PIN_FUNCTION(blsp3_i2c),
> +	MSM_PIN_FUNCTION(blsp3_spi),
> +	MSM_PIN_FUNCTION(blsp3_uart),
> +	MSM_PIN_FUNCTION(blsp4_i2c),
> +	MSM_PIN_FUNCTION(blsp4_spi),
> +	MSM_PIN_FUNCTION(blsp4_uart),
> +	MSM_PIN_FUNCTION(blsp5_i2c),
> +	MSM_PIN_FUNCTION(blsp5_uart),
> +	MSM_PIN_FUNCTION(gpio),
> +	MSM_PIN_FUNCTION(mdc),
> +	MSM_PIN_FUNCTION(mdio),
> +	MSM_PIN_FUNCTION(pcie0_clk),
> +	MSM_PIN_FUNCTION(pcie0_wake),
> +	MSM_PIN_FUNCTION(pcie1_clk),
> +	MSM_PIN_FUNCTION(pcie1_wake),
> +	MSM_PIN_FUNCTION(pcie2_clk),
> +	MSM_PIN_FUNCTION(pcie2_wake),
> +	MSM_PIN_FUNCTION(pcie3_clk),
> +	MSM_PIN_FUNCTION(pcie3_wake),
> +	MSM_PIN_FUNCTION(qspi_data),
> +	MSM_PIN_FUNCTION(qspi_clk),
> +	MSM_PIN_FUNCTION(qspi_cs),
> +	MSM_PIN_FUNCTION(sdc_data),
> +	MSM_PIN_FUNCTION(sdc_clk),
> +	MSM_PIN_FUNCTION(sdc_cmd),
> +	MSM_PIN_FUNCTION(sdc_rclk),
> +};
> +
> +typedef unsigned int msm_pin_function[10];
> +
> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
> +	[id] = {        msm_mux_gpio, /* gpio mode */	\
> +			msm_mux_##f1,			\
> +			msm_mux_##f2,			\
> +			msm_mux_##f3,			\
> +			msm_mux_##f4,			\
> +			msm_mux_##f5,			\
> +			msm_mux_##f6,			\
> +			msm_mux_##f7,			\
> +			msm_mux_##f8,			\
> +			msm_mux_##f9,			\
> +	}
> +
> +static const msm_pin_function ipq9574_pin_functions[] = {
> +	PINGROUP(0, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(1, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(2, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(3, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(4, sdc_cmd, qspi_cs, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(5, sdc_clk, qspi_clk, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(6, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(7, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(8, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(9, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(10, sdc_rclk, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(11, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(12, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(13, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(14, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(17, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(18, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(19, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(20, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(21, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(22, pcie0_clk, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(24, pcie0_wake, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(25, pcie1_clk, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(27, pcie1_wake, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(28, pcie2_clk, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(30, pcie2_wake, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(31, pcie3_clk, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(33, pcie3_wake, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
> +	PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
> +	PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(38, mdc, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(39, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(47, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(48, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(49, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(52, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(53, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(54, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(55, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(56, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(57, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(58, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(61, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(62, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(63, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(64, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
> +};
> +
> +static const char *ipq9574_get_function_name(struct udevice *dev,
> +					     unsigned int selector)
> +{
> +	return msm_pinctrl_functions[selector].name;
> +}
> +
> +static const char *ipq9574_get_pin_name(struct udevice *dev,
> +					unsigned int selector)
> +{
> +	snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
> +	return pin_name;
> +}
> +
> +static unsigned int ipq9574_get_function_mux(unsigned int pin,
> +					     unsigned int selector)
> +{
> +	unsigned int i;
> +	const msm_pin_function *func = ipq9574_pin_functions + pin;
> +
> +	for (i = 0; i < 10; i++)
> +		if ((*func)[i] == selector)
> +			return i;
> +
> +	pr_err("Can't find requested function for pin %u pin\n", pin);

Please demote to debug() and include the selector, or drop this entirely.
> +	return -EINVAL;

This function is currently assumed to never fail (so I guess on other 
platforms if you try to mux a pin to a function it doesn't support it 
would just be programmed wrong). Maybe you could fix this codepath to 
the error is actually bubbled up? Since this will just program (-EINVAL) 
<< 2 into your pin which is probably undesirable.
> +}
> +
> +static const struct msm_pinctrl_data ipq9574_data = {
> +	.pin_data = {
> +		.pin_count = 65,
> +		.special_pins_start = 65, /* There are no special pins */

No need to specify them then, please drop this.

Kind regards,
> +	},
> +	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
> +	.get_function_name = ipq9574_get_function_name,
> +	.get_function_mux = ipq9574_get_function_mux,
> +	.get_pin_name = ipq9574_get_pin_name,
> +};
> +
> +static const struct udevice_id msm_pinctrl_ids[] = {
> +	{ .compatible = "qcom,ipq9574-tlmm", .data = (ulong)&ipq9574_data },
> +	{ /* Sentinal */ }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_ipq9574) = {
> +	.name		= "pinctrl_ipq9574",
> +	.id		= UCLASS_NOP,
> +	.of_match	= msm_pinctrl_ids,
> +	.ops		= &msm_pinctrl_ops,
> +	.bind		= msm_pinctrl_bind,
> +	.flags = DM_FLAG_PRE_RELOC,
> +};

-- 
Caleb (they/them)

Re: [PATCH v2 5/6] qcom_defconfig: enable ipq9574 clock & pinctrl driver

[Caleb Connolly]

On 1/30/25 05:37, Varadarajan Narayanan wrote:
> Enable the IPQ9574 clock & pinctrl driver in the Qualcomm defconfig.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>   configs/qcom_defconfig | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
> index e4abfdf16b..865381f75d 100644
> --- a/configs/qcom_defconfig
> +++ b/configs/qcom_defconfig
> @@ -47,6 +47,7 @@ CONFIG_BUTTON_QCOM_PMIC=y
>   CONFIG_CLK=y
>   CONFIG_CLK_QCOM_APQ8016=y
>   CONFIG_CLK_QCOM_APQ8096=y
> +CONFIG_CLK_QCOM_IPQ9574=y
>   CONFIG_CLK_QCOM_QCM2290=y
>   CONFIG_CLK_QCOM_QCS404=y
>   CONFIG_CLK_QCOM_SA8775P=y
> @@ -94,6 +95,7 @@ CONFIG_PINCTRL=y
>   CONFIG_PINCONF=y
>   CONFIG_PINCTRL_QCOM_APQ8016=y
>   CONFIG_PINCTRL_QCOM_APQ8096=y
> +CONFIG_PINCTRL_QCOM_IPQ9574=y
>   CONFIG_PINCTRL_QCOM_QCM2290=y
>   CONFIG_PINCTRL_QCOM_QCS404=y
>   CONFIG_PINCTRL_QCOM_SDM845=y

-- 
Caleb (they/them)

Re: [PATCH v2 6/6] configs: add ipq9574_mmc_defconfig

[Caleb Connolly]

Hi Varadarajan,

On 1/30/25 05:37, Varadarajan Narayanan wrote:
> Introduce a defconfig for the Qualcomm IPQ9574 SoC based RDPs.
> Presently supports eMMC.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
>   configs/ipq9574_mmc_defconfig | 111 ++++++++++++++++++++++++++++++++++
>   1 file changed, 111 insertions(+)
>   create mode 100644 configs/ipq9574_mmc_defconfig
> 
> diff --git a/configs/ipq9574_mmc_defconfig b/configs/ipq9574_mmc_defconfig

Please name this qcom_ipq9574_mmc_defconfig

> new file mode 100644
> index 0000000000..62201d7948
> --- /dev/null
> +++ b/configs/ipq9574_mmc_defconfig
> @@ -0,0 +1,111 @@
> +#include "qcom_defconfig"
> +
> +CONFIG_DEBUG_UART=y
> +CONFIG_DEBUG_UART_ANNOUNCE=y
> +CONFIG_DEBUG_UART_BASE=0x78b1000
> +CONFIG_DEBUG_UART_MSM=y
> +CONFIG_DEBUG_UART_CLOCK=1843200
> +# Address where U-Boot will be loaded

This comment is redundant, please remove it.

With that

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>

Kind regards,
> +CONFIG_TEXT_BASE=0x4A240000
> +CONFIG_REMAKE_ELF=y
> +CONFIG_SYS_LOAD_ADDR=0x50000000
> +CONFIG_DEFAULT_DEVICE_TREE="qcom/ipq9574-rdp433"
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_BOOTSTD_FULL=y
> +CONFIG_BOOTDELAY=2
> +CONFIG_OF_BOARD_SETUP=y
> +CONFIG_SYS_CBSIZE=1024
> +CONFIG_SYS_PBSIZE=1024
> +CONFIG_OF_LIVE=y
> +CONFIG_MSM_GPIO=y
> +CONFIG_CLK_QCOM_IPQ9574=y
> +CONFIG_PINCTRL_QCOM_IPQ9574=y
> +CONFIG_MSM_SERIAL=y
> +CONFIG_DM_EVENT=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_ENV_SIZE=0x40000
> +CONFIG_ENV_OFFSET=0
> +CONFIG_PARTITIONS=y
> +CONFIG_PARTITION_UUIDS=y
> +CONFIG_MTD=y
> +CONFIG_MTD_PARTS=y
> +
> +#
> +# Turning off many options so that u-boot size is less
> +# than 756KB.
> +#
> +# CONFIG_BOOTP_PXE is not set
> +# CONFIG_BUTTON_KEYBOARD is not set
> +# CONFIG_CLK_QCOM_APQ8016 is not set
> +# CONFIG_CLK_QCOM_APQ8096 is not set
> +# CONFIG_CLK_QCOM_QCM2290 is not set
> +# CONFIG_CLK_QCOM_QCS404 is not set
> +# CONFIG_CLK_QCOM_SC7280 is not set
> +# CONFIG_CLK_QCOM_SDM845 is not set
> +# CONFIG_CLK_QCOM_SM6115 is not set
> +# CONFIG_CLK_QCOM_SM8150 is not set
> +# CONFIG_CLK_QCOM_SM8250 is not set
> +# CONFIG_CLK_QCOM_SM8550 is not set
> +# CONFIG_CLK_QCOM_SM8650 is not set
> +# CONFIG_CMD_BOOTP is not set
> +# CONFIG_CMD_GPIO is not set
> +# CONFIG_CMD_I2C is not set
> +# CONFIG_CMD_MII is not set
> +# CONFIG_CMD_NET is not set
> +# CONFIG_CMD_PING is not set
> +# CONFIG_CMD_PINMUX is not set
> +# CONFIG_CMD_PXE is not set
> +# CONFIG_CMD_RNG is not set
> +# CONFIG_CMD_TFTPBOOT is not set
> +# CONFIG_DISPLAY_CPUINFO is not set
> +# CONFIG_DM_ETH is not set
> +# CONFIG_DM_I2C is not set
> +# CONFIG_DM_KEYBOARD is not set
> +# CONFIG_DM_MDIO is not set
> +# CONFIG_DM_PMIC is not set
> +# CONFIG_DM_REGULATOR_COMMON is not set
> +# CONFIG_DM_REGULATOR_FIXED is not set
> +# CONFIG_DM_REGULATOR is not set
> +# CONFIG_DM_REGULATOR_QCOM_RPMH is not set
> +# CONFIG_DM_USB is not set
> +# CONFIG_ETH is not set
> +# CONFIG_FS_EXT4 is not set
> +# CONFIG_FS_FAT is not set
> +# CONFIG_I2C is not set
> +# CONFIG_INPUT is not set
> +# CONFIG_IOMMU is not set
> +# CONFIG_LEGACY_CRYPTO_BASIC is not set
> +# CONFIG_LEGACY_CRYPTO_CERT is not set
> +# CONFIG_LEGACY_CRYPTO is not set
> +# CONFIG_LIB_RAND is not set
> +# CONFIG_MD5_LEGACY is not set
> +# CONFIG_MISC is not set
> +# CONFIG_MMC_HS200_SUPPORT is not set
> +# CONFIG_NETDEVICES is not set
> +# CONFIG_NVMEM is not set
> +# CONFIG_PHY_GIGE is not set
> +# CONFIG_PHYLIB is not set
> +# CONFIG_PINCTRL_QCOM_APQ8016 is not set
> +# CONFIG_PINCTRL_QCOM_APQ8096 is not set
> +# CONFIG_PINCTRL_QCOM_IPQ4019 is not set
> +# CONFIG_PINCTRL_QCOM_QCM2290 is not set
> +# CONFIG_PINCTRL_QCOM_QCS404 is not set
> +# CONFIG_PINCTRL_QCOM_SDM845 is not set
> +# CONFIG_PINCTRL_QCOM_SM6115 is not set
> +# CONFIG_PINCTRL_QCOM_SM8150 is not set
> +# CONFIG_PINCTRL_QCOM_SM8250 is not set
> +# CONFIG_PINCTRL_QCOM_SM8550 is not set
> +# CONFIG_PINCTRL_QCOM_SM8650 is not set
> +# CONFIG_PMIC_CHILDREN is not set
> +# CONFIG_PMIC_QCOM is not set
> +# CONFIG_POWER_DOMAIN is not set
> +# CONFIG_PXE_UTILS is not set
> +# CONFIG_QCOM_HYP_SMMU is not set
> +# CONFIG_REGEX is not set
> +# CONFIG_RGMII is not set
> +# CONFIG_SHA1_LEGACY is not set
> +# CONFIG_SHA256_LEGACY is not set
> +# CONFIG_UFS is not set
> +# CONFIG_USB is not set
> +# CONFIG_VIDEO is not set

-- 
Caleb (they/them)

Re: [PATCH v2 0/6] Add initial support for IPQ9574 based boards

[Caleb Connolly]

Hi Varadarajan,

On 1/30/25 05:37, Varadarajan Narayanan wrote:
> These patches introduce the initial support code needed
> for the QTI IPQ9574 SoC and RDP433 board.
> 
> 	SoC	: Qualcomm IPQ9574
> 	RAM	: 2GB DDR4
> 	Flash	: eMMC 8GB
> 	WiFi	: 1 x 2.4GHz, 1 x 5GHz, 1 x 6GHz

Thanks for respinning these, this is a lot more palatable :P

Everything looks pretty good, just a few minor changes. However the lack 
of documentation worries me a little.

I'd appreciate it if you could add a document in the next revision 
describing how to build and flash U-Boot for these platforms. You can 
look at doc/board/qualcomm/rb3gen2.rst for reference.

That document should also briefly explain what the platform is, what 
variants exist, what RDP stands for, etc.

Robert: do you have anything to add here?

Kind regards,
> 
> Thanks
> Varada
> 
> v2: Have tried to address the issues raised in v1
>      * Use the upstream kernel dts itself
>      * Dropped linker script changes
>      * Break up the patches in clock, pinctrl and defconfig subsets
>      * Dropped ipq9574 specific files and use existing mach-snapdragon
>        infrastructure itself
>      * Dropped SMEM related changes. Will have them in a separate
>        series
>      * Use reset_get_by_index instead of reset_get_by_name
> 
> v1: https://lore.kernel.org/u-boot/20240226100807.1095607-1-quic_varada@quicinc.com/
> Varadarajan Narayanan (6):
>    dts: ipq9574-rdp433-u-boot: add override dtsi
>    clk/qcom: add initial clock driver for ipq9574
>    pinctrl: qcom: Add ipq9574 pinctrl driver
>    mmc: msm_sdhci: Reset clocks before reconfiguration
>    qcom_defconfig: enable ipq9574 clock & pinctrl driver
>    configs: add ipq9574_defconfig
> 
>   arch/arm/dts/ipq9574-rdp433-u-boot.dtsi |  19 ++
>   configs/ipq9574_defconfig               | 111 ++++++++++++
>   configs/qcom_defconfig                  |   2 +
>   drivers/clk/qcom/Kconfig                |   8 +
>   drivers/clk/qcom/Makefile               |   1 +
>   drivers/clk/qcom/clock-ipq9574.c        | 100 +++++++++++
>   drivers/clk/qcom/clock-qcom.h           |   1 +
>   drivers/mmc/msm_sdhci.c                 |  10 ++
>   drivers/pinctrl/qcom/Kconfig            |   7 +
>   drivers/pinctrl/qcom/Makefile           |   1 +
>   drivers/pinctrl/qcom/pinctrl-ipq9574.c  | 226 ++++++++++++++++++++++++
>   11 files changed, 486 insertions(+)
>   create mode 100644 arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
>   create mode 100644 configs/ipq9574_defconfig
>   create mode 100644 drivers/clk/qcom/clock-ipq9574.c
>   create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c
> 
> 
> base-commit: a2b489b170f8382f746202c36616eaf2bc38fe86

-- 
Caleb (they/them)

Re: [PATCH v2 0/6] Add initial support for IPQ9574 based boards

[Caleb Connolly]

On Thu, 30 Jan 2025 11:07:45 +0530, Varadarajan Narayanan wrote:
> These patches introduce the initial support code needed
> for the QTI IPQ9574 SoC and RDP433 board.
> 
> 	SoC	: Qualcomm IPQ9574
> 	RAM	: 2GB DDR4
> 	Flash	: eMMC 8GB
> 	WiFi	: 1 x 2.4GHz, 1 x 5GHz, 1 x 6GHz
> 
> [...]

Applied, thanks!

[1/6] dts: ipq9574-rdp433-u-boot: add override dtsi
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/25edbbf7fde8
[2/6] clk/qcom: add initial clock driver for ipq9574
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/ad3e8a2f59e7
[3/6] pinctrl: qcom: Add ipq9574 pinctrl driver
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/1b734e019048
[4/6] mmc: msm_sdhci: Reset clocks before reconfiguration
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/5bff42afd1c0
[5/6] qcom_defconfig: enable ipq9574 clock & pinctrl driver
      (no commit info)
[6/6] configs: add ipq9574_mmc_defconfig
      (no commit info)

Best regards,
-- 
Caleb Connolly <caleb.connolly@linaro.org>