* [PATCH] ARM: tegra: fix U16 divider range check
@ 2012-07-24 22:50 ` Stephen Warren
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Warren @ 2012-07-24 22:50 UTC (permalink / raw)
To: Olof Johansson, Colin Cross
Cc: Prashant Gaikwad,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
A U16 divider can divide a clock by 1..64K. However, the range-check
in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's
downstream kernels already have the fixed range-check.
In practice this is a problem on Whistler's I2C bus, which uses a bus
clock rate of 100KHz (rather than the more common 400KHz on Tegra boards),
which requires a HW module clock of 8*100KHz. The parent clock is 216MHz,
leading to a desired divider of 270. Prior to conversion to the common
clock framework, this range error was somehow ignored/irrelevant and
caused no problems. However, the common clock framework evidently has
more rigorous error-checking, so this failure causes the I2C bus to fail
to operate correctly.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/mach-tegra/tegra2_clocks.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index a703844..83ccb85 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -223,7 +223,7 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
if (divider_u16 - 1 < 0)
return 0;
- if (divider_u16 - 1 > 255)
+ if (divider_u16 - 1 > 0xFFFF)
return -EINVAL;
return divider_u16 - 1;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] ARM: tegra: fix U16 divider range check
@ 2012-07-24 22:50 ` Stephen Warren
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Warren @ 2012-07-24 22:50 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
A U16 divider can divide a clock by 1..64K. However, the range-check
in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's
downstream kernels already have the fixed range-check.
In practice this is a problem on Whistler's I2C bus, which uses a bus
clock rate of 100KHz (rather than the more common 400KHz on Tegra boards),
which requires a HW module clock of 8*100KHz. The parent clock is 216MHz,
leading to a desired divider of 270. Prior to conversion to the common
clock framework, this range error was somehow ignored/irrelevant and
caused no problems. However, the common clock framework evidently has
more rigorous error-checking, so this failure causes the I2C bus to fail
to operate correctly.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/mach-tegra/tegra2_clocks.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index a703844..83ccb85 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -223,7 +223,7 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
if (divider_u16 - 1 < 0)
return 0;
- if (divider_u16 - 1 > 255)
+ if (divider_u16 - 1 > 0xFFFF)
return -EINVAL;
return divider_u16 - 1;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
[parent not found: <1343170214-28262-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]
* Re: [PATCH] ARM: tegra: fix U16 divider range check
2012-07-24 22:50 ` Stephen Warren
@ 2012-07-25 6:42 ` Prashant Gaikwad
-1 siblings, 0 replies; 6+ messages in thread
From: Prashant Gaikwad @ 2012-07-25 6:42 UTC (permalink / raw)
To: Stephen Warren
Cc: Olof Johansson, Colin Cross,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Stephen Warren
On Wednesday 25 July 2012 04:20 AM, Stephen Warren wrote:
> From: Stephen Warren<swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> A U16 divider can divide a clock by 1..64K. However, the range-check
> in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's
> downstream kernels already have the fixed range-check.
>
> In practice this is a problem on Whistler's I2C bus, which uses a bus
> clock rate of 100KHz (rather than the more common 400KHz on Tegra boards),
> which requires a HW module clock of 8*100KHz. The parent clock is 216MHz,
> leading to a desired divider of 270. Prior to conversion to the common
> clock framework, this range error was somehow ignored/irrelevant and
> caused no problems. However, the common clock framework evidently has
> more rigorous error-checking, so this failure causes the I2C bus to fail
> to operate correctly.
>
> Signed-off-by: Stephen Warren<swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Thanks Stephen!!
Verified on Cardhu and Ventana with common clock framework patches.
> ---
> arch/arm/mach-tegra/tegra2_clocks.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
> index a703844..83ccb85 100644
> --- a/arch/arm/mach-tegra/tegra2_clocks.c
> +++ b/arch/arm/mach-tegra/tegra2_clocks.c
> @@ -223,7 +223,7 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
> if (divider_u16 - 1< 0)
> return 0;
>
> - if (divider_u16 - 1> 255)
> + if (divider_u16 - 1> 0xFFFF)
> return -EINVAL;
>
> return divider_u16 - 1;
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] ARM: tegra: fix U16 divider range check
@ 2012-07-25 6:42 ` Prashant Gaikwad
0 siblings, 0 replies; 6+ messages in thread
From: Prashant Gaikwad @ 2012-07-25 6:42 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 25 July 2012 04:20 AM, Stephen Warren wrote:
> From: Stephen Warren<swarren@nvidia.com>
>
> A U16 divider can divide a clock by 1..64K. However, the range-check
> in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's
> downstream kernels already have the fixed range-check.
>
> In practice this is a problem on Whistler's I2C bus, which uses a bus
> clock rate of 100KHz (rather than the more common 400KHz on Tegra boards),
> which requires a HW module clock of 8*100KHz. The parent clock is 216MHz,
> leading to a desired divider of 270. Prior to conversion to the common
> clock framework, this range error was somehow ignored/irrelevant and
> caused no problems. However, the common clock framework evidently has
> more rigorous error-checking, so this failure causes the I2C bus to fail
> to operate correctly.
>
> Signed-off-by: Stephen Warren<swarren@nvidia.com>
Thanks Stephen!!
Verified on Cardhu and Ventana with common clock framework patches.
> ---
> arch/arm/mach-tegra/tegra2_clocks.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
> index a703844..83ccb85 100644
> --- a/arch/arm/mach-tegra/tegra2_clocks.c
> +++ b/arch/arm/mach-tegra/tegra2_clocks.c
> @@ -223,7 +223,7 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
> if (divider_u16 - 1< 0)
> return 0;
>
> - if (divider_u16 - 1> 255)
> + if (divider_u16 - 1> 0xFFFF)
> return -EINVAL;
>
> return divider_u16 - 1;
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] ARM: tegra: fix U16 divider range check
2012-07-24 22:50 ` Stephen Warren
@ 2012-08-03 18:01 ` Stephen Warren
-1 siblings, 0 replies; 6+ messages in thread
From: Stephen Warren @ 2012-08-03 18:01 UTC (permalink / raw)
To: Olof Johansson, Colin Cross
Cc: Prashant Gaikwad,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren
On 07/24/2012 04:50 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> A U16 divider can divide a clock by 1..64K. However, the range-check
> in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's
> downstream kernels already have the fixed range-check.
>
> In practice this is a problem on Whistler's I2C bus, which uses a bus
> clock rate of 100KHz (rather than the more common 400KHz on Tegra boards),
> which requires a HW module clock of 8*100KHz. The parent clock is 216MHz,
> leading to a desired divider of 270. Prior to conversion to the common
> clock framework, this range error was somehow ignored/irrelevant and
> caused no problems. However, the common clock framework evidently has
> more rigorous error-checking, so this failure causes the I2C bus to fail
> to operate correctly.
Applied to for-3.7/common-clk.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] ARM: tegra: fix U16 divider range check
@ 2012-08-03 18:01 ` Stephen Warren
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Warren @ 2012-08-03 18:01 UTC (permalink / raw)
To: linux-arm-kernel
On 07/24/2012 04:50 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> A U16 divider can divide a clock by 1..64K. However, the range-check
> in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's
> downstream kernels already have the fixed range-check.
>
> In practice this is a problem on Whistler's I2C bus, which uses a bus
> clock rate of 100KHz (rather than the more common 400KHz on Tegra boards),
> which requires a HW module clock of 8*100KHz. The parent clock is 216MHz,
> leading to a desired divider of 270. Prior to conversion to the common
> clock framework, this range error was somehow ignored/irrelevant and
> caused no problems. However, the common clock framework evidently has
> more rigorous error-checking, so this failure causes the I2C bus to fail
> to operate correctly.
Applied to for-3.7/common-clk.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-08-03 18:01 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2012-07-24 22:50 [PATCH] ARM: tegra: fix U16 divider range check Stephen Warren
2012-07-24 22:50 ` Stephen Warren
[not found] ` <1343170214-28262-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-07-25 6:42 ` Prashant Gaikwad
2012-07-25 6:42 ` Prashant Gaikwad
2012-08-03 18:01 ` Stephen Warren
2012-08-03 18:01 ` Stephen Warren
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