* [PATCH v2 1/7] RTC: add DT bindings to pxa-rtc
2012-07-26 19:16 [PATCH v2 0/7] Assorted PXA3xx DT patches Daniel Mack
@ 2012-07-26 19:16 ` Daniel Mack
2012-07-26 19:16 ` [PATCH v2 2/7] MMC: pxa-mci: add DT bindings Daniel Mack
` (5 subsequent siblings)
6 siblings, 0 replies; 25+ messages in thread
From: Daniel Mack @ 2012-07-26 19:16 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds generic device tree bindings to the PXA RTC driver.
Documentation for bindings were also added.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Alessandro Zummo <a.zummo@towertech.it>
---
Documentation/devicetree/bindings/rtc/pxa-rtc.txt | 14 ++++++++++++++
drivers/rtc/rtc-pxa.c | 11 +++++++++++
2 files changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/pxa-rtc.txt
diff --git a/Documentation/devicetree/bindings/rtc/pxa-rtc.txt b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt
new file mode 100644
index 0000000..8c6672a
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt
@@ -0,0 +1,14 @@
+* PXA RTC
+
+PXA specific RTC driver.
+
+Required properties:
+- compatible : Should be "marvell,pxa-rtc"
+
+Examples:
+
+rtc at 40900000 {
+ compatible = "marvell,pxa-rtc";
+ reg = <0x40900000 0x3c>;
+ interrupts = <30 31>;
+};
diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
index 0075c8f..f771b2e 100644
--- a/drivers/rtc/rtc-pxa.c
+++ b/drivers/rtc/rtc-pxa.c
@@ -27,6 +27,8 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
#include <mach/hardware.h>
@@ -396,6 +398,14 @@ static int __exit pxa_rtc_remove(struct platform_device *pdev)
return 0;
}
+#ifdef CONFIG_OF
+static struct of_device_id pxa_rtc_dt_ids[] = {
+ { .compatible = "marvell,pxa-rtc" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
+#endif
+
#ifdef CONFIG_PM
static int pxa_rtc_suspend(struct device *dev)
{
@@ -425,6 +435,7 @@ static struct platform_driver pxa_rtc_driver = {
.remove = __exit_p(pxa_rtc_remove),
.driver = {
.name = "pxa-rtc",
+ .of_match_table = of_match_ptr(pxa_rtc_dt_ids),
#ifdef CONFIG_PM
.pm = &pxa_rtc_pm_ops,
#endif
--
1.7.11.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v2 2/7] MMC: pxa-mci: add DT bindings
2012-07-26 19:16 [PATCH v2 0/7] Assorted PXA3xx DT patches Daniel Mack
2012-07-26 19:16 ` [PATCH v2 1/7] RTC: add DT bindings to pxa-rtc Daniel Mack
@ 2012-07-26 19:16 ` Daniel Mack
2012-07-26 19:16 ` [PATCH v2 3/7] MTD: pxa3xx-nand: add devicetree bindings Daniel Mack
` (4 subsequent siblings)
6 siblings, 0 replies; 25+ messages in thread
From: Daniel Mack @ 2012-07-26 19:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Daniel Mack <zonque@gmail.com>
Cc: Nicolas Pitre <nico@fluxnic.net>
Cc: Chris Ball <cjb@laptop.org>
---
Documentation/devicetree/bindings/mmc/pxa-mmc.txt | 25 +++++++++++
drivers/mmc/host/pxamci.c | 52 +++++++++++++++++++++++
2 files changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/pxa-mmc.txt
diff --git a/Documentation/devicetree/bindings/mmc/pxa-mmc.txt b/Documentation/devicetree/bindings/mmc/pxa-mmc.txt
new file mode 100644
index 0000000..b7025de
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/pxa-mmc.txt
@@ -0,0 +1,25 @@
+* PXA MMC drivers
+
+Driver bindings for the PXA MCI (MMC/SDIO) interfaces
+
+Required properties:
+- compatible: Should be "marvell,pxa-mmc".
+- vmmc-supply: A regulator for VMMC
+
+Optional properties:
+- marvell,detect-delay-ms: sets the detection delay timeout in ms.
+- marvell,gpio-power: GPIO spec for the card power enable pin
+
+This file documents differences between the core properties in mmc.txt
+and the properties used by the pxa-mmc driver.
+
+Examples:
+
+mmc0: mmc at 41100000 {
+ compatible = "marvell,pxa-mmc";
+ reg = <0x41100000 0x1000>;
+ interrupts = <23>;
+ cd-gpios = <&gpio 23 0>;
+ wp-gpios = <&gpio 24 0>;
+};
+
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index cb2dc0e..11df800 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -30,6 +30,9 @@
#include <linux/regulator/consumer.h>
#include <linux/gpio.h>
#include <linux/gfp.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/of_device.h>
#include <asm/sizes.h>
@@ -573,6 +576,50 @@ static irqreturn_t pxamci_detect_irq(int irq, void *devid)
return IRQ_HANDLED;
}
+#ifdef CONFIG_OF
+static const struct of_device_id pxa_mmc_dt_ids[] = {
+ { .compatible = "marvell,pxa-mmc" },
+ { }
+};
+
+MODULE_DEVICE_TABLE(of, pxa_mmc_dt_ids);
+
+static int __devinit pxamci_of_init(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct pxamci_platform_data *pdata;
+ u32 tmp;
+
+ if (!np)
+ return 0;
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ pdata->gpio_card_detect =
+ of_get_named_gpio(np, "cd-gpios", 0);
+ pdata->gpio_card_ro =
+ of_get_named_gpio(np, "wp-gpios", 0);
+
+ /* pxa-mmc specific */
+ pdata->gpio_power =
+ of_get_named_gpio(np, "pxa-mmc,gpio-power", 0);
+
+ if (of_property_read_u32(np, "pxa-mmc,detect-delay-ms", &tmp) == 0)
+ pdata->detect_delay_ms = tmp;
+
+ pdev->dev.platform_data = pdata;
+
+ return 0;
+}
+#else
+static int __devinit pxamci_of_init(struct platform_device *pdev)
+{
+ return 0;
+}
+#endif
+
static int pxamci_probe(struct platform_device *pdev)
{
struct mmc_host *mmc;
@@ -580,6 +627,10 @@ static int pxamci_probe(struct platform_device *pdev)
struct resource *r, *dmarx, *dmatx;
int ret, irq, gpio_cd = -1, gpio_ro = -1, gpio_power = -1;
+ ret = pxamci_of_init(pdev);
+ if (ret)
+ return ret;
+
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
irq = platform_get_irq(pdev, 0);
if (!r || irq < 0)
@@ -866,6 +917,7 @@ static struct platform_driver pxamci_driver = {
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(pxa_mmc_dt_ids),
#ifdef CONFIG_PM
.pm = &pxamci_pm_ops,
#endif
--
1.7.11.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v2 3/7] MTD: pxa3xx-nand: add devicetree bindings
2012-07-26 19:16 [PATCH v2 0/7] Assorted PXA3xx DT patches Daniel Mack
2012-07-26 19:16 ` [PATCH v2 1/7] RTC: add DT bindings to pxa-rtc Daniel Mack
2012-07-26 19:16 ` [PATCH v2 2/7] MMC: pxa-mci: add DT bindings Daniel Mack
@ 2012-07-26 19:16 ` Daniel Mack
2012-07-26 19:16 ` [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling Daniel Mack
` (3 subsequent siblings)
6 siblings, 0 replies; 25+ messages in thread
From: Daniel Mack @ 2012-07-26 19:16 UTC (permalink / raw)
To: linux-arm-kernel
This patch contains a hack to get the DMA resources of the device when
probed from a devicetree node. This can be removed once a generic DMA
controller framework lands.
A mtd_part_parser_data is passed mtd_device_parse_register which
contains a reference to the device node, so MTD partitions can be
added as children.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
---
.../devicetree/bindings/mtd/pxa3xx-nand.txt | 31 ++++++++
drivers/mtd/nand/pxa3xx_nand.c | 85 ++++++++++++++++++----
2 files changed, 102 insertions(+), 14 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
new file mode 100644
index 0000000..f1421e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
@@ -0,0 +1,31 @@
+PXA3xx NAND DT bindings
+
+Required properties:
+
+ - compatible: Should be "marvell,pxa3xx-nand"
+ - reg: The register base for the controller
+ - interrupts: The interrupt to map
+ - #address-cells: Set to <1> if the node includes partitions
+
+Optional properties:
+
+ - marvell,nand-enable-arbiter: Set to enable the bus arbiter
+ - marvell,nand-keep-config: Set to keep the NAND controller config as set
+ by the bootloader
+ - num-cs: Number of chipselect lines to usw
+
+Example:
+
+ nand0: nand at 43100000 {
+ compatible = "marvell,pxa3xx-nand";
+ reg = <0x43100000 90>;
+ interrupts = <45>;
+ #address-cells = <1>;
+
+ marvell,nand-enable-arbiter;
+ marvell,nand-keep-config;
+ num-cs = <1>;
+
+ /* partitions (optional) */
+ };
+
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 252aaef..b0319d8 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -22,6 +22,8 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
#include <mach/dma.h>
#include <plat/pxa3xx_nand.h>
@@ -1081,21 +1083,31 @@ static int alloc_nand_resource(struct platform_device *pdev)
}
clk_enable(info->clk);
- r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
- if (r == NULL) {
- dev_err(&pdev->dev, "no resource defined for data DMA\n");
- ret = -ENXIO;
- goto fail_put_clk;
- }
- info->drcmr_dat = r->start;
+ /*
+ * This is a dirty hack to make this driver work from devicetree
+ * bindings. It can be removed once we have a prober DMA controller
+ * framework for DT.
+ */
+ if (pdev->dev.of_node && cpu_is_pxa3xx()) {
+ info->drcmr_dat = 97;
+ info->drcmr_cmd = 99;
+ } else {
+ r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+ if (r == NULL) {
+ dev_err(&pdev->dev, "no resource defined for data DMA\n");
+ ret = -ENXIO;
+ goto fail_put_clk;
+ }
+ info->drcmr_dat = r->start;
- r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
- if (r == NULL) {
- dev_err(&pdev->dev, "no resource defined for command DMA\n");
- ret = -ENXIO;
- goto fail_put_clk;
+ r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
+ if (r == NULL) {
+ dev_err(&pdev->dev, "no resource defined for command DMA\n");
+ ret = -ENXIO;
+ goto fail_put_clk;
+ }
+ info->drcmr_cmd = r->start;
}
- info->drcmr_cmd = r->start;
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
@@ -1200,12 +1212,55 @@ static int pxa3xx_nand_remove(struct platform_device *pdev)
return 0;
}
+#ifdef CONFIG_OF
+static struct of_device_id pxa3xx_nand_dt_ids[] = {
+ { .compatible = "marvell,pxa3xx-nand" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
+
+static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
+{
+ struct pxa3xx_nand_platform_data *pdata;
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *of_id =
+ of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
+
+ if (!of_id)
+ return 0;
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
+ pdata->enable_arbiter = 1;
+ if (of_get_property(np, "marvell,nand-keep-config", NULL))
+ pdata->keep_config = 1;
+ of_property_read_u32(np, "num-cs", &pdata->num_cs);
+
+ pdev->dev.platform_data = pdata;
+
+ return 0;
+}
+#else
+static inline int pxa3xx_nand_probe_dt(struct platform_device *)
+{
+ return 0;
+}
+#endif
+
static int pxa3xx_nand_probe(struct platform_device *pdev)
{
struct pxa3xx_nand_platform_data *pdata;
+ struct mtd_part_parser_data ppdata = {};
struct pxa3xx_nand_info *info;
int ret, cs, probe_success;
+ ret = pxa3xx_nand_probe_dt(pdev);
+ if (ret)
+ return ret;
+
pdata = pdev->dev.platform_data;
if (!pdata) {
dev_err(&pdev->dev, "no platform data defined\n");
@@ -1229,8 +1284,9 @@ static int pxa3xx_nand_probe(struct platform_device *pdev)
continue;
}
+ ppdata.of_node = pdev->dev.of_node;
ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
- NULL, pdata->parts[cs],
+ &ppdata, pdata->parts[cs],
pdata->nr_parts[cs]);
if (!ret)
probe_success = 1;
@@ -1306,6 +1362,7 @@ static int pxa3xx_nand_resume(struct platform_device *pdev)
static struct platform_driver pxa3xx_nand_driver = {
.driver = {
.name = "pxa3xx-nand",
+ .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
},
.probe = pxa3xx_nand_probe,
.remove = pxa3xx_nand_remove,
--
1.7.11.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-26 19:16 [PATCH v2 0/7] Assorted PXA3xx DT patches Daniel Mack
` (2 preceding siblings ...)
2012-07-26 19:16 ` [PATCH v2 3/7] MTD: pxa3xx-nand: add devicetree bindings Daniel Mack
@ 2012-07-26 19:16 ` Daniel Mack
2012-07-28 7:17 ` Haojian Zhuang
2012-07-26 19:16 ` [PATCH v2 5/7] ARM: pxa3xx: skip default device initialization when booting via DT Daniel Mack
` (2 subsequent siblings)
6 siblings, 1 reply; 25+ messages in thread
From: Daniel Mack @ 2012-07-26 19:16 UTC (permalink / raw)
To: linux-arm-kernel
Properly register on-chip interrupt using the irqdomain logic. The
number of interrupts is taken from the devicetree node.
Signed-off-by: Daniel Mack <zonque@gmail.com>
---
arch/arm/mach-pxa/irq.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-pxa/pxa3xx.c | 17 +++++++++--
2 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 5dae15e..7753d09 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -17,6 +17,8 @@
#include <linux/syscore_ops.h>
#include <linux/io.h>
#include <linux/irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <asm/exception.h>
@@ -202,3 +204,74 @@ struct syscore_ops pxa_irq_syscore_ops = {
.suspend = pxa_irq_suspend,
.resume = pxa_irq_resume,
};
+
+#ifdef CONFIG_OF
+static struct irq_domain *pxa_irq_domain;
+
+static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ int irq, i = hw % 32;
+ void __iomem *base = irq_base(hw / 32);
+
+ /* initialize interrupt priority */
+ if (cpu_has_ipr())
+ __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
+
+ irq = PXA_IRQ(virq);
+ irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
+ handle_level_irq);
+ irq_set_chip_data(virq, base);
+ set_irq_flags(virq, IRQF_VALID);
+
+ return 0;
+}
+
+static struct irq_domain_ops pxa_irq_ops = {
+ .map = pxa_irq_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static const struct of_device_id intc_ids[] __initconst = {
+ { .compatible = "marvell,pxa-intc", .data = NULL },
+ {}
+};
+
+void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
+{
+ struct device_node *node;
+ const struct of_device_id *of_id;
+ struct pxa_intc_conf *conf;
+ int nr_irqs, irq_base, ret;
+
+ node = of_find_matching_node(NULL, intc_ids);
+ if (!node) {
+ pr_err("Failed to find interrupt controller in arch-pxa\n");
+ return;
+ }
+ of_id = of_match_node(intc_ids, node);
+ conf = of_id->data;
+
+ ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
+ if (ret) {
+ pr_err("Not found mrvl,intc-nr-irqs property\n");
+ return;
+ }
+
+ irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+ if (irq_base < 0) {
+ pr_err("Failed to allocate IRQ numbers\n");
+ return;
+ }
+
+ pxa_irq_domain = irq_domain_add_legacy(node, nr_irqs, 0, 0,
+ &pxa_irq_ops, NULL);
+ if (!pxa_irq_domain)
+ panic("Unable to add PXA IRQ domain\n");
+
+ irq_set_default_host(pxa_irq_domain);
+ pxa_init_irq(nr_irqs, fn);
+
+ return;
+}
+#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index dffb7e8..1827d3c 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -40,6 +40,8 @@
#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
+extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
+
static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
@@ -382,7 +384,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
pxa_ext_wakeup_chip.irq_set_wake = fn;
}
-void __init pxa3xx_init_irq(void)
+static void __init __pxa3xx_init_irq(void)
{
/* enable CP6 access */
u32 value;
@@ -390,10 +392,21 @@ void __init pxa3xx_init_irq(void)
value |= (1 << 6);
__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
- pxa_init_irq(56, pxa3xx_set_wake);
pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
}
+void __init pxa3xx_init_irq(void)
+{
+ __pxa3xx_init_irq();
+ pxa_init_irq(56, pxa3xx_set_wake);
+}
+
+void __init pxa3xx_dt_init_irq(void)
+{
+ __pxa3xx_init_irq();
+ pxa_dt_irq_init(pxa3xx_set_wake);
+}
+
static struct map_desc pxa3xx_io_desc[] __initdata = {
{ /* Mem Ctl */
.virtual = (unsigned long)SMEMC_VIRT,
--
1.7.11.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-26 19:16 ` [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling Daniel Mack
@ 2012-07-28 7:17 ` Haojian Zhuang
2012-07-28 9:56 ` Daniel Mack
0 siblings, 1 reply; 25+ messages in thread
From: Haojian Zhuang @ 2012-07-28 7:17 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 27, 2012 at 3:16 AM, Daniel Mack <zonque@gmail.com> wrote:
> Properly register on-chip interrupt using the irqdomain logic. The
> number of interrupts is taken from the devicetree node.
>
> Signed-off-by: Daniel Mack <zonque@gmail.com>
> ---
> arch/arm/mach-pxa/irq.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
> arch/arm/mach-pxa/pxa3xx.c | 17 +++++++++--
> 2 files changed, 88 insertions(+), 2 deletions(-)
>
> +#ifdef CONFIG_OF
> +static struct irq_domain *pxa_irq_domain;
> +
> +static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
> + irq_hw_number_t hw)
> +{
> + int irq, i = hw % 32;
> + void __iomem *base = irq_base(hw / 32);
> +
> + /* initialize interrupt priority */
> + if (cpu_has_ipr())
> + __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
Since we have DT support at here. Could we use property for interrupt priority?
> +
> + irq = PXA_IRQ(virq);
#ifdef CONFIG_PXA_HAVE_ISA_IRQS
#define PXA_ISA_IRQ(x) (x)
#define PXA_ISA_IRQ_NUM (16)
#else
#define PXA_ISA_IRQ_NUM (0)
#endif
Could we avoid to use PXA_IRQ() at here? We can make use of
NR_IRQS_LEGACY that is 16. Since you already use irq_alloc_descs()
to allocate irqs that virtual irq number starts from 16. So you needn't
use PXA_IRQ() any more.
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-28 7:17 ` Haojian Zhuang
@ 2012-07-28 9:56 ` Daniel Mack
2012-07-28 15:42 ` Haojian Zhuang
0 siblings, 1 reply; 25+ messages in thread
From: Daniel Mack @ 2012-07-28 9:56 UTC (permalink / raw)
To: linux-arm-kernel
Hi Haojian,
On 28.07.2012 09:17, Haojian Zhuang wrote:
> On Fri, Jul 27, 2012 at 3:16 AM, Daniel Mack <zonque@gmail.com> wrote:
>> Properly register on-chip interrupt using the irqdomain logic. The
>> number of interrupts is taken from the devicetree node.
>>
>> Signed-off-by: Daniel Mack <zonque@gmail.com>
>> ---
>> arch/arm/mach-pxa/irq.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
>> arch/arm/mach-pxa/pxa3xx.c | 17 +++++++++--
>> 2 files changed, 88 insertions(+), 2 deletions(-)
>>
>> +#ifdef CONFIG_OF
>> +static struct irq_domain *pxa_irq_domain;
>> +
>> +static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
>> + irq_hw_number_t hw)
>> +{
>> + int irq, i = hw % 32;
>> + void __iomem *base = irq_base(hw / 32);
>> +
>> + /* initialize interrupt priority */
>> + if (cpu_has_ipr())
>> + __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
> Since we have DT support at here. Could we use property for interrupt priority?
Not sure what you mean here. Can you elaborate? I couldn't find any
reference to IRQ priorities in other platforms either.
Maybe we can also add that in a separate patch, which would also help in
tracking possible regressions du to such a change?
>> + irq = PXA_IRQ(virq);
> #ifdef CONFIG_PXA_HAVE_ISA_IRQS
> #define PXA_ISA_IRQ(x) (x)
> #define PXA_ISA_IRQ_NUM (16)
> #else
> #define PXA_ISA_IRQ_NUM (0)
> #endif
>
> Could we avoid to use PXA_IRQ() at here? We can make use of
> NR_IRQS_LEGACY that is 16. Since you already use irq_alloc_descs()
> to allocate irqs that virtual irq number starts from 16. So you needn't
> use PXA_IRQ() any more.
Ok, I changed this. Note that there's still need to subtract
NR_IRQS_LEGACY from the virq that is passed in to the .map function,
because early_irq_init() in kernel/irq/irqdesc.c will pre-allocate the
IRQs the platform claims to have natively, which defaults to 16 on PXA,
unless the machine descriptor sets nr_irqs, which it doesn't in case of DT.
I also found another hunk that I forgot to squash in the v2 series. I
will repost the whole thing and also include the two GPIO patches that
should go through your tree.
Thanks for the review,
Daniel
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-28 9:56 ` Daniel Mack
@ 2012-07-28 15:42 ` Haojian Zhuang
2012-07-29 14:09 ` Arnd Bergmann
2012-07-29 15:08 ` Daniel Mack
0 siblings, 2 replies; 25+ messages in thread
From: Haojian Zhuang @ 2012-07-28 15:42 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Jul 28, 2012 at 5:56 PM, Daniel Mack <zonque@gmail.com> wrote:
> Hi Haojian,
>
> On 28.07.2012 09:17, Haojian Zhuang wrote:
>> On Fri, Jul 27, 2012 at 3:16 AM, Daniel Mack <zonque@gmail.com> wrote:
>>> Properly register on-chip interrupt using the irqdomain logic. The
>>> number of interrupts is taken from the devicetree node.
>>>
>>> Signed-off-by: Daniel Mack <zonque@gmail.com>
>>> ---
>>> arch/arm/mach-pxa/irq.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
>>> arch/arm/mach-pxa/pxa3xx.c | 17 +++++++++--
>>> 2 files changed, 88 insertions(+), 2 deletions(-)
>>>
>>> +#ifdef CONFIG_OF
>>> +static struct irq_domain *pxa_irq_domain;
>>> +
>>> +static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
>>> + irq_hw_number_t hw)
>>> +{
>>> + int irq, i = hw % 32;
>>> + void __iomem *base = irq_base(hw / 32);
>>> +
>>> + /* initialize interrupt priority */
>>> + if (cpu_has_ipr())
>>> + __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
>> Since we have DT support at here. Could we use property for interrupt priority?
>
> Not sure what you mean here. Can you elaborate? I couldn't find any
> reference to IRQ priorities in other platforms either.
>
> Maybe we can also add that in a separate patch, which would also help in
> tracking possible regressions du to such a change?
>
cpu_has_ipr() returns true if CPU isn't PXA25x.
My point is that we can avoid to use cpu_is_xxx() while DT is used. We only need
to append a property "marvell,intc-priority" is DTS. So the code could
be changed
in below.
if (of_find_property(np, "marvell,intc-priority", NULL))
__raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
>>> + irq = PXA_IRQ(virq);
>> #ifdef CONFIG_PXA_HAVE_ISA_IRQS
>> #define PXA_ISA_IRQ(x) (x)
>> #define PXA_ISA_IRQ_NUM (16)
>> #else
>> #define PXA_ISA_IRQ_NUM (0)
>> #endif
>>
>> Could we avoid to use PXA_IRQ() at here? We can make use of
>> NR_IRQS_LEGACY that is 16. Since you already use irq_alloc_descs()
>> to allocate irqs that virtual irq number starts from 16. So you needn't
>> use PXA_IRQ() any more.
>
> Ok, I changed this. Note that there's still need to subtract
> NR_IRQS_LEGACY from the virq that is passed in to the .map function,
> because early_irq_init() in kernel/irq/irqdesc.c will pre-allocate the
> IRQs the platform claims to have natively, which defaults to 16 on PXA,
> unless the machine descriptor sets nr_irqs, which it doesn't in case of DT.
>
You needn't subtract NR_IRQS_LEGACY. PXA25x hwirq starts from
16 & PXA27x/PXA3xx hwirq starts from 0. While DT is used, irq_alloc_descs()
allocates virq from NR_IRQS_LEGACY. For PXA25x, there's exactly match.
For PXA27x/PXA3xx, there's a little different. But it doesn't matter. We needn't
force virq starting from 0 on PXA27x/PXA3xx. The first virq starts from 16 is
also OK.
Although I use this subtract in arch-mmp, it's a little different in
arch-pxa because
of PXA25x.
> I also found another hunk that I forgot to squash in the v2 series. I
> will repost the whole thing and also include the two GPIO patches that
> should go through your tree.
>
>
> Thanks for the review,
>
> Daniel
>
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-28 15:42 ` Haojian Zhuang
@ 2012-07-29 14:09 ` Arnd Bergmann
2012-07-29 20:40 ` Daniel Mack
2012-07-29 15:08 ` Daniel Mack
1 sibling, 1 reply; 25+ messages in thread
From: Arnd Bergmann @ 2012-07-29 14:09 UTC (permalink / raw)
To: linux-arm-kernel
On Saturday 28 July 2012, Haojian Zhuang wrote:
> On Sat, Jul 28, 2012 at 5:56 PM, Daniel Mack <zonque@gmail.com> wrote:
> >> Since we have DT support at here. Could we use property for interrupt priority?
> >
> > Not sure what you mean here. Can you elaborate? I couldn't find any
> > reference to IRQ priorities in other platforms either.
> >
> > Maybe we can also add that in a separate patch, which would also help in
> > tracking possible regressions du to such a change?
> >
> cpu_has_ipr() returns true if CPU isn't PXA25x.
> My point is that we can avoid to use cpu_is_xxx() while DT is used. We only need
> to append a property "marvell,intc-priority" is DTS. So the code could
> be changed
> in below.
> if (of_find_property(np, "marvell,intc-priority", NULL))
> __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
I think we can do even better if we extend the binding for this interrupt controller
driver to have either #interrupt-cells=<1> or #interrupt-cells=<2>, depending on the
chip that is being used. If the it is <1> (for pxa25x), then any driver would
just use a bare interrupt number. If it's <2> (for all others), the driver would
specify both the interrupt number and the priority, and we set up the register at
the time when the interrupt gets enabled.
Do you think that would work?
Arnd
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-29 14:09 ` Arnd Bergmann
@ 2012-07-29 20:40 ` Daniel Mack
2012-07-30 8:31 ` Arnd Bergmann
0 siblings, 1 reply; 25+ messages in thread
From: Daniel Mack @ 2012-07-29 20:40 UTC (permalink / raw)
To: linux-arm-kernel
On 29.07.2012 16:09, Arnd Bergmann wrote:
> On Saturday 28 July 2012, Haojian Zhuang wrote:
>> On Sat, Jul 28, 2012 at 5:56 PM, Daniel Mack <zonque@gmail.com> wrote:
>>>> Since we have DT support at here. Could we use property for interrupt priority?
>>>
>>> Not sure what you mean here. Can you elaborate? I couldn't find any
>>> reference to IRQ priorities in other platforms either.
>>>
>>> Maybe we can also add that in a separate patch, which would also help in
>>> tracking possible regressions du to such a change?
>>>
>> cpu_has_ipr() returns true if CPU isn't PXA25x.
>> My point is that we can avoid to use cpu_is_xxx() while DT is used. We only need
>> to append a property "marvell,intc-priority" is DTS. So the code could
>> be changed
>> in below.
>> if (of_find_property(np, "marvell,intc-priority", NULL))
>> __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
>
> I think we can do even better if we extend the binding for this interrupt controller
> driver to have either #interrupt-cells=<1> or #interrupt-cells=<2>, depending on the
> chip that is being used. If the it is <1> (for pxa25x), then any driver would
> just use a bare interrupt number. If it's <2> (for all others), the driver would
> specify both the interrupt number and the priority, and we set up the register at
> the time when the interrupt gets enabled.
>
> Do you think that would work?
Hmm, PXA25x (which does not feature IRQ priorities) shares a fair amount
of peripherals with other PXA series (which do have support for that). I
would much like to reflect that fact by inherhiting device nodes from
one dtsi to the other. Hence, if at all, we would need to have two cells
always, and just ignore the second argument on PXA25x.
And I also wonder whether using the second spec value for a priority
wouldn't be somehow abusive? Isn't that considered to denote the trigger
flags in contexts of interrupt controllers? At least, that is what
irq_domain_xlate_twocell() assumes.
Daniel
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-29 20:40 ` Daniel Mack
@ 2012-07-30 8:31 ` Arnd Bergmann
2012-07-30 8:34 ` Daniel Mack
0 siblings, 1 reply; 25+ messages in thread
From: Arnd Bergmann @ 2012-07-30 8:31 UTC (permalink / raw)
To: linux-arm-kernel
On Sunday 29 July 2012, Daniel Mack wrote:
> Hmm, PXA25x (which does not feature IRQ priorities) shares a fair amount
> of peripherals with other PXA series (which do have support for that). I
> would much like to reflect that fact by inherhiting device nodes from
> one dtsi to the other. Hence, if at all, we would need to have two cells
> always, and just ignore the second argument on PXA25x.
But that can only work if the interrupt numbers are identical between PXA25x
and the other SoCs. Are they?
> And I also wonder whether using the second spec value for a priority
> wouldn't be somehow abusive? Isn't that considered to denote the trigger
> flags in contexts of interrupt controllers? At least, that is what
> irq_domain_xlate_twocell() assumes.
You would not use irq_domain_xlate_twocell in that scenario but provide your
own, which is ok. Interpreting the second cell as the trigger flags is just
a convenient default because it's the most common use for that.
Arnd
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-30 8:31 ` Arnd Bergmann
@ 2012-07-30 8:34 ` Daniel Mack
2012-07-30 8:55 ` Haojian Zhuang
0 siblings, 1 reply; 25+ messages in thread
From: Daniel Mack @ 2012-07-30 8:34 UTC (permalink / raw)
To: linux-arm-kernel
On 30.07.2012 10:31, Arnd Bergmann wrote:
> On Sunday 29 July 2012, Daniel Mack wrote:
>> Hmm, PXA25x (which does not feature IRQ priorities) shares a fair amount
>> of peripherals with other PXA series (which do have support for that). I
>> would much like to reflect that fact by inherhiting device nodes from
>> one dtsi to the other. Hence, if at all, we would need to have two cells
>> always, and just ignore the second argument on PXA25x.
>
> But that can only work if the interrupt numbers are identical between PXA25x
> and the other SoCs. Are they?
Yes.
>> And I also wonder whether using the second spec value for a priority
>> wouldn't be somehow abusive? Isn't that considered to denote the trigger
>> flags in contexts of interrupt controllers? At least, that is what
>> irq_domain_xlate_twocell() assumes.
>
> You would not use irq_domain_xlate_twocell in that scenario but provide your
> own, which is ok. Interpreting the second cell as the trigger flags is just
> a convenient default because it's the most common use for that.
I see. Don't know how much sense it makes to have that detail
configurable though. Haojian? And I think we can still change that
detail later.
Daniel
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-30 8:34 ` Daniel Mack
@ 2012-07-30 8:55 ` Haojian Zhuang
2012-07-30 9:31 ` Daniel Mack
0 siblings, 1 reply; 25+ messages in thread
From: Haojian Zhuang @ 2012-07-30 8:55 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 30, 2012 at 4:34 PM, Daniel Mack <zonque@gmail.com> wrote:
> On 30.07.2012 10:31, Arnd Bergmann wrote:
>> On Sunday 29 July 2012, Daniel Mack wrote:
>>> And I also wonder whether using the second spec value for a priority
>>> wouldn't be somehow abusive? Isn't that considered to denote the trigger
>>> flags in contexts of interrupt controllers? At least, that is what
>>> irq_domain_xlate_twocell() assumes.
>>
>> You would not use irq_domain_xlate_twocell in that scenario but provide your
>> own, which is ok. Interpreting the second cell as the trigger flags is just
>> a convenient default because it's the most common use for that.
>
> I see. Don't know how much sense it makes to have that detail
> configurable though. Haojian? And I think we can still change that
> detail later.
>
Arnd's suggestion is good. So we can setup each interrupt's priority
while parsing
all these pxa interrupts. In current code, we only assign priority
with the irq number.
Maybe it's not perfect solution. For example, Timer interrupt should
have highest
priority. LCD interrupt also has higher priority.
It's worth to do. And it's also OK if you want to queue it into your TODO list.
By the way, which patches that you prefer not to go through pxa git tree?
Regards
Haojian
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-30 8:55 ` Haojian Zhuang
@ 2012-07-30 9:31 ` Daniel Mack
2012-07-31 12:18 ` Arnd Bergmann
0 siblings, 1 reply; 25+ messages in thread
From: Daniel Mack @ 2012-07-30 9:31 UTC (permalink / raw)
To: linux-arm-kernel
On 30.07.2012 10:55, Haojian Zhuang wrote:
> On Mon, Jul 30, 2012 at 4:34 PM, Daniel Mack <zonque@gmail.com> wrote:
>> On 30.07.2012 10:31, Arnd Bergmann wrote:
>>> On Sunday 29 July 2012, Daniel Mack wrote:
>>>> And I also wonder whether using the second spec value for a priority
>>>> wouldn't be somehow abusive? Isn't that considered to denote the trigger
>>>> flags in contexts of interrupt controllers? At least, that is what
>>>> irq_domain_xlate_twocell() assumes.
>>>
>>> You would not use irq_domain_xlate_twocell in that scenario but provide your
>>> own, which is ok. Interpreting the second cell as the trigger flags is just
>>> a convenient default because it's the most common use for that.
>>
>> I see. Don't know how much sense it makes to have that detail
>> configurable though. Haojian? And I think we can still change that
>> detail later.
>>
> Arnd's suggestion is good. So we can setup each interrupt's priority
> while parsing
> all these pxa interrupts. In current code, we only assign priority
> with the irq number.
> Maybe it's not perfect solution. For example, Timer interrupt should
> have highest
> priority. LCD interrupt also has higher priority.
Arnd mentioned that instead of using the default
irq_domain_xlate_onecell(), we can hook up our own translation function.
While that is true, I wonder how that value that we send back in
*out_type will ever appear in the irq_chip callbacks. Looking at the
code that calls ->xlate(), I can see that irq_create_of_mapping() would
call irq_set_irq_type() with our passed value, which will then &= it
with IRQ_TYPE_SENSE_MASK (which is 0xf which doesn't suffice for our up
to 96 interrupts).
Arnd, either I don't get your point, or this would need some changes in
the irqdomain core. Could you elaborate a little?
> It's worth to do. And it's also OK if you want to queue it into your TODO list.
Then let's do it as a separate patch later. It's easy to change once we
agree on how to do it.
> By the way, which patches that you prefer not to go through pxa git tree?
I would say you can take all 9 patches that I prepared in the branch
now. I got some feedback on the first round but didn't hear back from
anyone since then.
For the OHCI part (which is not part of it), I don't know if it might be
better to let it go through the USB tree.
Daniel
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-30 9:31 ` Daniel Mack
@ 2012-07-31 12:18 ` Arnd Bergmann
0 siblings, 0 replies; 25+ messages in thread
From: Arnd Bergmann @ 2012-07-31 12:18 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 30 July 2012, Daniel Mack wrote:
> On 30.07.2012 10:55, Haojian Zhuang wrote:
> > On Mon, Jul 30, 2012 at 4:34 PM, Daniel Mack <zonque@gmail.com> wrote:
> >> On 30.07.2012 10:31, Arnd Bergmann wrote:
> >>> On Sunday 29 July 2012, Daniel Mack wrote:
> >>>> And I also wonder whether using the second spec value for a priority
> >>>> wouldn't be somehow abusive? Isn't that considered to denote the trigger
> >>>> flags in contexts of interrupt controllers? At least, that is what
> >>>> irq_domain_xlate_twocell() assumes.
> >>>
> >>> You would not use irq_domain_xlate_twocell in that scenario but provide your
> >>> own, which is ok. Interpreting the second cell as the trigger flags is just
> >>> a convenient default because it's the most common use for that.
> >>
> >> I see. Don't know how much sense it makes to have that detail
> >> configurable though. Haojian? And I think we can still change that
> >> detail later.
> >>
> > Arnd's suggestion is good. So we can setup each interrupt's priority
> > while parsing
> > all these pxa interrupts. In current code, we only assign priority
> > with the irq number.
> > Maybe it's not perfect solution. For example, Timer interrupt should
> > have highest
> > priority. LCD interrupt also has higher priority.
>
> Arnd mentioned that instead of using the default
> irq_domain_xlate_onecell(), we can hook up our own translation function.
> While that is true, I wonder how that value that we send back in
> *out_type will ever appear in the irq_chip callbacks. Looking at the
> code that calls ->xlate(), I can see that irq_create_of_mapping() would
> call irq_set_irq_type() with our passed value, which will then &= it
> with IRQ_TYPE_SENSE_MASK (which is 0xf which doesn't suffice for our up
> to 96 interrupts).
>
> Arnd, either I don't get your point, or this would need some changes in
> the irqdomain core. Could you elaborate a little?
When you have your own xlate function, you would still always set the default
flags (IRQ_TYPE_NONE), but you do record the priority from the flags
in the same way that at91_aic_irq_domain_xlate does.
Arnd
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-28 15:42 ` Haojian Zhuang
2012-07-29 14:09 ` Arnd Bergmann
@ 2012-07-29 15:08 ` Daniel Mack
2012-07-29 15:54 ` Haojian Zhuang
2012-07-29 16:13 ` Haojian Zhuang
1 sibling, 2 replies; 25+ messages in thread
From: Daniel Mack @ 2012-07-29 15:08 UTC (permalink / raw)
To: linux-arm-kernel
Hi Haojian,
On 28.07.2012 17:42, Haojian Zhuang wrote:
> On Sat, Jul 28, 2012 at 5:56 PM, Daniel Mack <zonque@gmail.com> wrote:
>> On 28.07.2012 09:17, Haojian Zhuang wrote:
>>> On Fri, Jul 27, 2012 at 3:16 AM, Daniel Mack <zonque@gmail.com> wrote:
>>>> Properly register on-chip interrupt using the irqdomain logic. The
>>>> number of interrupts is taken from the devicetree node.
>>>>
>>>> Signed-off-by: Daniel Mack <zonque@gmail.com>
>>>> ---
>>>> arch/arm/mach-pxa/irq.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
>>>> arch/arm/mach-pxa/pxa3xx.c | 17 +++++++++--
>>>> 2 files changed, 88 insertions(+), 2 deletions(-)
>>>>
>>>> +#ifdef CONFIG_OF
>>>> +static struct irq_domain *pxa_irq_domain;
>>>> +
>>>> +static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
>>>> + irq_hw_number_t hw)
>>>> +{
>>>> + int irq, i = hw % 32;
>>>> + void __iomem *base = irq_base(hw / 32);
>>>> +
>>>> + /* initialize interrupt priority */
>>>> + if (cpu_has_ipr())
>>>> + __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
>>> Since we have DT support at here. Could we use property for interrupt priority?
>>
>> Not sure what you mean here. Can you elaborate? I couldn't find any
>> reference to IRQ priorities in other platforms either.
>>
>> Maybe we can also add that in a separate patch, which would also help in
>> tracking possible regressions du to such a change?
>>
> cpu_has_ipr() returns true if CPU isn't PXA25x.
> My point is that we can avoid to use cpu_is_xxx() while DT is used. We only need
> to append a property "marvell,intc-priority" is DTS. So the code could
> be changed
> in below.
> if (of_find_property(np, "marvell,intc-priority", NULL))
> __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
>
>>>> + irq = PXA_IRQ(virq);
>>> #ifdef CONFIG_PXA_HAVE_ISA_IRQS
>>> #define PXA_ISA_IRQ(x) (x)
>>> #define PXA_ISA_IRQ_NUM (16)
>>> #else
>>> #define PXA_ISA_IRQ_NUM (0)
>>> #endif
>>>
>>> Could we avoid to use PXA_IRQ() at here? We can make use of
>>> NR_IRQS_LEGACY that is 16. Since you already use irq_alloc_descs()
>>> to allocate irqs that virtual irq number starts from 16. So you needn't
>>> use PXA_IRQ() any more.
>>
>> Ok, I changed this. Note that there's still need to subtract
>> NR_IRQS_LEGACY from the virq that is passed in to the .map function,
>> because early_irq_init() in kernel/irq/irqdesc.c will pre-allocate the
>> IRQs the platform claims to have natively, which defaults to 16 on PXA,
>> unless the machine descriptor sets nr_irqs, which it doesn't in case of DT.
>>
> You needn't subtract NR_IRQS_LEGACY. PXA25x hwirq starts from
> 16 & PXA27x/PXA3xx hwirq starts from 0. While DT is used, irq_alloc_descs()
> allocates virq from NR_IRQS_LEGACY. For PXA25x, there's exactly match.
> For PXA27x/PXA3xx, there's a little different. But it doesn't matter. We needn't
> force virq starting from 0 on PXA27x/PXA3xx. The first virq starts from 16 is
> also OK.
Ok, now I got you. By simply ignoring the virq passed in and only taking
into account the hw irq, this is of course possible.
Please see the attached patch. Does that look better to you? I removed
the cpu_has_ipr() inline function and made it a variable that is used
and initalized from both the DT and the legacy code.
Daniel
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0001-ARM-pxa-add-devicetree-code-for-irq-handling.patch
Type: text/x-patch
Size: 5704 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20120729/89129869/attachment.bin>
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-29 15:08 ` Daniel Mack
@ 2012-07-29 15:54 ` Haojian Zhuang
2012-07-29 19:01 ` Daniel Mack
2012-07-29 16:13 ` Haojian Zhuang
1 sibling, 1 reply; 25+ messages in thread
From: Haojian Zhuang @ 2012-07-29 15:54 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Jul 29, 2012 at 11:08 PM, Daniel Mack <zonque@gmail.com> wrote:
> Hi Haojian,
>
> On 28.07.2012 17:42, Haojian Zhuang wrote:
>> On Sat, Jul 28, 2012 at 5:56 PM, Daniel Mack <zonque@gmail.com> wrote:
>>> On 28.07.2012 09:17, Haojian Zhuang wrote:
>>>> On Fri, Jul 27, 2012 at 3:16 AM, Daniel Mack <zonque@gmail.com> wrote:
>>>>> Properly register on-chip interrupt using the irqdomain logic. The
>>>>> number of interrupts is taken from the devicetree node.
>>>>>
>>>>> Signed-off-by: Daniel Mack <zonque@gmail.com>
>>>>> ---
>>>>> arch/arm/mach-pxa/irq.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
>>>>> arch/arm/mach-pxa/pxa3xx.c | 17 +++++++++--
>>>>> 2 files changed, 88 insertions(+), 2 deletions(-)
>>>>>
>>>>> +#ifdef CONFIG_OF
>>>>> +static struct irq_domain *pxa_irq_domain;
>>>>> +
>>>>> +static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
>>>>> + irq_hw_number_t hw)
>>>>> +{
>>>>> + int irq, i = hw % 32;
>>>>> + void __iomem *base = irq_base(hw / 32);
>>>>> +
>>>>> + /* initialize interrupt priority */
>>>>> + if (cpu_has_ipr())
>>>>> + __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
>>>> Since we have DT support at here. Could we use property for interrupt priority?
>>>
>>> Not sure what you mean here. Can you elaborate? I couldn't find any
>>> reference to IRQ priorities in other platforms either.
>>>
>>> Maybe we can also add that in a separate patch, which would also help in
>>> tracking possible regressions du to such a change?
>>>
>> cpu_has_ipr() returns true if CPU isn't PXA25x.
>> My point is that we can avoid to use cpu_is_xxx() while DT is used. We only need
>> to append a property "marvell,intc-priority" is DTS. So the code could
>> be changed
>> in below.
>> if (of_find_property(np, "marvell,intc-priority", NULL))
>> __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
>>
>>>>> + irq = PXA_IRQ(virq);
>>>> #ifdef CONFIG_PXA_HAVE_ISA_IRQS
>>>> #define PXA_ISA_IRQ(x) (x)
>>>> #define PXA_ISA_IRQ_NUM (16)
>>>> #else
>>>> #define PXA_ISA_IRQ_NUM (0)
>>>> #endif
>>>>
>>>> Could we avoid to use PXA_IRQ() at here? We can make use of
>>>> NR_IRQS_LEGACY that is 16. Since you already use irq_alloc_descs()
>>>> to allocate irqs that virtual irq number starts from 16. So you needn't
>>>> use PXA_IRQ() any more.
>>>
>>> Ok, I changed this. Note that there's still need to subtract
>>> NR_IRQS_LEGACY from the virq that is passed in to the .map function,
>>> because early_irq_init() in kernel/irq/irqdesc.c will pre-allocate the
>>> IRQs the platform claims to have natively, which defaults to 16 on PXA,
>>> unless the machine descriptor sets nr_irqs, which it doesn't in case of DT.
>>>
>> You needn't subtract NR_IRQS_LEGACY. PXA25x hwirq starts from
>> 16 & PXA27x/PXA3xx hwirq starts from 0. While DT is used, irq_alloc_descs()
>> allocates virq from NR_IRQS_LEGACY. For PXA25x, there's exactly match.
>> For PXA27x/PXA3xx, there's a little different. But it doesn't matter. We needn't
>> force virq starting from 0 on PXA27x/PXA3xx. The first virq starts from 16 is
>> also OK.
>
> Ok, now I got you. By simply ignoring the virq passed in and only taking
> into account the hw irq, this is of course possible.
>
> Please see the attached patch. Does that look better to you? I removed
> the cpu_has_ipr() inline function and made it a variable that is used
> and initalized from both the DT and the legacy code.
>
>
> Daniel
>
Yes, both of these two are fixed perfectly. Now let's focus on this in below.
I just find it.
+ if (cpu_has_ipr)
+ __raw_writel(bit | IPR_VALID, IRQ_BASE + IPR(bit));
#define IRQ_BASE io_p2v(0x40d00000)
IRQ_BASE is defined in arch/arm/mach-pxa/irq.c. It's OK for non-DT mode.
If we want to support DT, I hope that all registers mapping should be covered by
of_iomap(). We should discard this kind of static register mapping. You can
find some reference in current code base.
Regards
Haojian
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-29 15:54 ` Haojian Zhuang
@ 2012-07-29 19:01 ` Daniel Mack
2012-07-30 1:20 ` Haojian Zhuang
0 siblings, 1 reply; 25+ messages in thread
From: Daniel Mack @ 2012-07-29 19:01 UTC (permalink / raw)
To: linux-arm-kernel
On 29.07.2012 17:54, Haojian Zhuang wrote:
> On Sun, Jul 29, 2012 at 11:08 PM, Daniel Mack <zonque@gmail.com> wrote:
>> Hi Haojian,
>>
>> On 28.07.2012 17:42, Haojian Zhuang wrote:
>>> On Sat, Jul 28, 2012 at 5:56 PM, Daniel Mack <zonque@gmail.com> wrote:
>>>> On 28.07.2012 09:17, Haojian Zhuang wrote:
>>>>> On Fri, Jul 27, 2012 at 3:16 AM, Daniel Mack <zonque@gmail.com> wrote:
>>>>>> Properly register on-chip interrupt using the irqdomain logic. The
>>>>>> number of interrupts is taken from the devicetree node.
>>>>>>
>>>>>> Signed-off-by: Daniel Mack <zonque@gmail.com>
>>>>>> ---
>>>>>> arch/arm/mach-pxa/irq.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
>>>>>> arch/arm/mach-pxa/pxa3xx.c | 17 +++++++++--
>>>>>> 2 files changed, 88 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> +#ifdef CONFIG_OF
>>>>>> +static struct irq_domain *pxa_irq_domain;
>>>>>> +
>>>>>> +static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
>>>>>> + irq_hw_number_t hw)
>>>>>> +{
>>>>>> + int irq, i = hw % 32;
>>>>>> + void __iomem *base = irq_base(hw / 32);
>>>>>> +
>>>>>> + /* initialize interrupt priority */
>>>>>> + if (cpu_has_ipr())
>>>>>> + __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
>>>>> Since we have DT support at here. Could we use property for interrupt priority?
>>>>
>>>> Not sure what you mean here. Can you elaborate? I couldn't find any
>>>> reference to IRQ priorities in other platforms either.
>>>>
>>>> Maybe we can also add that in a separate patch, which would also help in
>>>> tracking possible regressions du to such a change?
>>>>
>>> cpu_has_ipr() returns true if CPU isn't PXA25x.
>>> My point is that we can avoid to use cpu_is_xxx() while DT is used. We only need
>>> to append a property "marvell,intc-priority" is DTS. So the code could
>>> be changed
>>> in below.
>>> if (of_find_property(np, "marvell,intc-priority", NULL))
>>> __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
>>>
>>>>>> + irq = PXA_IRQ(virq);
>>>>> #ifdef CONFIG_PXA_HAVE_ISA_IRQS
>>>>> #define PXA_ISA_IRQ(x) (x)
>>>>> #define PXA_ISA_IRQ_NUM (16)
>>>>> #else
>>>>> #define PXA_ISA_IRQ_NUM (0)
>>>>> #endif
>>>>>
>>>>> Could we avoid to use PXA_IRQ() at here? We can make use of
>>>>> NR_IRQS_LEGACY that is 16. Since you already use irq_alloc_descs()
>>>>> to allocate irqs that virtual irq number starts from 16. So you needn't
>>>>> use PXA_IRQ() any more.
>>>>
>>>> Ok, I changed this. Note that there's still need to subtract
>>>> NR_IRQS_LEGACY from the virq that is passed in to the .map function,
>>>> because early_irq_init() in kernel/irq/irqdesc.c will pre-allocate the
>>>> IRQs the platform claims to have natively, which defaults to 16 on PXA,
>>>> unless the machine descriptor sets nr_irqs, which it doesn't in case of DT.
>>>>
>>> You needn't subtract NR_IRQS_LEGACY. PXA25x hwirq starts from
>>> 16 & PXA27x/PXA3xx hwirq starts from 0. While DT is used, irq_alloc_descs()
>>> allocates virq from NR_IRQS_LEGACY. For PXA25x, there's exactly match.
>>> For PXA27x/PXA3xx, there's a little different. But it doesn't matter. We needn't
>>> force virq starting from 0 on PXA27x/PXA3xx. The first virq starts from 16 is
>>> also OK.
>>
>> Ok, now I got you. By simply ignoring the virq passed in and only taking
>> into account the hw irq, this is of course possible.
>>
>> Please see the attached patch. Does that look better to you? I removed
>> the cpu_has_ipr() inline function and made it a variable that is used
>> and initalized from both the DT and the legacy code.
>>
>>
>> Daniel
>>
>
> Yes, both of these two are fixed perfectly. Now let's focus on this in below.
> I just find it.
>
> + if (cpu_has_ipr)
> + __raw_writel(bit | IPR_VALID, IRQ_BASE + IPR(bit));
>
> #define IRQ_BASE io_p2v(0x40d00000)
>
> IRQ_BASE is defined in arch/arm/mach-pxa/irq.c. It's OK for non-DT mode.
> If we want to support DT, I hope that all registers mapping should be covered by
> of_iomap(). We should discard this kind of static register mapping. You can
> find some reference in current code base.
Ok, you're right. I thought it's ok to keep it that way as the entire
code here is really limited to pxa SoCs (which all have the same
physical address offset), but we should indeed take as much information
as possible from the tree.
Please check the appended version. What I also changed now is that
pxa_init_irq() only really handles non-DT initialization, so we have to
care for some details in pxa_dt_irq_init() separately. Also, the map()
function still had a bug, which I also fixed.
Thanks for your feedback,
Daniel
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0001-ARM-pxa-add-devicetree-code-for-irq-handling.patch
Type: text/x-patch
Size: 7795 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20120729/94f932b2/attachment.bin>
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-29 19:01 ` Daniel Mack
@ 2012-07-30 1:20 ` Haojian Zhuang
2012-07-30 1:24 ` Haojian Zhuang
0 siblings, 1 reply; 25+ messages in thread
From: Haojian Zhuang @ 2012-07-30 1:20 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 30, 2012 at 3:01 AM, Daniel Mack <zonque@gmail.com> wrote:
>
> Please check the appended version. What I also changed now is that
> pxa_init_irq() only really handles non-DT initialization, so we have to
> care for some details in pxa_dt_irq_init() separately. Also, the map()
> function still had a bug, which I also fixed.
>
>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Since "marvell,intc-priority" is appended. Maybe you need to update the DTSI
file. How about send out the updated v4 patch series? I'll merge it in
this week.
Regards
Haojian
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-30 1:20 ` Haojian Zhuang
@ 2012-07-30 1:24 ` Haojian Zhuang
2012-07-30 7:11 ` Daniel Mack
0 siblings, 1 reply; 25+ messages in thread
From: Haojian Zhuang @ 2012-07-30 1:24 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 30, 2012 at 9:20 AM, Haojian Zhuang
<haojian.zhuang@gmail.com> wrote:
> On Mon, Jul 30, 2012 at 3:01 AM, Daniel Mack <zonque@gmail.com> wrote:
>>
>> Please check the appended version. What I also changed now is that
>> pxa_init_irq() only really handles non-DT initialization, so we have to
>> care for some details in pxa_dt_irq_init() separately. Also, the map()
>> function still had a bug, which I also fixed.
>>
>>
> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
>
> Since "marvell,intc-priority" is appended. Maybe you need to update the DTSI
> file. How about send out the updated v4 patch series? I'll merge it in
> this week.
>
> Regards
> Haojian
I requested for you sending patch since 2 patches in v3 are lost in my
gmail account.
Regards
Haojian
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-30 1:24 ` Haojian Zhuang
@ 2012-07-30 7:11 ` Daniel Mack
0 siblings, 0 replies; 25+ messages in thread
From: Daniel Mack @ 2012-07-30 7:11 UTC (permalink / raw)
To: linux-arm-kernel
On 30.07.2012 03:24, Haojian Zhuang wrote:
> On Mon, Jul 30, 2012 at 9:20 AM, Haojian Zhuang
> <haojian.zhuang@gmail.com> wrote:
>> On Mon, Jul 30, 2012 at 3:01 AM, Daniel Mack <zonque@gmail.com> wrote:
>>>
>>> Please check the appended version. What I also changed now is that
>>> pxa_init_irq() only really handles non-DT initialization, so we have to
>>> care for some details in pxa_dt_irq_init() separately. Also, the map()
>>> function still had a bug, which I also fixed.
>>>
>>>
>> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
>>
>> Since "marvell,intc-priority" is appended. Maybe you need to update the DTSI
>> file. How about send out the updated v4 patch series? I'll merge it in
>> this week.
>>
>> Regards
>> Haojian
>
> I requested for you sending patch since 2 patches in v3 are lost in my
> gmail account.
To avoid mailing out the whole series to everybody again, even though
most of them haven't changed, I prepared a branch that includes all 9
patches on top of Linus' current tree:
git://github.com/zonque/linux.git pxa-dt
Is it ok for you to pick the patches from there? Otherwise, I can of
course send them out by email again as well.
Thanks,
Daniel
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling
2012-07-29 15:08 ` Daniel Mack
2012-07-29 15:54 ` Haojian Zhuang
@ 2012-07-29 16:13 ` Haojian Zhuang
1 sibling, 0 replies; 25+ messages in thread
From: Haojian Zhuang @ 2012-07-29 16:13 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Jul 29, 2012 at 11:08 PM, Daniel Mack <zonque@gmail.com> wrote:
> Hi Haojian,
>
> On 28.07.2012 17:42, Haojian Zhuang wrote:
>> On Sat, Jul 28, 2012 at 5:56 PM, Daniel Mack <zonque@gmail.com> wrote:
>>> On 28.07.2012 09:17, Haojian Zhuang wrote:
>>>> On Fri, Jul 27, 2012 at 3:16 AM, Daniel Mack <zonque@gmail.com> wrote:
>>>>> Properly register on-chip interrupt using the irqdomain logic. The
>>>>> number of interrupts is taken from the devicetree node.
>>>>>
>>>>> Signed-off-by: Daniel Mack <zonque@gmail.com>
>>>>> ---
>>>>> arch/arm/mach-pxa/irq.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
>>>>> arch/arm/mach-pxa/pxa3xx.c | 17 +++++++++--
>>>>> 2 files changed, 88 insertions(+), 2 deletions(-)
>>>>>
>>>>> +#ifdef CONFIG_OF
>>>>> +static struct irq_domain *pxa_irq_domain;
>>>>> +
>>>>> +static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
>>>>> + irq_hw_number_t hw)
>>>>> +{
>>>>> + int irq, i = hw % 32;
>>>>> + void __iomem *base = irq_base(hw / 32);
>>>>> +
>>>>> + /* initialize interrupt priority */
>>>>> + if (cpu_has_ipr())
>>>>> + __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
>>>> Since we have DT support at here. Could we use property for interrupt priority?
>>>
>>> Not sure what you mean here. Can you elaborate? I couldn't find any
>>> reference to IRQ priorities in other platforms either.
>>>
>>> Maybe we can also add that in a separate patch, which would also help in
>>> tracking possible regressions du to such a change?
>>>
>> cpu_has_ipr() returns true if CPU isn't PXA25x.
>> My point is that we can avoid to use cpu_is_xxx() while DT is used. We only need
>> to append a property "marvell,intc-priority" is DTS. So the code could
>> be changed
>> in below.
>> if (of_find_property(np, "marvell,intc-priority", NULL))
>> __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
>>
>
> Please see the attached patch. Does that look better to you? I removed
> the cpu_has_ipr() inline function and made it a variable that is used
> and initalized from both the DT and the legacy code.
>
>
> Daniel
>
Don't forget to append this property into .dtsi file. Only PXA25x don't support
this property.
Regards
Haojian
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 5/7] ARM: pxa3xx: skip default device initialization when booting via DT
2012-07-26 19:16 [PATCH v2 0/7] Assorted PXA3xx DT patches Daniel Mack
` (3 preceding siblings ...)
2012-07-26 19:16 ` [PATCH v2 4/7] ARM: pxa: add devicetree code for irq handling Daniel Mack
@ 2012-07-26 19:16 ` Daniel Mack
2012-07-26 19:16 ` [PATCH v2 6/7] ARM: pxa3xx: add generic DT machine code Daniel Mack
2012-07-26 19:16 ` [PATCH v2 7/7] ARM: pxa: add .dtsi files Daniel Mack
6 siblings, 0 replies; 25+ messages in thread
From: Daniel Mack @ 2012-07-26 19:16 UTC (permalink / raw)
To: linux-arm-kernel
When booting via DT, the default PXA devices must not have been probed
before, otherwise the augmented information from the device tree is
ignored.
Signed-off-by: Daniel Mack <zonque@gmail.com>
---
arch/arm/mach-pxa/pxa3xx.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 1827d3c..4a9d04a 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -19,6 +19,7 @@
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
+#include <linux/of.h>
#include <linux/syscore_ops.h>
#include <linux/i2c/pxa-i2c.h>
@@ -479,7 +480,8 @@ static int __init pxa3xx_init(void)
register_syscore_ops(&pxa3xx_mfp_syscore_ops);
register_syscore_ops(&pxa3xx_clock_syscore_ops);
- ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+ if (!of_have_populated_dt())
+ ret = platform_add_devices(devices, ARRAY_SIZE(devices));
}
return ret;
--
1.7.11.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v2 6/7] ARM: pxa3xx: add generic DT machine code
2012-07-26 19:16 [PATCH v2 0/7] Assorted PXA3xx DT patches Daniel Mack
` (4 preceding siblings ...)
2012-07-26 19:16 ` [PATCH v2 5/7] ARM: pxa3xx: skip default device initialization when booting via DT Daniel Mack
@ 2012-07-26 19:16 ` Daniel Mack
2012-07-26 19:16 ` [PATCH v2 7/7] ARM: pxa: add .dtsi files Daniel Mack
6 siblings, 0 replies; 25+ messages in thread
From: Daniel Mack @ 2012-07-26 19:16 UTC (permalink / raw)
To: linux-arm-kernel
Add a DT_MACHINE_START entry for PXA3xx machines and a auxdata table for
some of the devices. This file can be extended to also support pxa2xx
and pxa9xx boards.
Signed-off-by: Daniel Mack <zonque@gmail.com>
---
arch/arm/mach-pxa/Kconfig | 12 +++++++++
arch/arm/mach-pxa/Makefile | 3 +++
arch/arm/mach-pxa/pxa-dt.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 78 insertions(+)
create mode 100644 arch/arm/mach-pxa/pxa-dt.c
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index fe2d1f8..8e6288d 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -25,6 +25,18 @@ config PXA_V7_MACH_AUTO
if !ARCH_PXA_V7
comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
+config MACH_PXA3XX_DT
+ bool "Support PXA3xx platforms from device tree"
+ select PXA3xx
+ select CPU_PXA300
+ select POWER_SUPPLY
+ select HAVE_PWM
+ select USE_OF
+ help
+ Include support for Marvell PXA3xx based platforms using
+ the device tree. Needn't select any other machine while
+ MACH_PXA3XX_DT is enabled.
+
config ARCH_LUBBOCK
bool "Intel DBPXA250 Development Platform (aka Lubbock)"
select PXA25x
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index be0f7df..2bedc9e 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -26,6 +26,9 @@ obj-$(CONFIG_CPU_PXA930) += pxa930.o
# NOTE: keep the order of boards in accordance to their order in Kconfig
+# Device Tree support
+obj-$(CONFIG_MACH_PXA3XX_DT) += pxa-dt.o
+
# Intel/Marvell Dev Platforms
obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c
new file mode 100644
index 0000000..dfe245d
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa-dt.c
@@ -0,0 +1,63 @@
+/*
+ * linux/arch/arm/mach-pxa/pxa-dt.c
+ *
+ * Copyright (C) 2012 Daniel Mack
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/pxa3xx.h>
+
+#include "generic.h"
+
+#ifdef CONFIG_PXA3xx
+extern void __init pxa3xx_dt_init_irq(void);
+
+static const struct of_dev_auxdata pxa3xx_auxdata_lookup[] __initconst = {
+ OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40100000, "pxa2xx-uart.0", NULL),
+ OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40200000, "pxa2xx-uart.1", NULL),
+ OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40700000, "pxa2xx-uart.2", NULL),
+ OF_DEV_AUXDATA("mrvl,pxa-uart", 0x41600000, "pxa2xx-uart.3", NULL),
+ OF_DEV_AUXDATA("mrvl,pxa-mmc", 0x41100000, "pxa2xx-mci.0", NULL),
+ OF_DEV_AUXDATA("mrvl,pxa-gpio", 0x40e00000, "pxa-gpio", NULL),
+ OF_DEV_AUXDATA("mrvl,pxa-ohci", 0x4c000000, "pxa27x-ohci", NULL),
+ OF_DEV_AUXDATA("mrvl,pxa-i2c", 0x40301680, "pxa2xx-i2c.0", NULL),
+ OF_DEV_AUXDATA("mrvl,pwri2c", 0x40f500c0, "pxa3xx-i2c.1", NULL),
+ OF_DEV_AUXDATA("mrvl,pxa3xx-nand", 0x43100000, "pxa3xx-nand", NULL),
+ {}
+};
+
+static void __init pxa3xx_dt_init(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table,
+ pxa3xx_auxdata_lookup, NULL);
+}
+
+static const char *pxa3xx_dt_board_compat[] __initdata = {
+ "marvell,pxa300",
+ "marvell,pxa310",
+ "marvell,pxa320",
+ NULL,
+};
+#endif
+
+#ifdef CONFIG_PXA3xx
+DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)")
+ .map_io = pxa3xx_map_io,
+ .init_irq = pxa3xx_dt_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
+ .timer = &pxa_timer,
+ .restart = pxa_restart,
+ .init_machine = pxa3xx_dt_init,
+ .dt_compat = pxa3xx_dt_board_compat,
+MACHINE_END
+#endif
--
1.7.11.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v2 7/7] ARM: pxa: add .dtsi files
2012-07-26 19:16 [PATCH v2 0/7] Assorted PXA3xx DT patches Daniel Mack
` (5 preceding siblings ...)
2012-07-26 19:16 ` [PATCH v2 6/7] ARM: pxa3xx: add generic DT machine code Daniel Mack
@ 2012-07-26 19:16 ` Daniel Mack
6 siblings, 0 replies; 25+ messages in thread
From: Daniel Mack @ 2012-07-26 19:16 UTC (permalink / raw)
To: linux-arm-kernel
This adds .dtsi files to describe the PXA SoCs. pxa3xx simply augments
pxa2xx. Not all devices are listed yet, and it will need some time to
get all the drivers ported.
Signed-off-by: Daniel Mack <zonque@gmail.com>
---
arch/arm/boot/dts/pxa2xx.dtsi | 132 ++++++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/pxa3xx.dtsi | 27 +++++++++
2 files changed, 159 insertions(+)
create mode 100644 arch/arm/boot/dts/pxa2xx.dtsi
create mode 100644 arch/arm/boot/dts/pxa3xx.dtsi
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
new file mode 100644
index 0000000..4fe3b91
--- /dev/null
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -0,0 +1,132 @@
+/*
+ * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "Marvell PXA2xx family SoC";
+ compatible = "marvell,pxa2xx";
+ interrupt-parent = <&pxairq>;
+
+ aliases {
+ serial0 = &ffuart;
+ serial1 = &btuart;
+ serial2 = &stuart;
+ serial3 = &hwuart;
+ i2c0 = &pwri2c;
+ i2c1 = &pxai2c1;
+ };
+
+ cpus {
+ cpu at 0 {
+ compatible = "arm,xscale";
+ };
+ };
+
+ pxabus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pxairq: interrupt-controller at 40d00000 {
+ #interrupt-cells = <1>;
+ compatible = "marvell,pxa-intc";
+ interrupt-controller;
+ interrupt-parent;
+ mrvl,intc-nr-irqs = <56>;
+ reg = <0x40d00000 0xd0>;
+ };
+
+ gpio: gpio at 40e00000 {
+ compatible = "mrvl,pxa-gpio";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ reg = <0x40e00000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ interrupts = <10>;
+ interrupt-names = "gpio_mux";
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ ranges;
+
+ gcb0: gpio at 40e00000 {
+ reg = <0x40e00000 0x4>;
+ };
+
+ gcb1: gpio at 40e00004 {
+ reg = <0x40e00004 0x4>;
+ };
+
+ gcb2: gpio at 40e00008 {
+ reg = <0x40e00008 0x4>;
+ };
+ gcb3: gpio at 40e0000c {
+ reg = <0x40e0000c 0x4>;
+ };
+ };
+
+ ffuart: uart at 40100000 {
+ compatible = "mrvl,pxa-uart";
+ reg = <0x40100000 0x30>;
+ interrupts = <22>;
+ status = "disabled";
+ };
+
+ btuart: uart at 40200000 {
+ compatible = "mrvl,pxa-uart";
+ reg = <0x40200000 0x30>;
+ interrupts = <21>;
+ status = "disabled";
+ };
+
+ stuart: uart at 40700000 {
+ compatible = "mrvl,pxa-uart";
+ reg = <0x40700000 0x30>;
+ interrupts = <20>;
+ status = "disabled";
+ };
+
+ hwuart: uart at 41100000 {
+ compatible = "mrvl,pxa-uart";
+ reg = <0x41100000 0x30>;
+ interrupts = <7>;
+ status = "disabled";
+ };
+
+ pxai2c1: i2c at 40301680 {
+ compatible = "mrvl,pxa-i2c";
+ reg = <0x40301680 0x30>;
+ interrupts = <18>;
+ #address-cells = <0x1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ usb0: ohci at 4c000000 {
+ compatible = "mrvl,pxa-ohci";
+ reg = <0x4c000000 0x10000>;
+ interrupts = <3>;
+ status = "disabled";
+ };
+
+ mmc0: mmc at 41100000 {
+ compatible = "mrvl,pxa-mmc";
+ reg = <0x41100000 0x1000>;
+ interrupts = <23>;
+ status = "disabled";
+ };
+
+ rtc at 40900000 {
+ compatible = "marvell,pxa-rtc";
+ reg = <0x40900000 0x3c>;
+ interrupts = <30 31>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
new file mode 100644
index 0000000..41e0a42
--- /dev/null
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -0,0 +1,27 @@
+/* The pxa3xx skeleton simply augments the 2xx version */
+/include/ "pxa2xx.dtsi"
+
+/ {
+ model = "Marvell PXA3xx familiy SoC";
+ compatible = "marvell,pxa3xx";
+
+ pxabus {
+ pwri2c: i2c at 40f500c0 {
+ compatible = "mrvl,pwri2c";
+ reg = <0x40f500c0 0x30>;
+ interrupts = <6>;
+ #address-cells = <0x1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ nand0: nand at 43100000 {
+ compatible = "marvell,pxa3xx-nand";
+ reg = <0x43100000 90>;
+ interrupts = <45>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
+ };
+};
--
1.7.11.2
^ permalink raw reply related [flat|nested] 25+ messages in thread