Re: [Qemu-devel] [PATCH] MIPS: Correct FCR0 initialization

[Phil Staub <phils@windriver.com>]

On 08/07/2012 05:10 AM, Peter Maydell wrote:
> On 6 August 2012 19:21, Phil Staub <phil.staub@windriver.com> wrote:
>> On Tue, Jun 12, 2012 at 10:28:14AM -0400, qemu-devel-request@nongnu.org wrote:
>>> From: Richard Henderson <rth@twiddle.net>
>>> On 2012-06-07 18:04, Maciej W. Rozycki wrote:
>>>>   I have verified this change with system emulation running the GDB test
>>>> suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated),
>>>> there were 55 progressions and no regressions.
>>>>
>>>> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
>>>> ---
>>>>
>>>>   Sent on behalf of Nathan, who's since left the company.  Please apply.
>>>>
>>>>    Maciej
>>>>
>>>> qemu-mips-fcr0.diff
>>>> Index: qemu-git-trunk/target-mips/translate.c
>>>> ===================================================================
>>>> --- qemu-git-trunk.orig/target-mips/translate.c     2012-06-04 05:35:53.245610241 +0100
>>>> +++ qemu-git-trunk/target-mips/translate.c  2012-06-04 05:39:26.245563823 +0100
>>>> @@ -12776,6 +12776,7 @@ void cpu_state_reset(CPUMIPSState *env)
>>>>       env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
>>>>       env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
>>>>       env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
>>>> +    env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
>>>
>>> Reviewed-by: Richard Henderson <rth@twiddle.net>
>
>> What are the plans for this patch? It doesn't appear to have been
>> applied in any of the repository branches.
>
> Basically MIPS is currently without an active maintainer, so
> people submitting patches need to keep pinging them until
> one of the core maintainers (usually Blue Swirl) applies them.
> For this purpose the usual approach is to follow up to the patch
> mail saying "Ping" and giving a url to the patch in patchwork,
> like this one:
> http://patchwork.ozlabs.org/patch/163705/
>
> Eventually somebody will take pity on it and apply it, but
> it does require a bit more persistence than for more actively
> maintained areas of the codebase.

Thanks for the advice, Peter. It gives me an idea of what to expect if
I need to address other MIPS issues...

Phil

>
> -- PMM
>
>


-- 
Phil Staub, Senior Member of Technical Staff, Wind River
Direct: 702.290.0470 Fax: 702.982.0085