From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Suman Anna <s-anna@ti.com>
Cc: Benoit Cousson <bcousson@baylibre.com>,
Tony Lindgren <tony@atomide.com>,
Florian Vaussard <florian.vaussard@epfl.ch>,
devicetree@vger.kernel.org, iommu@lists.linux-foundation.org,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 3/4] ARM: dts: OMAP4: Add IOMMU nodes
Date: Wed, 26 Feb 2014 22:05:17 +0100 [thread overview]
Message-ID: <5025565.C2g8cq3k2V@avalon> (raw)
In-Reply-To: <1392315776-33197-4-git-send-email-s-anna@ti.com>
Hi Suman,
Thank you for the patch.
On Thursday 13 February 2014 12:22:55 Suman Anna wrote:
> From: Florian Vaussard <florian.vaussard@epfl.ch>
>
> Add the IOMMU nodes for the DSP and IPU subsystems. The external
> address space for DSP starts at 0x20000000 in OMAP4 compared to
> 0x11000000 in OMAP3, and the addresses beyond 0xE0000000 are
> private address space for the Cortex-M3 cores in the IPU subsystem.
> The MMU within the IPU sub-system also supports a bus error back
> capability, not available on the DSP MMU.
>
> Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
> [s-anna@ti.com: dma-window updates and bus error back addition]
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
> arch/arm/boot/dts/omap4.dtsi | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index d3f8a6e..1885f90 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -461,6 +461,23 @@
> dma-names = "tx", "rx";
> };
>
> + mmu_dsp: mmu@4a066000 {
> + compatible = "ti,omap4-iommu";
> + reg = <0x4a066000 0xff>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + ti,hwmods = "mmu_dsp";
> + dma-window = <0x20000000 0xdffff000>;
> + };
> +
> + mmu_ipu: mmu@55082000 {
> + compatible = "ti,omap4-iommu";
> + reg = <0x55082000 0xff>;
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + ti,hwmods = "mmu_ipu";
> + dma-window = <0 0xdffff000>;
I'm not too familiar with the M3 MPU in the OMAP4, but doesn't its memory map
also include other reserved regions, such as 0x55040000- 0x5505ffff to access
the ISS ?
> + ti,iommu-bus-err-back;
> + };
> +
> wdt2: wdt@4a314000 {
> compatible = "ti,omap4-wdt", "ti,omap3-wdt";
> reg = <0x4a314000 0x80>;
--
Regards,
Laurent Pinchart
WARNING: multiple messages have this Message-ID (diff)
From: laurent.pinchart@ideasonboard.com (Laurent Pinchart)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/4] ARM: dts: OMAP4: Add IOMMU nodes
Date: Wed, 26 Feb 2014 22:05:17 +0100 [thread overview]
Message-ID: <5025565.C2g8cq3k2V@avalon> (raw)
In-Reply-To: <1392315776-33197-4-git-send-email-s-anna@ti.com>
Hi Suman,
Thank you for the patch.
On Thursday 13 February 2014 12:22:55 Suman Anna wrote:
> From: Florian Vaussard <florian.vaussard@epfl.ch>
>
> Add the IOMMU nodes for the DSP and IPU subsystems. The external
> address space for DSP starts at 0x20000000 in OMAP4 compared to
> 0x11000000 in OMAP3, and the addresses beyond 0xE0000000 are
> private address space for the Cortex-M3 cores in the IPU subsystem.
> The MMU within the IPU sub-system also supports a bus error back
> capability, not available on the DSP MMU.
>
> Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
> [s-anna at ti.com: dma-window updates and bus error back addition]
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
> arch/arm/boot/dts/omap4.dtsi | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index d3f8a6e..1885f90 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -461,6 +461,23 @@
> dma-names = "tx", "rx";
> };
>
> + mmu_dsp: mmu at 4a066000 {
> + compatible = "ti,omap4-iommu";
> + reg = <0x4a066000 0xff>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + ti,hwmods = "mmu_dsp";
> + dma-window = <0x20000000 0xdffff000>;
> + };
> +
> + mmu_ipu: mmu at 55082000 {
> + compatible = "ti,omap4-iommu";
> + reg = <0x55082000 0xff>;
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + ti,hwmods = "mmu_ipu";
> + dma-window = <0 0xdffff000>;
I'm not too familiar with the M3 MPU in the OMAP4, but doesn't its memory map
also include other reserved regions, such as 0x55040000- 0x5505ffff to access
the ISS ?
> + ti,iommu-bus-err-back;
> + };
> +
> wdt2: wdt at 4a314000 {
> compatible = "ti,omap4-wdt", "ti,omap3-wdt";
> reg = <0x4a314000 0x80>;
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2014-02-26 21:05 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-13 18:22 [PATCH 0/4] OMAP IOMMU DTS nodes Suman Anna
2014-02-13 18:22 ` Suman Anna
[not found] ` <1392315776-33197-1-git-send-email-s-anna-l0cyMroinI0@public.gmane.org>
2014-02-13 18:22 ` [PATCH 1/4] ARM: dts: OMAP3: Update ISP IOMMU node Suman Anna
2014-02-13 18:22 ` Suman Anna
2014-02-13 18:22 ` [PATCH 2/4] ARM: dts: OMAP3: Add IVA " Suman Anna
2014-02-13 18:22 ` Suman Anna
2014-02-13 18:22 ` [PATCH 3/4] ARM: dts: OMAP4: Add IOMMU nodes Suman Anna
2014-02-13 18:22 ` Suman Anna
2014-02-26 21:05 ` Laurent Pinchart [this message]
2014-02-26 21:05 ` Laurent Pinchart
2014-02-26 22:06 ` Suman Anna
2014-02-26 22:06 ` Suman Anna
2014-02-13 18:22 ` [PATCH 4/4] ARM: dts: OMAP5: " Suman Anna
2014-02-13 18:22 ` Suman Anna
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