[PATCH v2] drm/i915: fix color order for BGR formats on IVB

[PATCH v2] drm/i915: fix color order for BGR formats on IVB

[Vijay Purushothaman]

This is already fixed for ILK and SNB in the below commit but somehow
IVB is missed.

commit ab2f9df10dd955f1fc0a8650e377588c98f1c029
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Mon Feb 27 12:40:10 2012 -0800

    drm/i915: fix color order for BGR formats on SNB

Had the wrong bits and field definitions.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Lin <ben.y.lin@intel.com>
---
 drivers/gpu/drm/i915/intel_sprite.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index cc8df4d..6045a01 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -54,17 +54,17 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 
 	/* Mask out pixel format bits in case we change it */
 	sprctl &= ~SPRITE_PIXFORMAT_MASK;
-	sprctl &= ~SPRITE_RGB_ORDER_RGBX;
+	sprctl &= ~SPRITE_RGB_ORDER_XBGR;
 	sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
 	sprctl &= ~SPRITE_TILED;
 
 	switch (fb->pixel_format) {
 	case DRM_FORMAT_XBGR8888:
-		sprctl |= SPRITE_FORMAT_RGBX888;
+		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 		pixel_size = 4;
 		break;
 	case DRM_FORMAT_XRGB8888:
-		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
+		sprctl |= SPRITE_FORMAT_RGBX888;
 		pixel_size = 4;
 		break;
 	case DRM_FORMAT_YUYV:
-- 
1.7.9.5

Re: [PATCH v2] drm/i915: fix color order for BGR formats on IVB

[Antti Koskipää]

Hi,

On 08/22/12 12:17, Vijay Purushothaman wrote:
> This is already fixed for ILK and SNB in the below commit but somehow
> IVB is missed.
> 
> commit ab2f9df10dd955f1fc0a8650e377588c98f1c029
> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date:   Mon Feb 27 12:40:10 2012 -0800
> 
>     drm/i915: fix color order for BGR formats on SNB
> 
> Had the wrong bits and field definitions.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Lin <ben.y.lin@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_sprite.c |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index cc8df4d..6045a01 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -54,17 +54,17 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
>  
>  	/* Mask out pixel format bits in case we change it */
>  	sprctl &= ~SPRITE_PIXFORMAT_MASK;
> -	sprctl &= ~SPRITE_RGB_ORDER_RGBX;
> +	sprctl &= ~SPRITE_RGB_ORDER_XBGR;
Are you sure about this? Where is the #define for _XBGR?

>  	sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
>  	sprctl &= ~SPRITE_TILED;
>  
>  	switch (fb->pixel_format) {
>  	case DRM_FORMAT_XBGR8888:
> -		sprctl |= SPRITE_FORMAT_RGBX888;
> +		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
>  		pixel_size = 4;
>  		break;
>  	case DRM_FORMAT_XRGB8888:
> -		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
> +		sprctl |= SPRITE_FORMAT_RGBX888;
>  		pixel_size = 4;
>  		break;
>  	case DRM_FORMAT_YUYV:

-- 
- Antti

Re: [PATCH v2] drm/i915: fix color order for BGR formats on IVB

[Vijay Purushothaman]

On 8/22/2012 6:30 PM, Antti Koskipää wrote:
> Hi,
>
> On 08/22/12 12:17, Vijay Purushothaman wrote:
>> This is already fixed for ILK and SNB in the below commit but somehow
>> IVB is missed.
>>
>> commit ab2f9df10dd955f1fc0a8650e377588c98f1c029
>> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
>> Date:   Mon Feb 27 12:40:10 2012 -0800
>>
>>      drm/i915: fix color order for BGR formats on SNB
>>
>> Had the wrong bits and field definitions.
>>
>> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
>> Signed-off-by: Ben Lin <ben.y.lin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_sprite.c |    6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> index cc8df4d..6045a01 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -54,17 +54,17 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
>>
>>   	/* Mask out pixel format bits in case we change it */
>>   	sprctl &= ~SPRITE_PIXFORMAT_MASK;
>> -	sprctl &= ~SPRITE_RGB_ORDER_RGBX;
>> +	sprctl &= ~SPRITE_RGB_ORDER_XBGR;
> Are you sure about this? Where is the #define for _XBGR?
>

Thanks for the catch. I assumed SPRITE_RGB_ORDER_XBGR as defined similar 
to DVS_RGB_ORDER_XBGR for SNB. The original code snippet is correct.

>>   	sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
>>   	sprctl &= ~SPRITE_TILED;
>>
>>   	switch (fb->pixel_format) {
>>   	case DRM_FORMAT_XBGR8888:
>> -		sprctl |= SPRITE_FORMAT_RGBX888;
>> +		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
>>   		pixel_size = 4;
>>   		break;
>>   	case DRM_FORMAT_XRGB8888:
>> -		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
>> +		sprctl |= SPRITE_FORMAT_RGBX888;
>>   		pixel_size = 4;
>>   		break;
>>   	case DRM_FORMAT_YUYV:
>