Re: [PATCH 2/6] clk: exynos5410: register clocks using common clock framework

[Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>]

Hi,

On Tuesday, October 01, 2013 08:17:03 PM Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran <t.dakhran@samsung.com>
> 
> The EXYNOS5410 clocks are statically listed and registered
> using the Samsung specific common clock helper functions.
> 
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
>  .../devicetree/bindings/clock/exynos5410-clock.txt |  72 ++++++
>  drivers/clk/samsung/Makefile                       |   1 +
>  drivers/clk/samsung/clk-exynos5410.c               | 274 +++++++++++++++++++++
>  3 files changed, 347 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>  create mode 100644 drivers/clk/samsung/clk-exynos5410.c
> 
> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> new file mode 100644
> index 0000000..8c3a7c2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> @@ -0,0 +1,72 @@
> +* Samsung Exynos5410 Clock Controller
> +
> +The Exynos5410 clock controller generates and supplies clock to various
> +controllers within the Exynos5410 SoC.
> +
> +Required Properties:
> +
> +- comptible: should be one of the following.
> +  - "samsung,exynos5410-clock" - controller compatible with Exynos5410 SoC.
> +
> +- reg: physical base address of the controller and length of memory mapped
> +  region.
> +
> +- #clock-cells: should be 1.
> +
> +The following is the list of clocks generated by the controller. Each clock is
> +assigned an identifier and client nodes use this identifier to specify the
> +clock which they consume.
> +
> +
> +       [Core Clocks]
> +
> +  Clock			ID
> +  ----------------------------
> +
> +  fin_pll		1
> +
> +  [Clock Gate for Special Clocks]
> +
> +  Clock			ID
> +  ----------------------------
> +  sclk_uart0		128
> +  sclk_uart1		129
> +  sclk_uart2		130
> +  sclk_uart3		131
> +  sclk_mmc0		132
> +  sclk_mmc1		133
> +  sclk_mmc2		134
> +
> +   [Peripheral Clock Gates]
> +
> +  Clock			ID
> +  ----------------------------
> +
> +  uart0			257
> +  uart1			258
> +  uart2			259
> +  uart3			260
> +  mct			315
> +  mmc0			351
> +  mmc1			352
> +  mmc2			353
> +
> +Example 1: An example of a clock controller node is listed below.
> +
> +	clock: clock-controller@0x10010000 {
> +		compatible = "samsung,exynos5410-clock";
> +		reg = <0x10010000 0x30000>;
> +		#clock-cells = <1>;
> +	};
> +
> +Example 2: UART controller node that consumes the clock generated by the clock
> +	   controller. Refer to the standard clock bindings for information
> +	   about 'clocks' and 'clock-names' property.
> +
> +	serial@13820000 {
> +		compatible = "samsung,exynos4210-uart";
> +		reg = <0x13820000 0x100>;
> +		interrupts = <0 54 0>;
> +		clocks = <&clock 259>, <&clock 130>;
> +		clock-names = "uart", "clk_uart_baud0";
> +	};
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index 3413380..5a446ca 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -5,6 +5,7 @@
>  obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
>  obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
>  obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
> +obj-$(CONFIG_SOC_EXYNOS5410)	+= clk-exynos5410.o
>  obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o
>  obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
>  obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-audss.o
> diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
> new file mode 100644
> index 0000000..a5d6cac
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos5410.c
> @@ -0,0 +1,274 @@
> +/*
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * Author: Tarek Dakhran <t.dakhran@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Common Clock Framework support for Exynos5410 SoC.
> +*/
> +
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +
> +#include "clk.h"
> +#include "clk-pll.h"
> +
> +#define SRC_CPU			0x200
> +#define DIV_CPU0		0x500
> +#define SRC_CPERI1		0x4204
> +#define DIV_TOP0		0x10510
> +#define DIV_TOP1		0x10514
> +#define DIV_FSYS1		0x1054c
> +#define DIV_FSYS2		0x10550
> +#define DIV_PERIC0		0x10558
> +#define SRC_TOP0		0x10210
> +#define SRC_TOP1		0x10214
> +#define SRC_TOP2		0x10218
> +#define SRC_FSYS		0x10244
> +#define SRC_PERIC0		0x10250
> +#define SRC_MASK_FSYS		0x10340
> +#define SRC_MASK_PERIC0		0x10350
> +#define GATE_BUS_FSYS0		0x10740
> +#define GATE_IP_FSYS		0x10944
> +#define GATE_IP_PERIC		0x10950
> +#define GATE_IP_PERIS		0x10960
> +#define SRC_CDREX		0x20200
> +#define SRC_KFC			0x28200
> +#define DIV_KFC0		0x28500
> +
> +/* list of PLLs */
> +enum exynos5420_plls {
> +	apll, cpll, mpll,
> +	bpll, kpll,
> +	nr_plls			/* number of PLLs */
> +};
> +
> +enum exynos5410_clks {
> +	none,
> +
> +	/* core clocks */
> +	fin_pll, fout_apll, fout_cpll, fout_mpll, fout_bpll, fout_kpll,
> +
> +	/* gate for special clocks (sclk) */
> +	sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
> +	sclk_mmc1, sclk_mmc2,
> +
> +	/* gate clocks */
> +	aclk66_peric = 256, uart0, uart1, uart2, uart3,
> +	mct = 315,
> +	sdmmc0 = 351, sdmmc1, sdmmc2,
> +
> +	nr_clks,
> +};

All other EXYNOS clock drivers have been recently converted to use macros
instead of magic numbers/enums to describe clock bindings.

Please take a look at:

http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg22376.html

and convert your code accordingly.

> +/*
> + * list of controller registers to be saved and restored during a
> + * suspend/resume cycle.
> + */
> +
> +static unsigned long exynos5410_clk_regs[] __initdata = {
> +	SRC_CPU,
> +	DIV_CPU0,
> +	SRC_CPERI1,
> +	DIV_TOP0,
> +	DIV_TOP1,
> +	DIV_FSYS1,
> +	DIV_FSYS2,
> +	DIV_PERIC0,
> +	SRC_TOP0,
> +	SRC_TOP1,
> +	SRC_TOP2,
> +	SRC_FSYS,
> +	SRC_PERIC0,
> +	SRC_MASK_FSYS,
> +	SRC_MASK_PERIC0,
> +	GATE_BUS_FSYS0,
> +	GATE_IP_FSYS,
> +	GATE_IP_PERIC,
> +	GATE_IP_PERIS,
> +	SRC_CDREX,
> +	SRC_KFC,
> +	DIV_KFC0,
> +};
> +
> +/* list of all parent clocks */
> +
> +PNAME(apll_p)		= { "fin_pll", "fout_apll", };
> +PNAME(bpll_p)		= { "fin_pll", "fout_bpll", };
> +PNAME(cpll_p)		= { "fin_pll", "fout_cpll" };
> +PNAME(mpll_p)		= { "fin_pll", "fout_mpll", };
> +PNAME(kpll_p)		= { "fin_pll", "fout_kpll", };
> +
> +PNAME(mout_cpu_p)	= { "mout_apll", "sclk_mpll", };
> +PNAME(mout_kfc_p)	= { "mout_kpll", "sclk_mpll", };
> +
> +PNAME(mpll_user_p)	= { "fin_pll", "sclk_mpll", };
> +PNAME(bpll_user_p)	= { "fin_pll", "sclk_bpll", };
> +PNAME(mpll_bpll_p)	= { "sclk_mpll_muxed", "sclk_bpll_muxed", };
> +
> +
> +
> +PNAME(group_main)	= {	"fin_pll", "fin_pll",
> +				"sclk_hdmi27m", "sclk_dptxphty",
> +				"sclk_usbhost20phy", "sclk_hdmiphy",
> +				"sclk_mpll_bpll", "sclk_epll",
> +				"sclk_vpll", "sclk_cpll" };
> +
> +/* fixed rate clocks generated outside the soc */
> +struct samsung_fixed_rate_clock exynos5410_fixed_rate_ext_clks[] __initdata = {
> +	FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
> +};
> +
> +struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
> +	MUX_A(none, "mout_apll", apll_p, SRC_CPU, 0, 1, "mout_apll"),
> +	MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
> +
> +	MUX_A(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1, "mout_kpll"),
> +	MUX_A(none, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1, "mout_kfc"),
> +
> +	MUX(none, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
> +	MUX(none, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
> +
> +	MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
> +	MUX(none, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
> +
> +	MUX(none, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
> +
> +	MUX(none, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
> +
> +	MUX(none, "mout_mmc0", group_main, SRC_FSYS, 0, 4),
> +	MUX(none, "mout_mmc1", group_main, SRC_FSYS, 4, 4),
> +	MUX(none, "mout_mmc2", group_main, SRC_FSYS, 8, 4),
> +
> +	MUX(none, "mout_uart0", group_main, SRC_PERIC0, 0, 4),
> +	MUX(none, "mout_uart1", group_main, SRC_PERIC0, 4, 4),
> +	MUX(none, "mout_uart2", group_main, SRC_PERIC0, 8, 4),
> +
> +	MUX(none, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
> +	MUX(none, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
> +};
> +
> +struct samsung_div_clock exynos5410_div_clks[] __initdata = {
> +
> +	DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
> +	DIV(none, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
> +
> +	DIV_A(none, "div_acp", "div_arm2", DIV_CPU0, 8, 3, "cpu_arm_clk"),
> +	DIV_A(none, "div_cpud", "div_arm2", DIV_CPU0, 4, 3, "cpu_aclk_cpud"),
> +	DIV_A(none, "div_atb", "div_arm2", DIV_CPU0, 16, 3, "cpu_atclk"),
> +	DIV_A(none, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3, "cpu_pclk_dbg"),
> +
> +
> +	DIV_A(none, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3, "kfc_arm_clk"),
> +	DIV_A(none, "div_aclk", "div_kfc", DIV_KFC0, 4, 3, "kfc_aclk_cpud"),
> +	DIV_A(none, "div_pclk", "div_kfc", DIV_KFC0, 20, 3, "kfc_pclk_dbg"),
> +
> +
> +	DIV(none, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
> +	DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
> +
> +	DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
> +	DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
> +	DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
> +
> +	DIV_F(none, "div_mmc_pre0", "div_mmc0",
> +			DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
> +	DIV_F(none, "div_mmc_pre1", "div_mmc1",
> +			DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
> +	DIV_F(none, "div_mmc_pre2", "div_mmc2",
> +			DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
> +
> +	DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
> +	DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
> +	DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
> +	DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
> +
> +	DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
> +	DIV(none, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
> +};
> +
> +struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
> +
> +	GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
> +
> +	GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0",
> +			SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
> +	GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1",
> +			SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
> +	GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2",
> +			SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
> +
> +	GATE(sdmmc0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
> +	GATE(sdmmc1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
> +	GATE(sdmmc2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
> +
> +	GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
> +	GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
> +	GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
> +
> +	GATE(sclk_uart0, "sclk_uart0", "div_uart0",
> +			SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
> +	GATE(sclk_uart1, "sclk_uart1", "div_uart1",
> +			SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
> +	GATE(sclk_uart2, "sclk_uart2", "div_uart2",
> +			SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
> +
> +};
> +
> +static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
> +	[apll] = PLL(pll_35xx, fout_apll, "fout_apll", "fin_pll", 0x0,
> +		0x100, NULL),
> +	[cpll] = PLL(pll_35xx, fout_mpll, "fout_cpll", "fin_pll", 0x10020,
> +		0x10120, NULL),
> +	[mpll] = PLL(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", 0x4000,
> +		0x4100, NULL),
> +	[bpll] = PLL(pll_35xx, fout_bpll, "fout_bpll", "fin_pll", 0x20010,
> +		0x20110, NULL),
> +	[kpll] = PLL(pll_35xx, fout_kpll, "fout_kpll", "fin_pll", 0x28000,
> +		0x28100, NULL),
> +};
> +
> +static struct of_device_id ext_clk_match[] __initdata = {
> +	{ .compatible = "samsung,exynos5410-oscclk", .data = (void *)0, },
> +	{ },
> +};
> +
> +DEFINE_SPINLOCK(int_div_lock);

this is unused currently

> +/* register exynos5410 clocks */
> +void __init exynos5410_clk_init(struct device_node *np)

static?

> +{
> +	void __iomem *reg_base;
> +
> +	if (np) {
> +		reg_base = of_iomap(np, 0);
> +		if (!reg_base)
> +			panic("%s: failed to map registers\n", __func__);
> +	} else {
> +		panic("%s: unable to determine soc\n", __func__);
> +	}
> +
> +	samsung_clk_init(np, reg_base, nr_clks,
> +			exynos5410_clk_regs, ARRAY_SIZE(exynos5410_clk_regs),
> +			NULL, 0);
> +	samsung_clk_of_register_fixed_ext(exynos5410_fixed_rate_ext_clks,
> +			ARRAY_SIZE(exynos5410_fixed_rate_ext_clks),
> +			ext_clk_match);
> +	samsung_clk_register_pll(exynos5410_plls, ARRAY_SIZE(exynos5410_plls),
> +					reg_base);
> +
> +	samsung_clk_register_mux(exynos5410_mux_clks,
> +			ARRAY_SIZE(exynos5410_mux_clks));
> +	samsung_clk_register_div(exynos5410_div_clks,
> +			ARRAY_SIZE(exynos5410_div_clks));
> +	samsung_clk_register_gate(exynos5410_gate_clks,
> +			ARRAY_SIZE(exynos5410_gate_clks));
> +
> +	pr_info("Exynos5410: clock setup completed.\n");
> +}
> +CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics