From: Avi Kivity <avi@redhat.com>
To: "Li, Jiongxi" <jiongxi.li@intel.com>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>
Subject: Re: [PATCH 2/5]KVM:x86, apicv: adjust for virtual interrupt delivery
Date: Thu, 06 Sep 2012 19:22:17 +0300 [thread overview]
Message-ID: <5048CDB9.4040202@redhat.com> (raw)
In-Reply-To: <D9137FCD9CFF644B965863BCFBEDABB877AC53@SHSMSX101.ccr.corp.intel.com>
On 09/05/2012 08:41 AM, Li, Jiongxi wrote:
> Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
> manually, which is fully taken care of by the hardware. This needs
> some special awareness into existing interrupr injection path:
>
> - for pending interrupt, instead of direct injection, we may need
> update architecture specific indicators before resuming to guest.
>
> - A pending interrupt, which is masked by ISR, should be also
> considered in above update action, since hardware will decide
> when to inject it at right time. Current has_interrupt and
> get_interrupt only returns a valid vector from injection p.o.v.
>
>
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -5194,6 +5194,13 @@ static void inject_pending_event(struct kvm_vcpu *vcpu)
> vcpu->arch.nmi_injected = true;
> kvm_x86_ops->set_nmi(vcpu);
> }
> + } else if (kvm_apic_vid_enabled(vcpu)) {
> + if (kvm_cpu_has_interrupt_apic_vid(vcpu) &&
> + kvm_x86_ops->interrupt_allowed(vcpu)) {
> + kvm_queue_interrupt(vcpu,
> + kvm_cpu_get_interrupt_apic_vid(vcpu), false);
> + kvm_x86_ops->set_irq(vcpu);
> + }
It may be simpler to change kvm_cpu_{has,get}_interrupt to ignore the
apic if virtual interrupt delivery is enabled.
> @@ -5293,16 +5300,27 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
> }
>
> if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
> + /* update archtecture specific hints for APIC virtual interrupt delivery */
> + if (kvm_apic_vid_enabled(vcpu))
> + kvm_x86_ops->update_irq(vcpu);
> +
Not defined.
> inject_pending_event(vcpu);
>
> /* enable NMI/IRQ window open exits if needed */
> if (vcpu->arch.nmi_pending)
> kvm_x86_ops->enable_nmi_window(vcpu);
> - else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
> + else if (kvm_apic_vid_enabled(vcpu)) {
> + if (kvm_cpu_has_interrupt_apic_vid(vcpu))
> + kvm_x86_ops->enable_irq_window(vcpu);
> + } else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
> kvm_x86_ops->enable_irq_window(vcpu);
>
> if (kvm_lapic_enabled(vcpu)) {
> - update_cr8_intercept(vcpu);
> + /* no need for tpr_threshold update if APIC virtual
> + * interrupt delivery is enabled
> + */
> + if (!kvm_apic_vid_enabled(vcpu))
> + update_cr8_intercept(vcpu);
Perhaps the arch function should do the ignoring.
> kvm_lapic_sync_to_vapic(vcpu);
> }
> }
>
--
error compiling committee.c: too many arguments to function
next prev parent reply other threads:[~2012-09-06 16:22 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-05 5:41 [PATCH 2/5]KVM:x86, apicv: adjust for virtual interrupt delivery Li, Jiongxi
2012-09-06 16:22 ` Avi Kivity [this message]
2012-09-14 14:15 ` Li, Jiongxi
2012-09-19 14:53 ` Avi Kivity
2012-09-17 11:28 ` Li, Jiongxi
2012-09-19 15:19 ` Avi Kivity
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5048CDB9.4040202@redhat.com \
--to=avi@redhat.com \
--cc=jiongxi.li@intel.com \
--cc=kvm@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.