[PATCH] mips/octeon: 16-Bit NOR flash was not being detected during boot

[PATCH] mips/octeon: 16-Bit NOR flash was not being detected during boot

[Charles Hardin]

The cavium code assumed that all NOR on the boot bus was
an 8-bit NOR part and hardcoded the bankwidth. The simple
solution was to add the code that queries the configuration
register for the width of the bus that has been hardware strapped
to the Cavium. This allows both 8-bit and 16-bit parts to be
discovered during boot.

Signed-off-by: Charles Hardin <ckhardin@exablox.com>

diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c
index e44a55b..9e46976 100644
--- a/arch/mips/cavium-octeon/flash_setup.c
+++ b/arch/mips/cavium-octeon/flash_setup.c
@@ -51,7 +51,17 @@ static int __init flash_init(void)
 		flash_map.name = "phys_mapped_flash";
 		flash_map.phys = region_cfg.s.base << 16;
 		flash_map.size = 0x1fc00000 - flash_map.phys;
-		flash_map.bankwidth = 1;
+		switch (region_cfg.s.width) {
+		default:
+		case 0:
+			/* 8-bit bus */
+			flash_map.bankwidth = 1;
+			break;
+		case 1:
+			/* 16-bit bus */
+			flash_map.bankwidth = 2;
+			break;
+		}
 		flash_map.virt = ioremap(flash_map.phys, flash_map.size);
 		pr_notice("Bootbus flash: Setting flash for %luMB flash at "
 			  "0x%08llx\n", flash_map.size >> 20, flash_map.phys);

[PATCH] mips/octeon: 16-Bit NOR flash was not being detected during boot

[Charles Hardin]

The cavium code assumed that all NOR on the boot bus was
an 8-bit NOR part and hardcoded the bankwidth. The simple
solution was to add the code that queries the configuration
register for the width of the bus that has been hardware strapped
to the Cavium. This allows both 8-bit and 16-bit parts to be
discovered during boot.

Acked-by: David Daney <david.daney@cavium.com>
Signed-off-by: Charles Hardin <ckhardin@exablox.com>

diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c
index e44a55b..237e5b1 100644
--- a/arch/mips/cavium-octeon/flash_setup.c
+++ b/arch/mips/cavium-octeon/flash_setup.c
@@ -51,7 +51,8 @@ static int __init flash_init(void)
 		flash_map.name = "phys_mapped_flash";
 		flash_map.phys = region_cfg.s.base << 16;
 		flash_map.size = 0x1fc00000 - flash_map.phys;
-		flash_map.bankwidth = 1;
+		/* 8-bit bus (0 + 1) or 16-bit bus (1 + 1) */
+		flash_map.bankwidth = region_cfg.s.width + 1;
 		flash_map.virt = ioremap(flash_map.phys, flash_map.size);
 		pr_notice("Bootbus flash: Setting flash for %luMB flash at "
 			  "0x%08llx\n", flash_map.size >> 20, flash_map.phys);

Re: [PATCH] mips/octeon: 16-Bit NOR flash was not being detected during boot

[David Daney]

On 09/05/2012 06:54 AM, Charles Hardin wrote:
> The cavium code assumed that all NOR on the boot bus was
> an 8-bit NOR part and hardcoded the bankwidth. The simple
> solution was to add the code that queries the configuration
> register for the width of the bus that has been hardware strapped
> to the Cavium. This allows both 8-bit and 16-bit parts to be
> discovered during boot.
>
> Signed-off-by: Charles Hardin <ckhardin@exablox.com>
>
> diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c
> index e44a55b..9e46976 100644
> --- a/arch/mips/cavium-octeon/flash_setup.c
> +++ b/arch/mips/cavium-octeon/flash_setup.c
> @@ -51,7 +51,17 @@ static int __init flash_init(void)
>   		flash_map.name = "phys_mapped_flash";
>   		flash_map.phys = region_cfg.s.base << 16;
>   		flash_map.size = 0x1fc00000 - flash_map.phys;
> -		flash_map.bankwidth = 1;
> +		switch (region_cfg.s.width) {
> +		default:
> +		case 0:
> +			/* 8-bit bus */
> +			flash_map.bankwidth = 1;
> +			break;
> +		case 1:
> +			/* 16-bit bus */
> +			flash_map.bankwidth = 2;
> +			break;
> +		}

A slightly less verbose version of this would be:

-       flash_map.bankwidth = 1;
+       flash_map.bankwidth = region_cfg.s.width + 1;


Can you test that instead?

If it works, Acked-by me.

David Daney