From: David Daney <ddaney.cavm@gmail.com>
To: "Steven J. Hill" <sjhill@mips.com>, ralf@linux-mips.org
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH 0/2] Add RI and XI bits to MIPS base architecture.
Date: Wed, 12 Sep 2012 10:47:24 -0700 [thread overview]
Message-ID: <5050CAAC.1090600@gmail.com> (raw)
In-Reply-To: <1347469309-11468-1-git-send-email-sjhill@mips.com>
On 09/12/2012 10:01 AM, Steven J. Hill wrote:
> From: "Steven J. Hill" <sjhill@mips.com>
>
> Add MIPSr3(TM) base architecture TLB support for Read Inhibit (RI)
> and Execute Inhibit (XI) page protection. SmartMIPS cores will not
> notice any change in functionality.
>
> This patchset obsoletes the previous patchset with four commits.
>
> Signed-off-by: Steven J. Hill <sjhill@mips.com>
FWIW: I haven't tested it, but the entire set ...
Acked-by: David Daney <david.daney@cavium.com>
>
> Steven J. Hill (2):
> MIPS: Add base architecture support for RI and XI.
> MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
>
> arch/mips/include/asm/cpu-features.h | 4 ++--
> arch/mips/include/asm/cpu.h | 1 +
> .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 2 +-
> arch/mips/include/asm/mipsregs.h | 1 +
> arch/mips/include/asm/pgtable-bits.h | 18 +++++++++---------
> arch/mips/include/asm/pgtable.h | 12 ++++++------
> arch/mips/kernel/cpu-probe.c | 6 +++++-
> arch/mips/mm/cache.c | 2 +-
> arch/mips/mm/fault.c | 2 +-
> arch/mips/mm/tlb-r4k.c | 2 +-
> arch/mips/mm/tlbex.c | 14 +++++++-------
> 11 files changed, 35 insertions(+), 29 deletions(-)
>
prev parent reply other threads:[~2012-09-12 17:47 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-12 17:01 [PATCH 0/2] Add RI and XI bits to MIPS base architecture Steven J. Hill
2012-09-12 17:01 ` [PATCH 1/2] MIPS: Add base architecture support for RI and XI Steven J. Hill
2012-09-12 17:01 ` [PATCH 2/2] MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi' Steven J. Hill
2012-09-12 17:47 ` David Daney [this message]
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