* [PATCH 0/2] Add RI and XI bits to MIPS base architecture.
@ 2012-09-12 17:01 Steven J. Hill
2012-09-12 17:01 ` [PATCH 1/2] MIPS: Add base architecture support for RI and XI Steven J. Hill
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Steven J. Hill @ 2012-09-12 17:01 UTC (permalink / raw)
To: linux-mips; +Cc: Steven J. Hill, ralf
From: "Steven J. Hill" <sjhill@mips.com>
Add MIPSr3(TM) base architecture TLB support for Read Inhibit (RI)
and Execute Inhibit (XI) page protection. SmartMIPS cores will not
notice any change in functionality.
This patchset obsoletes the previous patchset with four commits.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Steven J. Hill (2):
MIPS: Add base architecture support for RI and XI.
MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
arch/mips/include/asm/cpu-features.h | 4 ++--
arch/mips/include/asm/cpu.h | 1 +
.../asm/mach-cavium-octeon/cpu-feature-overrides.h | 2 +-
arch/mips/include/asm/mipsregs.h | 1 +
arch/mips/include/asm/pgtable-bits.h | 18 +++++++++---------
arch/mips/include/asm/pgtable.h | 12 ++++++------
arch/mips/kernel/cpu-probe.c | 6 +++++-
arch/mips/mm/cache.c | 2 +-
arch/mips/mm/fault.c | 2 +-
arch/mips/mm/tlb-r4k.c | 2 +-
arch/mips/mm/tlbex.c | 14 +++++++-------
11 files changed, 35 insertions(+), 29 deletions(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] MIPS: Add base architecture support for RI and XI.
2012-09-12 17:01 [PATCH 0/2] Add RI and XI bits to MIPS base architecture Steven J. Hill
@ 2012-09-12 17:01 ` Steven J. Hill
2012-09-12 17:01 ` [PATCH 2/2] MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi' Steven J. Hill
2012-09-12 17:47 ` [PATCH 0/2] Add RI and XI bits to MIPS base architecture David Daney
2 siblings, 0 replies; 4+ messages in thread
From: Steven J. Hill @ 2012-09-12 17:01 UTC (permalink / raw)
To: linux-mips; +Cc: Steven J. Hill, ralf
From: "Steven J. Hill" <sjhill@mips.com>
Originally both Read Inhibit (RI) and Execute Inhibit (XI) were
supported by the TLB only for a SmartMIPS core. The MIPSr3(TM)
Architecture now defines an optional feature to implement these
TLB bits separately. Support for one or both features can be
checked by looking at the Config3.RXI bit.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
---
arch/mips/include/asm/cpu-features.h | 3 +++
arch/mips/include/asm/cpu.h | 1 +
arch/mips/include/asm/mipsregs.h | 1 +
arch/mips/kernel/cpu-probe.c | 6 +++++-
4 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index bba9398..232cb1e 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -95,6 +95,9 @@
#ifndef cpu_has_smartmips
#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
#endif
+#ifndef cpu_has_rixi
+#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
+#endif
#ifndef kernel_uses_smartmips_rixi
#define kernel_uses_smartmips_rixi 0
#endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 4889fae..f3150f6 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -323,6 +323,7 @@ enum cpu_type_enum {
#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
+#define MIPS_CPU_RIXI 0x02000000 /* CPU has TLB Read/eXec Inhibit */
/*
* CPU ASE encodings
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index cdb9c87..19430fb 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -591,6 +591,7 @@
#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
+#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 009fc13..b63732c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -422,8 +422,12 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
config3 = read_c0_config3();
- if (config3 & MIPS_CONF3_SM)
+ if (config3 & MIPS_CONF3_SM) {
c->ases |= MIPS_ASE_SMARTMIPS;
+ c->options |= MIPS_CPU_RIXI;
+ }
+ if (config3 & MIPS_CONF3_RXI)
+ c->options |= MIPS_CPU_RIXI;
if (config3 & MIPS_CONF3_DSP)
c->ases |= MIPS_ASE_DSP;
if (config3 & MIPS_CONF3_DSP2P)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
2012-09-12 17:01 [PATCH 0/2] Add RI and XI bits to MIPS base architecture Steven J. Hill
2012-09-12 17:01 ` [PATCH 1/2] MIPS: Add base architecture support for RI and XI Steven J. Hill
@ 2012-09-12 17:01 ` Steven J. Hill
2012-09-12 17:47 ` [PATCH 0/2] Add RI and XI bits to MIPS base architecture David Daney
2 siblings, 0 replies; 4+ messages in thread
From: Steven J. Hill @ 2012-09-12 17:01 UTC (permalink / raw)
To: linux-mips; +Cc: Steven J. Hill, ralf
From: "Steven J. Hill" <sjhill@mips.com>
Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files
and use new 'cpu_has_rixi' instead.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
---
arch/mips/include/asm/cpu-features.h | 3 ---
.../asm/mach-cavium-octeon/cpu-feature-overrides.h | 2 +-
arch/mips/include/asm/pgtable-bits.h | 18 +++++++++---------
arch/mips/include/asm/pgtable.h | 12 ++++++------
arch/mips/mm/cache.c | 2 +-
arch/mips/mm/fault.c | 2 +-
arch/mips/mm/tlb-r4k.c | 2 +-
arch/mips/mm/tlbex.c | 14 +++++++-------
8 files changed, 26 insertions(+), 29 deletions(-)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 232cb1e..5a65870 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -98,9 +98,6 @@
#ifndef cpu_has_rixi
#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
#endif
-#ifndef kernel_uses_smartmips_rixi
-#define kernel_uses_smartmips_rixi 0
-#endif
#ifndef cpu_has_mmips
#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index a58addb..375ad0c 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -58,7 +58,7 @@
#define cpu_has_veic 0
#define cpu_hwrena_impl_bits 0xc0000000
-#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
+#define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
#define ARCH_HAS_IRQ_PER_CPU 1
#define ARCH_HAS_SPINLOCK_PREFETCH 1
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index e9fe7e9..2f99313 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -79,9 +79,9 @@
/* implemented in software */
#define _PAGE_PRESENT_SHIFT (0)
#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
-/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */
-#define _PAGE_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
-#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; })
+/* implemented in software, should be unused if cpu_has_rixi. */
+#define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ ({if (cpu_has_rixi) BUG(); 1 << _PAGE_READ_SHIFT; })
/* implemented in software */
#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
@@ -104,12 +104,12 @@
#endif
/* Page cannot be executed */
-#define _PAGE_NO_EXEC_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
-#define _PAGE_NO_EXEC ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; })
+#define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
+#define _PAGE_NO_EXEC ({if (!cpu_has_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; })
/* Page cannot be read */
-#define _PAGE_NO_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
-#define _PAGE_NO_READ ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; })
+#define _PAGE_NO_READ_SHIFT (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
+#define _PAGE_NO_READ ({if (!cpu_has_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; })
#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
@@ -155,7 +155,7 @@
*/
static inline uint64_t pte_to_entrylo(unsigned long pte_val)
{
- if (kernel_uses_smartmips_rixi) {
+ if (cpu_has_rixi) {
int sa;
#ifdef CONFIG_32BIT
sa = 31 - _PAGE_NO_READ_SHIFT;
@@ -220,7 +220,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#endif
-#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ))
+#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index b2202a6..c02158b 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -22,15 +22,15 @@ struct mm_struct;
struct vm_area_struct;
#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
-#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
+#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_rixi ? 0 : _PAGE_READ) | \
_page_cachable_default)
-#define PAGE_COPY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
- (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default)
-#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
+#define PAGE_COPY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \
+ (cpu_has_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default)
+#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \
_page_cachable_default)
#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
_PAGE_GLOBAL | _page_cachable_default)
-#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \
+#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \
_page_cachable_default)
#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
__WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
@@ -299,7 +299,7 @@ static inline pte_t pte_mkdirty(pte_t pte)
static inline pte_t pte_mkyoung(pte_t pte)
{
pte_val(pte) |= _PAGE_ACCESSED;
- if (kernel_uses_smartmips_rixi) {
+ if (cpu_has_rixi) {
if (!(pte_val(pte) & _PAGE_NO_READ))
pte_val(pte) |= _PAGE_SILENT_READ;
} else {
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index ff910a1..d449d9a 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -183,7 +183,7 @@ EXPORT_SYMBOL(_page_cachable_default);
static inline void setup_protection_map(void)
{
- if (kernel_uses_smartmips_rixi) {
+ if (cpu_has_rixi) {
protection_map[0] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC);
protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index c14f6df..7a19957 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -114,7 +114,7 @@ good_area:
if (!(vma->vm_flags & VM_WRITE))
goto bad_area;
} else {
- if (kernel_uses_smartmips_rixi) {
+ if (cpu_has_rixi) {
if (address == regs->cp0_epc && !(vma->vm_flags & VM_EXEC)) {
#if 0
pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] XI violation\n",
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index d2572cb..87b9cfc 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -401,7 +401,7 @@ void __cpuinit tlb_init(void)
current_cpu_type() == CPU_R14000)
write_c0_framemask(0);
- if (kernel_uses_smartmips_rixi) {
+ if (cpu_has_rixi) {
/*
* Enable the no read, no exec bits, and enable large virtual
* address.
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 202908e..542dae1 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -601,7 +601,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
unsigned int reg)
{
- if (kernel_uses_smartmips_rixi) {
+ if (cpu_has_rixi) {
UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
} else {
@@ -1021,7 +1021,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
if (cpu_has_64bits) {
uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
- if (kernel_uses_smartmips_rixi) {
+ if (cpu_has_rixi) {
UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
@@ -1048,7 +1048,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
if (r45k_bvahwbug())
build_tlb_probe_entry(p);
- if (kernel_uses_smartmips_rixi) {
+ if (cpu_has_rixi) {
UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
@@ -1214,7 +1214,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
UASM_i_LW(p, even, 0, ptr); /* get even pte */
UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
}
- if (kernel_uses_smartmips_rixi) {
+ if (cpu_has_rixi) {
uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_NO_EXEC));
uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_NO_EXEC));
uasm_i_drotr(p, even, even,
@@ -1576,7 +1576,7 @@ build_pte_present(u32 **p, struct uasm_reloc **r,
{
int t = scratch >= 0 ? scratch : pte;
- if (kernel_uses_smartmips_rixi) {
+ if (cpu_has_rixi) {
if (use_bbit_insns()) {
uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
uasm_i_nop(p);
@@ -1906,7 +1906,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
if (m4kc_tlbp_war())
build_tlb_probe_entry(&p);
- if (kernel_uses_smartmips_rixi) {
+ if (cpu_has_rixi) {
/*
* If the page is not _PAGE_VALID, RI or XI could not
* have triggered it. Skip the expensive test..
@@ -1960,7 +1960,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
build_tlb_probe_entry(&p);
- if (kernel_uses_smartmips_rixi) {
+ if (cpu_has_rixi) {
/*
* If the page is not _PAGE_VALID, RI or XI could not
* have triggered it. Skip the expensive test..
--
1.7.9.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 0/2] Add RI and XI bits to MIPS base architecture.
2012-09-12 17:01 [PATCH 0/2] Add RI and XI bits to MIPS base architecture Steven J. Hill
2012-09-12 17:01 ` [PATCH 1/2] MIPS: Add base architecture support for RI and XI Steven J. Hill
2012-09-12 17:01 ` [PATCH 2/2] MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi' Steven J. Hill
@ 2012-09-12 17:47 ` David Daney
2 siblings, 0 replies; 4+ messages in thread
From: David Daney @ 2012-09-12 17:47 UTC (permalink / raw)
To: Steven J. Hill, ralf; +Cc: linux-mips
On 09/12/2012 10:01 AM, Steven J. Hill wrote:
> From: "Steven J. Hill" <sjhill@mips.com>
>
> Add MIPSr3(TM) base architecture TLB support for Read Inhibit (RI)
> and Execute Inhibit (XI) page protection. SmartMIPS cores will not
> notice any change in functionality.
>
> This patchset obsoletes the previous patchset with four commits.
>
> Signed-off-by: Steven J. Hill <sjhill@mips.com>
FWIW: I haven't tested it, but the entire set ...
Acked-by: David Daney <david.daney@cavium.com>
>
> Steven J. Hill (2):
> MIPS: Add base architecture support for RI and XI.
> MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
>
> arch/mips/include/asm/cpu-features.h | 4 ++--
> arch/mips/include/asm/cpu.h | 1 +
> .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 2 +-
> arch/mips/include/asm/mipsregs.h | 1 +
> arch/mips/include/asm/pgtable-bits.h | 18 +++++++++---------
> arch/mips/include/asm/pgtable.h | 12 ++++++------
> arch/mips/kernel/cpu-probe.c | 6 +++++-
> arch/mips/mm/cache.c | 2 +-
> arch/mips/mm/fault.c | 2 +-
> arch/mips/mm/tlb-r4k.c | 2 +-
> arch/mips/mm/tlbex.c | 14 +++++++-------
> 11 files changed, 35 insertions(+), 29 deletions(-)
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2012-09-12 17:47 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-09-12 17:01 [PATCH 0/2] Add RI and XI bits to MIPS base architecture Steven J. Hill
2012-09-12 17:01 ` [PATCH 1/2] MIPS: Add base architecture support for RI and XI Steven J. Hill
2012-09-12 17:01 ` [PATCH 2/2] MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi' Steven J. Hill
2012-09-12 17:47 ` [PATCH 0/2] Add RI and XI bits to MIPS base architecture David Daney
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