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* [PATCH v3] drm/amd/display: Restore analog connector support
@ 2026-04-18  0:35 Roman.Li
  2026-04-21 18:08 ` Li, Roman
  0 siblings, 1 reply; 4+ messages in thread
From: Roman.Li @ 2026-04-18  0:35 UTC (permalink / raw)
  To: amd-gfx
  Cc: alexander.deucher, Harry.Wentland, Sunpeng.Li, Aurabindo.Pillai,
	alex.hung, Roman Li, Timur Kristóf

From: Roman Li <Roman.Li@amd.com>

[Why]
The analog connector support was accidentally removed,
causing a crash when connecting an analog monitor.

[How]
This patch restores the functions and pointers required for proper analog
and DP bridge encoder support on legacy GPUs.

V2: Restore the external encoder control functions.

V3:
 - Restore BIOS parser external encoder DAC load detection
 - Restore stream initialization and source selection changes

Fixes: 66715fc0ecfd ("drm/amd/display: Sync dcn42 with DC 3.2.373")

Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
---
 .../gpu/drm/amd/display/dc/bios/bios_parser.c | 11 ++-
 .../gpu/drm/amd/display/dc/dc_bios_types.h    |  3 +-
 .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 94 ++++++++++++-------
 3 files changed, 71 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 25c94962e141..ec75882ac477 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -794,11 +794,13 @@ static enum bp_result bios_parser_external_encoder_control(
 
 static enum bp_result bios_parser_dac_load_detection(
 	struct dc_bios *dcb,
-	enum engine_id engine_id)
+	enum engine_id engine_id,
+	struct graphics_object_id ext_enc_id)
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	struct dc_context *ctx = dcb->ctx;
 	struct bp_load_detection_parameters bp_params = {0};
+	struct bp_external_encoder_control ext_cntl = {0};
 	enum bp_result bp_result = BP_RESULT_UNSUPPORTED;
 	uint32_t bios_0_scratch;
 	uint32_t device_id_mask = 0;
@@ -824,6 +826,13 @@ static enum bp_result bios_parser_dac_load_detection(
 
 		bp_params.engine_id = engine_id;
 		bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params);
+	} else if (ext_enc_id.id) {
+		if (!bp->cmd_tbl.external_encoder_control)
+			return BP_RESULT_UNSUPPORTED;
+
+		ext_cntl.action = EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT;
+		ext_cntl.encoder_id = ext_enc_id;
+		bp_result = bp->cmd_tbl.external_encoder_control(bp, &ext_cntl);
 	}
 
 	if (bp_result != BP_RESULT_OK)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index 6f96c5cf39fe..526f71616f94 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -102,7 +102,8 @@ struct dc_vbios_funcs {
 		struct bp_external_encoder_control *cntl);
 	enum bp_result (*dac_load_detection)(
 		struct dc_bios *bios,
-		enum engine_id engine_id);
+		enum engine_id engine_id,
+		struct graphics_object_id ext_enc_id);
 	enum bp_result (*transmitter_control)(
 		struct dc_bios *bios,
 		struct bp_transmitter_control *cntl);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 7af239524d71..e6712cffeb04 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -665,16 +665,45 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 }
 
 static void
-dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable)
+dce110_external_encoder_control(enum bp_external_encoder_control_action action,
+				struct dc_link *link,
+				struct dc_crtc_timing *timing)
 {
-	struct dc_link *link = pipe_ctx->stream->link;
+	struct dc *dc = link->ctx->dc;
 	struct dc_bios *bios = link->ctx->dc_bios;
-	struct bp_encoder_control encoder_control = {0};
+	const struct dc_link_settings *link_settings = &link->cur_link_settings;
+	enum bp_result bp_result = BP_RESULT_OK;
+	struct bp_external_encoder_control ext_cntl = {
+		.action = action,
+		.connector_obj_id = link->link_enc->connector,
+		.encoder_id = link->ext_enc_id,
+		.lanes_number = link_settings->lane_count,
+		.link_rate = link_settings->link_rate,
+
+		/* Use signal type of the real link encoder, ie. DP */
+		.signal = link->connector_signal,
+
+		/* We don't know the timing yet when executing the SETUP action,
+		 * so use a reasonably high default value. It seems that ENABLE
+		 * can change the actual pixel clock but doesn't work with higher
+		 * pixel clocks than what SETUP was called with.
+		 */
+		.pixel_clock = timing ? timing->pix_clk_100hz / 10 : 300000,
+		.color_depth = timing ? timing->display_color_depth : COLOR_DEPTH_888,
+	};
+	DC_LOGGER_INIT(dc->ctx);
 
-	encoder_control.action = enable ? ENCODER_CONTROL_ENABLE : ENCODER_CONTROL_DISABLE;
-	encoder_control.engine_id = link->link_enc->analog_engine;
-	encoder_control.pixel_clock = pipe_ctx->stream->timing.pix_clk_100hz / 10;
-	bios->funcs->encoder_control(bios, &encoder_control);
+	bp_result = bios->funcs->external_encoder_control(bios, &ext_cntl);
+
+	if (bp_result != BP_RESULT_OK)
+		DC_LOG_ERROR("Failed to execute external encoder action: 0x%x\n", action);
+}
+
+static void
+dce110_prepare_ddc(struct dc_link *link)
+{
+	if (link->ext_enc_id.id)
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DDC_SETUP, link, NULL);
 }
 
 static bool
@@ -684,7 +713,8 @@ dce110_dac_load_detect(struct dc_link *link)
 	struct link_encoder *link_enc = link->link_enc;
 	enum bp_result bp_result;
 
-	bp_result = bios->funcs->dac_load_detection(bios, link_enc->analog_engine);
+	bp_result = bios->funcs->dac_load_detection(
+			bios, link_enc->analog_engine, link->ext_enc_id);
 	return bp_result == BP_RESULT_OK;
 }
 
@@ -700,7 +730,6 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 	uint32_t early_control = 0;
 	struct timing_generator *tg = pipe_ctx->stream_res.tg;
 
-	link_hwss->setup_stream_attribute(pipe_ctx);
 	link_hwss->setup_stream_encoder(pipe_ctx);
 
 	dc->hwss.update_info_frame(pipe_ctx);
@@ -719,8 +748,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 
 	tg->funcs->set_early_control(tg, early_control);
 
-	if (dc_is_rgb_signal(pipe_ctx->stream->signal))
-		dce110_dac_encoder_control(pipe_ctx, true);
+	if (link->ext_enc_id.id)
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_ENABLE, link, timing);
 }
 
 static enum bp_result link_transmitter_control(
@@ -1220,8 +1249,8 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
 					       link_enc->transmitter - TRANSMITTER_UNIPHY_A);
 	}
 
-	if (dc_is_rgb_signal(pipe_ctx->stream->signal))
-		dce110_dac_encoder_control(pipe_ctx, false);
+	if (link->ext_enc_id.id)
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DISABLE, link, NULL);
 }
 
 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
@@ -1604,22 +1633,6 @@ static enum dc_status dce110_enable_stream_timing(
 
 	return DC_OK;
 }
-static void
-dce110_select_crtc_source(struct pipe_ctx *pipe_ctx)
-{
-	struct dc_link *link = pipe_ctx->stream->link;
-	struct dc_bios *bios = link->ctx->dc_bios;
-	struct bp_crtc_source_select crtc_source_select = {0};
-	enum engine_id engine_id = link->link_enc->preferred_engine;
-
-	if (dc_is_rgb_signal(pipe_ctx->stream->signal))
-		engine_id = link->link_enc->analog_engine;
-	crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx->stream_res.tg->inst;
-	crtc_source_select.color_depth = pipe_ctx->stream->timing.display_color_depth;
-	crtc_source_select.engine_id = engine_id;
-	crtc_source_select.sink_signal = pipe_ctx->stream->signal;
-	bios->funcs->select_crtc_source(bios, &crtc_source_select);
-}
 
 enum dc_status dce110_apply_single_controller_ctx_to_hw(
 		struct pipe_ctx *pipe_ctx,
@@ -1640,10 +1653,6 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw(
 		hws->funcs.disable_stream_gating(dc, pipe_ctx);
 	}
 
-	if (pipe_ctx->stream->signal == SIGNAL_TYPE_RGB) {
-		dce110_select_crtc_source(pipe_ctx);
-	}
-
 	if (pipe_ctx->stream_res.audio != NULL) {
 		struct audio_output audio_output = {0};
 
@@ -1723,8 +1732,7 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw(
 		pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
 				pipe_ctx->stream_res.tg, event_triggers, 2);
 
-	if (!dc_is_virtual_signal(pipe_ctx->stream->signal) &&
-		!dc_is_rgb_signal(pipe_ctx->stream->signal))
+	if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
 		pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
 			pipe_ctx->stream_res.stream_enc,
 			pipe_ctx->stream_res.tg->inst);
@@ -3379,6 +3387,15 @@ void dce110_enable_tmds_link_output(struct dc_link *link,
 	link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
 }
 
+static void dce110_enable_analog_link_output(
+		struct dc_link *link,
+		uint32_t pix_clk_100hz)
+{
+	link->link_enc->funcs->enable_analog_output(
+			link->link_enc,
+			pix_clk_100hz);
+}
+
 void dce110_enable_dp_link_output(
 		struct dc_link *link,
 		const struct link_resource *link_res,
@@ -3426,6 +3443,11 @@ void dce110_enable_dp_link_output(
 		}
 	}
 
+	if (link->ext_enc_id.id) {
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_INIT, link, NULL);
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_SETUP, link, NULL);
+	}
+
 	if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
 		if (dc->clk_mgr->funcs->notify_link_rate_change)
 			dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
@@ -3516,8 +3538,10 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 	.enable_lvds_link_output = dce110_enable_lvds_link_output,
 	.enable_tmds_link_output = dce110_enable_tmds_link_output,
 	.enable_dp_link_output = dce110_enable_dp_link_output,
+	.enable_analog_link_output = dce110_enable_analog_link_output,
 	.disable_link_output = dce110_disable_link_output,
 	.dac_load_detect = dce110_dac_load_detect,
+	.prepare_ddc = dce110_prepare_ddc,
 };
 
 static const struct hwseq_private_funcs dce110_private_funcs = {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* RE: [PATCH v3] drm/amd/display: Restore analog connector support
  2026-04-18  0:35 [PATCH v3] drm/amd/display: Restore analog connector support Roman.Li
@ 2026-04-21 18:08 ` Li, Roman
  2026-04-21 19:25   ` Timur Kristóf
  0 siblings, 1 reply; 4+ messages in thread
From: Li, Roman @ 2026-04-21 18:08 UTC (permalink / raw)
  To: Timur Kristóf, amd-gfx@lists.freedesktop.org
  Cc: Deucher, Alexander, Wentland, Harry, Li, Sun peng (Leo),
	Pillai,  Aurabindo, Hung, Alex

[Public]

Hi Timur,

Did you get a chance to test V3?

Thanks,
Roman

> -----Original Message-----
> From: Roman.Li@amd.com <Roman.Li@amd.com>
> Sent: Friday, April 17, 2026 8:36 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Wentland, Harry
> <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Pillai,
> Aurabindo <Aurabindo.Pillai@amd.com>; Hung, Alex <Alex.Hung@amd.com>; Li,
> Roman <Roman.Li@amd.com>; Timur Kristóf <timur.kristof@gmail.com>
> Subject: [PATCH v3] drm/amd/display: Restore analog connector support
>
> From: Roman Li <Roman.Li@amd.com>
>
> [Why]
> The analog connector support was accidentally removed, causing a crash when
> connecting an analog monitor.
>
> [How]
> This patch restores the functions and pointers required for proper analog and DP
> bridge encoder support on legacy GPUs.
>
> V2: Restore the external encoder control functions.
>
> V3:
>  - Restore BIOS parser external encoder DAC load detection
>  - Restore stream initialization and source selection changes
>
> Fixes: 66715fc0ecfd ("drm/amd/display: Sync dcn42 with DC 3.2.373")
>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Roman Li <Roman.Li@amd.com>
> Reviewed-by: Alex Hung <alex.hung@amd.com>
> ---
>  .../gpu/drm/amd/display/dc/bios/bios_parser.c | 11 ++-
>  .../gpu/drm/amd/display/dc/dc_bios_types.h    |  3 +-
>  .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 94 ++++++++++++-------
>  3 files changed, 71 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> index 25c94962e141..ec75882ac477 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> @@ -794,11 +794,13 @@ static enum bp_result
> bios_parser_external_encoder_control(
>
>  static enum bp_result bios_parser_dac_load_detection(
>       struct dc_bios *dcb,
> -     enum engine_id engine_id)
> +     enum engine_id engine_id,
> +     struct graphics_object_id ext_enc_id)
>  {
>       struct bios_parser *bp = BP_FROM_DCB(dcb);
>       struct dc_context *ctx = dcb->ctx;
>       struct bp_load_detection_parameters bp_params = {0};
> +     struct bp_external_encoder_control ext_cntl = {0};
>       enum bp_result bp_result = BP_RESULT_UNSUPPORTED;
>       uint32_t bios_0_scratch;
>       uint32_t device_id_mask = 0;
> @@ -824,6 +826,13 @@ static enum bp_result bios_parser_dac_load_detection(
>
>               bp_params.engine_id = engine_id;
>               bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params);
> +     } else if (ext_enc_id.id) {
> +             if (!bp->cmd_tbl.external_encoder_control)
> +                     return BP_RESULT_UNSUPPORTED;
> +
> +             ext_cntl.action =
> EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT;
> +             ext_cntl.encoder_id = ext_enc_id;
> +             bp_result = bp->cmd_tbl.external_encoder_control(bp, &ext_cntl);
>       }
>
>       if (bp_result != BP_RESULT_OK)
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
> b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
> index 6f96c5cf39fe..526f71616f94 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
> @@ -102,7 +102,8 @@ struct dc_vbios_funcs {
>               struct bp_external_encoder_control *cntl);
>       enum bp_result (*dac_load_detection)(
>               struct dc_bios *bios,
> -             enum engine_id engine_id);
> +             enum engine_id engine_id,
> +             struct graphics_object_id ext_enc_id);
>       enum bp_result (*transmitter_control)(
>               struct dc_bios *bios,
>               struct bp_transmitter_control *cntl); diff --git
> a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
> b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
> index 7af239524d71..e6712cffeb04 100644
> --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
> @@ -665,16 +665,45 @@ void dce110_update_info_frame(struct pipe_ctx
> *pipe_ctx)  }
>
>  static void
> -dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable)
> +dce110_external_encoder_control(enum bp_external_encoder_control_action
> action,
> +                             struct dc_link *link,
> +                             struct dc_crtc_timing *timing)
>  {
> -     struct dc_link *link = pipe_ctx->stream->link;
> +     struct dc *dc = link->ctx->dc;
>       struct dc_bios *bios = link->ctx->dc_bios;
> -     struct bp_encoder_control encoder_control = {0};
> +     const struct dc_link_settings *link_settings = &link->cur_link_settings;
> +     enum bp_result bp_result = BP_RESULT_OK;
> +     struct bp_external_encoder_control ext_cntl = {
> +             .action = action,
> +             .connector_obj_id = link->link_enc->connector,
> +             .encoder_id = link->ext_enc_id,
> +             .lanes_number = link_settings->lane_count,
> +             .link_rate = link_settings->link_rate,
> +
> +             /* Use signal type of the real link encoder, ie. DP */
> +             .signal = link->connector_signal,
> +
> +             /* We don't know the timing yet when executing the SETUP action,
> +              * so use a reasonably high default value. It seems that ENABLE
> +              * can change the actual pixel clock but doesn't work with higher
> +              * pixel clocks than what SETUP was called with.
> +              */
> +             .pixel_clock = timing ? timing->pix_clk_100hz / 10 : 300000,
> +             .color_depth = timing ? timing->display_color_depth :
> COLOR_DEPTH_888,
> +     };
> +     DC_LOGGER_INIT(dc->ctx);
>
> -     encoder_control.action = enable ? ENCODER_CONTROL_ENABLE :
> ENCODER_CONTROL_DISABLE;
> -     encoder_control.engine_id = link->link_enc->analog_engine;
> -     encoder_control.pixel_clock = pipe_ctx->stream->timing.pix_clk_100hz / 10;
> -     bios->funcs->encoder_control(bios, &encoder_control);
> +     bp_result = bios->funcs->external_encoder_control(bios, &ext_cntl);
> +
> +     if (bp_result != BP_RESULT_OK)
> +             DC_LOG_ERROR("Failed to execute external encoder action:
> 0x%x\n",
> +action); }
> +
> +static void
> +dce110_prepare_ddc(struct dc_link *link) {
> +     if (link->ext_enc_id.id)
> +
>       dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_D
> DC_SETUP,
> +link, NULL);
>  }
>
>  static bool
> @@ -684,7 +713,8 @@ dce110_dac_load_detect(struct dc_link *link)
>       struct link_encoder *link_enc = link->link_enc;
>       enum bp_result bp_result;
>
> -     bp_result = bios->funcs->dac_load_detection(bios, link_enc-
> >analog_engine);
> +     bp_result = bios->funcs->dac_load_detection(
> +                     bios, link_enc->analog_engine, link->ext_enc_id);
>       return bp_result == BP_RESULT_OK;
>  }
>
> @@ -700,7 +730,6 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
>       uint32_t early_control = 0;
>       struct timing_generator *tg = pipe_ctx->stream_res.tg;
>
> -     link_hwss->setup_stream_attribute(pipe_ctx);
>       link_hwss->setup_stream_encoder(pipe_ctx);
>
>       dc->hwss.update_info_frame(pipe_ctx);
> @@ -719,8 +748,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
>
>       tg->funcs->set_early_control(tg, early_control);
>
> -     if (dc_is_rgb_signal(pipe_ctx->stream->signal))
> -             dce110_dac_encoder_control(pipe_ctx, true);
> +     if (link->ext_enc_id.id)
> +
>       dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_E
> NABLE,
> +link, timing);
>  }
>
>  static enum bp_result link_transmitter_control( @@ -1220,8 +1249,8 @@ void
> dce110_disable_stream(struct pipe_ctx *pipe_ctx)
>                                              link_enc->transmitter -
> TRANSMITTER_UNIPHY_A);
>       }
>
> -     if (dc_is_rgb_signal(pipe_ctx->stream->signal))
> -             dce110_dac_encoder_control(pipe_ctx, false);
> +     if (link->ext_enc_id.id)
> +
>       dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DI
> SABLE,
> +link, NULL);
>  }
>
>  void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, @@ -1604,22 +1633,6
> @@ static enum dc_status dce110_enable_stream_timing(
>
>       return DC_OK;
>  }
> -static void
> -dce110_select_crtc_source(struct pipe_ctx *pipe_ctx) -{
> -     struct dc_link *link = pipe_ctx->stream->link;
> -     struct dc_bios *bios = link->ctx->dc_bios;
> -     struct bp_crtc_source_select crtc_source_select = {0};
> -     enum engine_id engine_id = link->link_enc->preferred_engine;
> -
> -     if (dc_is_rgb_signal(pipe_ctx->stream->signal))
> -             engine_id = link->link_enc->analog_engine;
> -     crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx-
> >stream_res.tg->inst;
> -     crtc_source_select.color_depth = pipe_ctx->stream-
> >timing.display_color_depth;
> -     crtc_source_select.engine_id = engine_id;
> -     crtc_source_select.sink_signal = pipe_ctx->stream->signal;
> -     bios->funcs->select_crtc_source(bios, &crtc_source_select);
> -}
>
>  enum dc_status dce110_apply_single_controller_ctx_to_hw(
>               struct pipe_ctx *pipe_ctx,
> @@ -1640,10 +1653,6 @@ enum dc_status
> dce110_apply_single_controller_ctx_to_hw(
>               hws->funcs.disable_stream_gating(dc, pipe_ctx);
>       }
>
> -     if (pipe_ctx->stream->signal == SIGNAL_TYPE_RGB) {
> -             dce110_select_crtc_source(pipe_ctx);
> -     }
> -
>       if (pipe_ctx->stream_res.audio != NULL) {
>               struct audio_output audio_output = {0};
>
> @@ -1723,8 +1732,7 @@ enum dc_status
> dce110_apply_single_controller_ctx_to_hw(
>               pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
>                               pipe_ctx->stream_res.tg, event_triggers, 2);
>
> -     if (!dc_is_virtual_signal(pipe_ctx->stream->signal) &&
> -             !dc_is_rgb_signal(pipe_ctx->stream->signal))
> +     if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
>               pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
>                       pipe_ctx->stream_res.stream_enc,
>                       pipe_ctx->stream_res.tg->inst);
> @@ -3379,6 +3387,15 @@ void dce110_enable_tmds_link_output(struct dc_link
> *link,
>       link->phy_state.symclk_state = SYMCLK_ON_TX_ON;  }
>
> +static void dce110_enable_analog_link_output(
> +             struct dc_link *link,
> +             uint32_t pix_clk_100hz)
> +{
> +     link->link_enc->funcs->enable_analog_output(
> +                     link->link_enc,
> +                     pix_clk_100hz);
> +}
> +
>  void dce110_enable_dp_link_output(
>               struct dc_link *link,
>               const struct link_resource *link_res, @@ -3426,6 +3443,11 @@
> void dce110_enable_dp_link_output(
>               }
>       }
>
> +     if (link->ext_enc_id.id) {
> +
>       dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_IN
> IT, link, NULL);
> +
>       dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_S
> ETUP, link, NULL);
> +     }
> +
>       if (dc->link_srv->dp_get_encoding_format(link_settings) ==
> DP_8b_10b_ENCODING) {
>               if (dc->clk_mgr->funcs->notify_link_rate_change)
>                       dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr,
> link); @@ -3516,8 +3538,10 @@ static const struct hw_sequencer_funcs
> dce110_funcs = {
>       .enable_lvds_link_output = dce110_enable_lvds_link_output,
>       .enable_tmds_link_output = dce110_enable_tmds_link_output,
>       .enable_dp_link_output = dce110_enable_dp_link_output,
> +     .enable_analog_link_output = dce110_enable_analog_link_output,
>       .disable_link_output = dce110_disable_link_output,
>       .dac_load_detect = dce110_dac_load_detect,
> +     .prepare_ddc = dce110_prepare_ddc,
>  };
>
>  static const struct hwseq_private_funcs dce110_private_funcs = {
> --
> 2.34.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v3] drm/amd/display: Restore analog connector support
  2026-04-21 18:08 ` Li, Roman
@ 2026-04-21 19:25   ` Timur Kristóf
  2026-04-21 22:11     ` Li, Roman
  0 siblings, 1 reply; 4+ messages in thread
From: Timur Kristóf @ 2026-04-21 19:25 UTC (permalink / raw)
  To: amd-gfx@lists.freedesktop.org, Li, Roman
  Cc: Deucher, Alexander, Wentland, Harry, Li, Sun peng (Leo),
	Pillai, Aurabindo, Hung, Alex

On 2026. április 21., kedd 20:08:21 közép-európai nyári idő Li, Roman wrote:
> [Public]
> 
> Hi Timur,
> 
> Did you get a chance to test V3?
> 
> Thanks,
> Roman

Hi Roman,

Yes I tested it, it works fine also on Kaveri (with DP bridge encoder) and 
other GPUs with a DAC encoder. Nice work, thank you!
V3 of the patch is:
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Tested-by: Timur Kristóf <timur.kristof@gmail.com>

I noticed that there is still an issue with an Oland GPU that has a VGA 
connector, that hits an ASSERT(0) thanks to a recent HPD refactor:
https://gitlab.freedesktop.org/agd5f/linux/-/blob/
a1404287ad4cc349ce3f5d94ac81903db9e0351f/drivers/gpu/drm/amd/display/dc/link/
link_factory.c#L608

At the moment I'm not sure if we should just remove the assertion or maybe 
other changes are also necessary? What do you think?

Thanks & best regards,
Timur




^ permalink raw reply	[flat|nested] 4+ messages in thread

* RE: [PATCH v3] drm/amd/display: Restore analog connector support
  2026-04-21 19:25   ` Timur Kristóf
@ 2026-04-21 22:11     ` Li, Roman
  0 siblings, 0 replies; 4+ messages in thread
From: Li, Roman @ 2026-04-21 22:11 UTC (permalink / raw)
  To: Timur Kristóf, amd-gfx@lists.freedesktop.org
  Cc: Deucher, Alexander, Wentland, Harry, Li, Sun peng (Leo),
	Pillai,  Aurabindo, Hung, Alex

[Public]

> -----Original Message-----
> From: Timur Kristóf <timur.kristof@gmail.com>
> Sent: Tuesday, April 21, 2026 3:26 PM
> To: amd-gfx@lists.freedesktop.org; Li, Roman <Roman.Li@amd.com>
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Wentland, Harry
> <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Pillai,
> Aurabindo <Aurabindo.Pillai@amd.com>; Hung, Alex <Alex.Hung@amd.com>
> Subject: Re: [PATCH v3] drm/amd/display: Restore analog connector support
>
> On 2026. április 21., kedd 20:08:21 közép-európai nyári idő Li, Roman wrote:
> > [Public]
> >
> > Hi Timur,
> >
> > Did you get a chance to test V3?
> >
> > Thanks,
> > Roman
>
> Hi Roman,
>
> Yes I tested it, it works fine also on Kaveri (with DP bridge encoder) and other
> GPUs with a DAC encoder. Nice work, thank you!
> V3 of the patch is:
> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
> Tested-by: Timur Kristóf <timur.kristof@gmail.com>

Thanks, Timur! The patch is merged.

>
> I noticed that there is still an issue with an Oland GPU that has a VGA connector,
> that hits an ASSERT(0) thanks to a recent HPD refactor:
> https://gitlab.freedesktop.org/agd5f/linux/-/blob/
> a1404287ad4cc349ce3f5d94ac81903db9e0351f/drivers/gpu/drm/amd/display/dc/lin
> k/
> link_factory.c#L608
>
> At the moment I'm not sure if we should just remove the assertion or maybe other
> changes are also necessary? What do you think?

I think we should remove the assert and gracefully fall back to HPD_SOURCEID_UNKNOWN for VGA connectors.
Will submit a patch after internal review.
- Roman

>
> Thanks & best regards,
> Timur
>
>


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2026-04-21 22:11 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-04-18  0:35 [PATCH v3] drm/amd/display: Restore analog connector support Roman.Li
2026-04-21 18:08 ` Li, Roman
2026-04-21 19:25   ` Timur Kristóf
2026-04-21 22:11     ` Li, Roman

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