[U-Boot] [PATCH v1 0/4] introducing vect1: mpc8309 keymile board

[U-Boot] [PATCH v1 0/4] introducing vect1: mpc8309 keymile board

[Gerlando Falauto]

This patch series adds support for VECT1, an mpc8309-powered Keymile board.
MPC8309 is not currently supported by u-boot, so we first add support for
this processor.
VECT1 is somewhat similar to suvd3, albeit powered by a different processor,
so we use its config file as opposed to introducing a new one.

NOTE: speed.c is getting more and more complicated by long #ifdef conditions
affecting even single lines. Perhaps a whole feature-set partitioning could
lead to much cleaner code.

Gerlando Falauto (4):
  cosmetic: suvd3: align #defines
  mpc83xx: add support for mpc8309
  km83xx: add common support for km8309 boards
  km83xx: add kmvect1 board

 arch/powerpc/cpu/mpc83xx/cpu.c         |    1 +
 arch/powerpc/cpu/mpc83xx/cpu_init.c    |    3 +
 arch/powerpc/cpu/mpc83xx/speed.c       |   30 +++++-
 arch/powerpc/include/asm/global_data.h |    2 +
 arch/powerpc/include/asm/immap_83xx.h  |   65 +++++++++++-
 arch/powerpc/include/asm/immap_qe.h    |    2 +-
 board/keymile/km83xx/km83xx.c          |    2 +-
 boards.cfg                             |    3 +-
 drivers/qe/qe.c                        |   21 ++--
 include/configs/km/km8309-common.h     |  174 ++++++++++++++++++++++++++++++++
 include/configs/km/km8321-common.h     |    2 +-
 include/configs/km/km83xx-common.h     |    6 ++
 include/configs/suvd3.h                |   19 +++-
 include/mpc83xx.h                      |  156 +++++++++++++++++++++++++++-
 14 files changed, 461 insertions(+), 25 deletions(-)
 create mode 100644 include/configs/km/km8309-common.h

-- 
1.7.10.1

[U-Boot] [PATCH v1 1/4] cosmetic: suvd3: align #defines

[Gerlando Falauto]

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
---
 include/configs/km/km8321-common.h |    2 +-
 include/configs/suvd3.h            |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h
index 580b72f..8ad6fc3 100644
--- a/include/configs/km/km8321-common.h
+++ b/include/configs/km/km8321-common.h
@@ -115,7 +115,7 @@
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 
 #define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
-#define	CONFIG_SYS_KMBEC_FPGA_SIZE	128
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
 
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index ae19701..68680c5 100644
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -33,9 +33,9 @@
 #include "km/km8321-common.h"
 
 #define CONFIG_SYS_APP1_BASE		0xA0000000
-#define	CONFIG_SYS_APP1_SIZE		256 /* Megabytes */
+#define CONFIG_SYS_APP1_SIZE		256 /* Megabytes */
 #define CONFIG_SYS_APP2_BASE		0xB0000000
-#define	CONFIG_SYS_APP2_SIZE		256 /* Megabytes */
+#define CONFIG_SYS_APP2_SIZE		256 /* Megabytes */
 
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-- 
1.7.10.1

[U-Boot] [PATCH v1 2/4] mpc83xx: add support for mpc8309

[Gerlando Falauto]

This processor, though very similar to other members of the
PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
yet another feature set than any supported sibling.

So we add a bunch of new #ifdefs (or complicate the existing ones)
to arch/powerpc/cpu/mpc83xx/speed.c.

Perhaps it would be worth to refactor the whole file so to first
identify the featureset of the given CPU, and enclose each block within
 #ifdef CONFIG_MPC83XX_FEAT_XXXX
for instance:
 - CONFIG_MPC83XX_FEAT_USBDR
 - CONFIG_MPC83XX_FEAT_QE
 - CONFIG_MPC83XX_FEAT_DDRSEC
...etc...

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
---
 arch/powerpc/cpu/mpc83xx/cpu.c         |    1 +
 arch/powerpc/cpu/mpc83xx/cpu_init.c    |    3 +
 arch/powerpc/cpu/mpc83xx/speed.c       |   30 +++++-
 arch/powerpc/include/asm/global_data.h |    2 +
 arch/powerpc/include/asm/immap_83xx.h  |   65 ++++++++++++-
 arch/powerpc/include/asm/immap_qe.h    |    2 +-
 drivers/qe/qe.c                        |   21 +++--
 include/mpc83xx.h                      |  156 +++++++++++++++++++++++++++++++-
 8 files changed, 263 insertions(+), 17 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 6635109..e64b0c3 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -56,6 +56,7 @@ int checkcpu(void)
 		u32 partid;
 	} cpu_type_list [] = {
 		CPU_TYPE_ENTRY(8308),
+		CPU_TYPE_ENTRY(8309),
 		CPU_TYPE_ENTRY(8311),
 		CPU_TYPE_ENTRY(8313),
 		CPU_TYPE_ENTRY(8314),
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 76afba5..20d0600 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -268,6 +268,9 @@ void cpu_init_f (volatile immap_t * im)
 #ifdef CONFIG_SYS_SICRL
 	__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 #endif
+#ifdef CONFIG_SYS_GPR1
+	__raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
+#endif
 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 	__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 #endif
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index f78099d..06ed86f 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -105,6 +105,8 @@ int get_clocks(void)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+	u32 usbdr_clk;
 #endif
 #ifdef CONFIG_MPC834x
 	u32 usbmph_clk;
@@ -120,14 +122,17 @@ int get_clocks(void)
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
+#if !defined(CONFIG_MPC8309)
 	u32 enc_clk;
+#endif
 	u32 lbiu_clk;
 	u32 lclk_clk;
 	u32 mem_clk;
 #if defined(CONFIG_MPC8360)
 	u32 mem_sec_clk;
 #endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_MPC8309) || defined(CONFIG_MPC8360) || \
+	defined(CONFIG_MPC832x)
 	u32 qepmf;
 	u32 qepdf;
 	u32 qe_clk;
@@ -185,7 +190,10 @@ int get_clocks(void)
 		/* unkown SCCR_TSEC1CM value */
 		return -2;
 	}
+#endif
 
+#if defined(CONFIG_MPC8309) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
 	case 0:
 		usbdr_clk = 0;
@@ -260,6 +268,7 @@ int get_clocks(void)
 		return -6;
 	}
 #endif
+#if !defined(CONFIG_MPC8309)
 	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
 	case 0:
 		enc_clk = 0;
@@ -277,6 +286,7 @@ int get_clocks(void)
 		/* unkown SCCR_ENCCM value */
 		return -7;
 	}
+#endif
 
 #if defined(CONFIG_FSL_ESDHC)
 	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
@@ -329,6 +339,8 @@ int get_clocks(void)
 	i2c1_clk = sdhc_clk;
 #elif defined(CONFIG_MPC837x)
 	i2c1_clk = enc_clk;
+#elif defined(CONFIG_MPC8309)
+	i2c1_clk = csb_clk;
 #endif
 #if !defined(CONFIG_MPC832x)
 	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
@@ -444,7 +456,8 @@ int get_clocks(void)
 		return -13;
 	}
 
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_MPC8309) || defined(CONFIG_MPC8360) \
+	|| defined(CONFIG_MPC832x)
 	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
 	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
 	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
@@ -457,6 +470,8 @@ int get_clocks(void)
 	gd->tsec1_clk = tsec1_clk;
 	gd->tsec2_clk = tsec2_clk;
 	gd->usbdr_clk = usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+	gd->usbdr_clk = usbdr_clk;
 #endif
 #if defined(CONFIG_MPC834x)
 	gd->usbmph_clk = usbmph_clk;
@@ -472,14 +487,17 @@ int get_clocks(void)
 #if !defined(CONFIG_MPC832x)
 	gd->i2c2_clk = i2c2_clk;
 #endif
+#if !defined(CONFIG_MPC8309)
 	gd->enc_clk = enc_clk;
+#endif
 	gd->lbiu_clk = lbiu_clk;
 	gd->lclk_clk = lclk_clk;
 	gd->mem_clk = mem_clk;
 #if defined(CONFIG_MPC8360)
 	gd->mem_sec_clk = mem_sec_clk;
 #endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_MPC8309) || defined(CONFIG_MPC8360) || \
+	defined(CONFIG_MPC832x)
 	gd->qe_clk = qe_clk;
 	gd->brg_clk = brg_clk;
 #endif
@@ -523,7 +541,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 	printf("Clock configuration:\n");
 	printf("  Core:                %-4s MHz\n", strmhz(buf, gd->core_clk));
 	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_MPC8309) || defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 	printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
 	printf("  BRG:                 %-4s MHz\n", strmhz(buf, gd->brg_clk));
 #endif
@@ -533,7 +551,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_MPC8360)
 	printf("  DDR Secondary:       %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
 #endif
+#if !defined(CONFIG_MPC8309)
 	printf("  SEC:                 %-4s MHz\n", strmhz(buf, gd->enc_clk));
+#endif
 	printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
 #if !defined(CONFIG_MPC832x)
 	printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
@@ -549,6 +569,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 	printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
 	printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
 	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+#elif defined(CONFIG_MPC8309)
+	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
 #endif
 #if defined(CONFIG_MPC834x)
 	printf("  USB MPH:             %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 01f1d4a..5424160 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -65,6 +65,8 @@ typedef	struct	global_data {
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+	u32 usbdr_clk;
 #endif
 #if defined (CONFIG_MPC834x)
 	u32 usbmph_clk;
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 2ba502a..c03b693 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -73,12 +73,19 @@ typedef struct sysconf83xx {
 	u32 obir;		/* Output Buffer Impedance Register */
 	u8 res8[0xC];
 	u32 pecr1;		/* PCI Express control register 1 */
-#ifdef CONFIG_MPC8308
-	u32 sdhccr;		/* eSDHC Control Registers for MPC8308 */
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8309)
+	u32 sdhccr;		/* eSDHC Control Registers for MPC830x */
 #else
 	u32 pecr2;		/* PCI Express control register 2 */
 #endif
+#if defined(CONFIG_MPC8309)
+	u32 can_dbg_ctrl;
+	u32 res9a;
+	u32 gpr1;
+	u8 res9b[0xAC];
+#else
 	u8 res9[0xB8];
+#endif
 } sysconf83xx_t;
 
 /*
@@ -708,7 +715,11 @@ typedef struct serdes83xx {
  * On Chip ROM
  */
 typedef struct rom83xx {
+#if defined(CONFIG_MPC8309)
+	u8 mem[0x8000];
+#else
 	u8 mem[0x10000];
+#endif
 } rom83xx_t;
 
 /*
@@ -972,6 +983,56 @@ typedef struct immap {
 	u8			res8[0xC0000];
 	u8			qe[0x100000];	/* QE block */
 } immap_t;
+#elif defined(CONFIG_MPC8309)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[2];	/* General purpose I/O module */
+	u8			res0[0x500];	/* res0 1.25 KBytes added for 8309 */
+	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
+	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
+	u8			res1[0x800];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res2[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res3[0x200];
+	duart83xx_t		duart1[2];	/* DUART */
+	u8			res4[0x500];
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
+	u8			res5[0x1000];
+	u8			spi[0x100];
+	u8			res6[0xf00];
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Configuration Registers */
+	u8			res7[0x80];
+	ios83xx_t		ios;		/* Sequencer (IOS) */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Control & Status Registers */
+	u8			res8[0x13A00];
+	u8			can1[0x1000];	/* Flexcan 1 */
+	u8			can2[0x1000];	/* Flexcan 2 */
+	u8			res9[0x5000];
+	usb83xx_t		usb;
+	u8			res10[0x5000];
+	u8			can3[0x1000];	/* Flexcan 3 */
+	u8			can4[0x1000];	/* Flexcan 4 */
+	u8			res11[0x1000];
+	u8			dma1[0x2000];	/* DMA */
+	sdhc83xx_t		sdhc;		/* SDHC Controller */
+	u8			res12[0xC1000];
+	rom83xx_t		rom;		/* On Chip ROM */
+	u8			res13[0x8000];
+	u8			qe[0x100000];	/* QE block */
+	u8			res14[0xE00000];/* Added for 8309 */
+} immap_t;
 #endif
 
 #define CONFIG_SYS_MPC83xx_DDR_OFFSET	(0x2000)
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
index 9be9dca..f0b989a 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -20,7 +20,7 @@
 #define QE_MURAM_SIZE		0xc000UL
 #define MAX_QE_RISC		2
 #define QE_NUM_OF_SNUM		28
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
 #define QE_MURAM_SIZE		0x4000UL
 #define MAX_QE_RISC		1
 #define QE_NUM_OF_SNUM		28
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 9f71151..345587b 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -113,18 +113,21 @@ static void qe_sdma_init(void)
  * we just need to know what the SNUMs are for the threads.
  */
 static u8 thread_snum[] = {
+/* Evthreads 16-29 are not supported in MPC8309 */
+#if !defined(CONFIG_MPC8309)
 	0x04, 0x05, 0x0c, 0x0d,
 	0x14, 0x15, 0x1c, 0x1d,
 	0x24, 0x25, 0x2c, 0x2d,
-	0x34, 0x35, 0x88, 0x89,
-	0x98, 0x99, 0xa8, 0xa9,
-	0xb8, 0xb9, 0xc8, 0xc9,
-	0xd8, 0xd9, 0xe8, 0xe9,
-	0x08, 0x09, 0x18, 0x19,
-	0x28, 0x29, 0x38, 0x39,
-	0x48, 0x49, 0x58, 0x59,
-	0x68, 0x69, 0x78, 0x79,
-	0x80, 0x81
+	0x34, 0x35,
+#endif
+	0x88, 0x89, 0x98, 0x99,
+	0xa8, 0xa9, 0xb8, 0xb9,
+	0xc8, 0xc9, 0xd8, 0xd9,
+	0xe8, 0xe9, 0x08, 0x09,
+	0x18, 0x19, 0x28, 0x29,
+	0x38, 0x39, 0x48, 0x49,
+	0x58, 0x59, 0x68, 0x69,
+	0x78, 0x79, 0x80, 0x81
 };
 
 static void qe_snums_init(void)
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index a78f1a2..260bf79 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -74,6 +74,7 @@
 #define SPR_FAMILY(spridr)		((spridr & 0xFFF00000) >> 20)
 
 #define SPR_8308			0x8100
+#define SPR_8309			0x8110
 #define SPR_831X_FAMILY			0x80B
 #define SPR_8311			0x80B2
 #define SPR_8313			0x80B0
@@ -389,6 +390,86 @@
 #define SICRH_TSOBI1_V2P5		(1 << 1)
 #define SICRH_TSOBI2_V3P3		(0 << 0)
 #define SICRH_TSOBI2_V2P5		(1 << 0)
+
+#elif defined(CONFIG_MPC8309)
+/* SICR_1 */
+#define SICR_1_UART1_UART1S		(0 << (30-2))
+#define SICR_1_UART1_UART1RTS		(1 << (30-2))
+#define SICR_1_I2C_I2C			(0 << (30-4))
+#define SICR_1_I2C_CKSTOP		(1 << (30-4))
+#define SICR_1_IRQ_A_IRQ		(0 << (30-6))
+#define SICR_1_IRQ_A_MCP		(1 << (30-6))
+#define SICR_1_IRQ_B_IRQ		(0 << (30-8))
+#define SICR_1_IRQ_B_CKSTOP		(1 << (30-8))
+#define SICR_1_GPIO_A_GPIO		(0 << (30-10))
+#define SICR_1_GPIO_A_SD		(2 << (30-10))
+#define SICR_1_GPIO_A_DDR		(3 << (30-10))
+#define SICR_1_GPIO_B_GPIO		(0 << (30-12))
+#define SICR_1_GPIO_B_SD		(2 << (30-12))
+#define SICR_1_GPIO_B_QE		(3 << (30-12))
+#define SICR_1_GPIO_C_GPIO		(0 << (30-14))
+#define SICR_1_GPIO_C_CAN		(1 << (30-14))
+#define SICR_1_GPIO_C_DDR		(2 << (30-14))
+#define SICR_1_GPIO_C_LCS		(3 << (30-14))
+#define SICR_1_GPIO_D_GPIO		(0 << (30-16))
+#define SICR_1_GPIO_D_CAN		(1 << (30-16))
+#define SICR_1_GPIO_D_DDR		(2 << (30-16))
+#define SICR_1_GPIO_D_LCS		(3 << (30-16))
+#define SICR_1_GPIO_E_GPIO		(0 << (30-18))
+#define SICR_1_GPIO_E_CAN		(1 << (30-18))
+#define SICR_1_GPIO_E_DDR		(2 << (30-18))
+#define SICR_1_GPIO_E_LCS		(3 << (30-18))
+#define SICR_1_GPIO_F_GPIO		(0 << (30-20))
+#define SICR_1_GPIO_F_CAN		(1 << (30-20))
+#define SICR_1_GPIO_F_CK		(2 << (30-20))
+#define SICR_1_USB_A_USBDR		(0 << (30-22))
+#define SICR_1_USB_A_UART2S		(1 << (30-22))
+#define SICR_1_USB_B_USBDR		(0 << (30-24))
+#define SICR_1_USB_B_UART2S		(1 << (30-24))
+#define SICR_1_USB_B_UART2RTS		(2 << (30-24))
+#define SICR_1_USB_C_USBDR		(0 << (30-26))
+#define SICR_1_USB_C_QE_EXT		(3 << (30-26))
+#define SICR_1_FEC1_FEC1		(0 << (30-28))
+#define SICR_1_FEC1_GTM			(1 << (30-28))
+#define SICR_1_FEC1_GPIO		(2 << (30-28))
+#define SICR_1_FEC2_FEC2		(0 << (30-30))
+#define SICR_1_FEC2_GTM			(1 << (30-30))
+#define SICR_1_FEC2_GPIO		(2 << (30-30))
+/* SICR_2 */
+#define SICR_2_FEC3_FEC3		(0 << (30-0))
+#define SICR_2_FEC3_TMR			(1 << (30-0))
+#define SICR_2_FEC3_GPIO		(2 << (30-0))
+#define SICR_2_HDLC1_A_HDLC1		(0 << (30-2))
+#define SICR_2_HDLC1_A_GPIO		(1 << (30-2))
+#define SICR_2_HDLC1_A_TDM1		(2 << (30-2))
+#define SICR_2_ELBC_A_LA		(0 << (30-4))
+#define SICR_2_ELBC_B_LCLK		(0 << (30-6))
+#define SICR_2_HDLC2_A_HDLC2		(0 << (30-8))
+#define SICR_2_HDLC2_A_GPIO		(0 << (30-8))
+#define SICR_2_HDLC2_A_TDM2		(0 << (30-8))
+/* bits 10-11 unused */
+#define SICR_2_USB_D_USBDR		(0 << (30-12))
+#define SICR_2_USB_D_GPIO		(2 << (30-12))
+#define SICR_2_USB_D_QE_BRG		(3 << (30-12))
+#define SICR_2_PCI_PCI			(0 << (30-14))
+#define SICR_2_PCI_CPCI_HS		(2 << (30-14))
+#define SICR_2_HDLC1_B_HDLC1		(0 << (30-16))
+#define SICR_2_HDLC1_B_GPIO		(1 << (30-16))
+#define SICR_2_HDLC1_B_QE_BRG		(2 << (30-16))
+#define SICR_2_HDLC1_B_TDM1		(3 << (30-16))
+#define SICR_2_HDLC1_C_HDLC1		(0 << (30-18))
+#define SICR_2_HDLC1_C_GPIO		(1 << (30-18))
+#define SICR_2_HDLC1_C_TDM1		(2 << (30-18))
+#define SICR_2_HDLC2_B_HDLC2		(0 << (30-20))
+#define SICR_2_HDLC2_B_GPIO		(1 << (30-20))
+#define SICR_2_HDLC2_B_QE_BRG		(2 << (30-20))
+#define SICR_2_HDLC2_B_TDM2		(3 << (30-20))
+#define SICR_2_HDLC2_C_HDLC2		(0 << (30-22))
+#define SICR_2_HDLC2_C_GPIO		(1 << (30-22))
+#define SICR_2_HDLC2_C_TDM2		(2 << (30-22))
+#define SICR_2_HDLC2_C_QE_BRG		(3 << (30-22))
+#define SICR_2_QUIESCE_B		(0 << (30-24))
+
 #endif
 
 /*
@@ -580,6 +661,63 @@
 #define HRCWL_SVCOD_DIV_8		0x10000000
 #define HRCWL_SVCOD_DIV_2		0x20000000
 #define HRCWL_SVCOD_DIV_1		0x30000000
+#elif defined(CONFIG_MPC8309)
+
+#define HRCWL_CEVCOD			0x000000C0
+#define HRCWL_CEVCOD_SHIFT		6
+/*
+ * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
+ * these are different than with 8360, 832x
+ */
+#define HRCWL_CE_PLL_VCO_DIV_2		0x00000000
+#define HRCWL_CE_PLL_VCO_DIV_4		0x00000040
+#define HRCWL_CE_PLL_VCO_DIV_8		0x00000080
+
+#define HRCWL_CEPDF			0x00000020
+#define HRCWL_CEPDF_SHIFT		5
+#define HRCWL_CE_PLL_DIV_1X1		0x00000000
+#define HRCWL_CE_PLL_DIV_2X1		0x00000020
+
+#define HRCWL_CEPMF			0x0000001F
+#define HRCWL_CEPMF_SHIFT		0
+#define HRCWL_CE_TO_PLL_1X16_		0x00000000
+#define HRCWL_CE_TO_PLL_1X2		0x00000002
+#define HRCWL_CE_TO_PLL_1X3		0x00000003
+#define HRCWL_CE_TO_PLL_1X4		0x00000004
+#define HRCWL_CE_TO_PLL_1X5		0x00000005
+#define HRCWL_CE_TO_PLL_1X6		0x00000006
+#define HRCWL_CE_TO_PLL_1X7		0x00000007
+#define HRCWL_CE_TO_PLL_1X8		0x00000008
+#define HRCWL_CE_TO_PLL_1X9		0x00000009
+#define HRCWL_CE_TO_PLL_1X10		0x0000000A
+#define HRCWL_CE_TO_PLL_1X11		0x0000000B
+#define HRCWL_CE_TO_PLL_1X12		0x0000000C
+#define HRCWL_CE_TO_PLL_1X13		0x0000000D
+#define HRCWL_CE_TO_PLL_1X14		0x0000000E
+#define HRCWL_CE_TO_PLL_1X15		0x0000000F
+#define HRCWL_CE_TO_PLL_1X16		0x00000010
+#define HRCWL_CE_TO_PLL_1X17		0x00000011
+#define HRCWL_CE_TO_PLL_1X18		0x00000012
+#define HRCWL_CE_TO_PLL_1X19		0x00000013
+#define HRCWL_CE_TO_PLL_1X20		0x00000014
+#define HRCWL_CE_TO_PLL_1X21		0x00000015
+#define HRCWL_CE_TO_PLL_1X22		0x00000016
+#define HRCWL_CE_TO_PLL_1X23		0x00000017
+#define HRCWL_CE_TO_PLL_1X24		0x00000018
+#define HRCWL_CE_TO_PLL_1X25		0x00000019
+#define HRCWL_CE_TO_PLL_1X26		0x0000001A
+#define HRCWL_CE_TO_PLL_1X27		0x0000001B
+#define HRCWL_CE_TO_PLL_1X28		0x0000001C
+#define HRCWL_CE_TO_PLL_1X29		0x0000001D
+#define HRCWL_CE_TO_PLL_1X30		0x0000001E
+#define HRCWL_CE_TO_PLL_1X31		0x0000001F
+
+#define HRCWL_SVCOD			0x30000000
+#define HRCWL_SVCOD_SHIFT		28
+#define HRCWL_SVCOD_DIV_2		0x00000000
+#define HRCWL_SVCOD_DIV_4		0x10000000
+#define HRCWL_SVCOD_DIV_8		0x20000000
+#define HRCWL_SVCOD_DIV_1		0x30000000
 #endif
 
 /*
@@ -940,6 +1078,21 @@
 #define SCCR_SATACM_1			0x00000055
 #define SCCR_SATACM_2			0x000000aa
 #define SCCR_SATACM_3			0x000000ff
+#elif defined(CONFIG_MPC8309)
+/* SCCR bits - MPC8309 specific */
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+
+#define SCCR_USBDRCM			0x00c00000
+#define SCCR_USBDRCM_SHIFT		22
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00400000
+#define SCCR_USBDRCM_2			0x00800000
+#define SCCR_USBDRCM_3			0x00c00000
 #endif
 
 #define SCCR_PCIEXP1CM			0x00300000
@@ -969,7 +1122,8 @@
  */
 #define CSCONFIG_EN			0x80000000
 #define CSCONFIG_AP			0x00800000
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8309) || \
+	defined(CONFIG_MPC831x)
 #define CSCONFIG_ODT_RD_NEVER		0x00000000
 #define CSCONFIG_ODT_RD_ONLY_CURRENT	0x00100000
 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS	0x00200000
-- 
1.7.10.1

[U-Boot] [PATCH v1 2/4] mpc83xx: add support for mpc8309

[Kim Phillips]

On Wed, 26 Sep 2012 10:28:08 +0200
Gerlando Falauto <gerlando.falauto@keymile.com> wrote:

> This processor, though very similar to other members of the
> PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
> yet another feature set than any supported sibling.
> 
> So we add a bunch of new #ifdefs (or complicate the existing ones)
> to arch/powerpc/cpu/mpc83xx/speed.c.
> 
> Perhaps it would be worth to refactor the whole file so to first
> identify the featureset of the given CPU, and enclose each block within
>  #ifdef CONFIG_MPC83XX_FEAT_XXXX
> for instance:
>  - CONFIG_MPC83XX_FEAT_USBDR

this is CONFIG_HAS_FSL_DR_USB

>  - CONFIG_MPC83XX_FEAT_QE

this could be CONFIG_QE but should probably be CONFIG_HAS_FSL_QE
which doesn't exist.

>  - CONFIG_MPC83XX_FEAT_DDRSEC
> ...etc...

it still wouldn't help that much with the cases like one SoC getting
its tsec clock from somewhere completely different than the others.
Plus, the mpc8309 should be the last of the Mohicans...

> @@ -120,14 +122,17 @@ int get_clocks(void)
>  #if defined(CONFIG_FSL_ESDHC)
>  	u32 sdhc_clk;
>  #endif
> +#if !defined(CONFIG_MPC8309)
>  	u32 enc_clk;
> +#endif

the 8309 is supposed to be similar to the 8308, which also doesn't
have enc_clk (even though it doesn't do this).  I'm thinking
CONFIG_MPC8308 should be renamed _MPC830x before adding support for
the 8309.

> @@ -457,6 +470,8 @@ int get_clocks(void)
>  	gd->tsec1_clk = tsec1_clk;
>  	gd->tsec2_clk = tsec2_clk;
>  	gd->usbdr_clk = usbdr_clk;
> +#elif defined(CONFIG_MPC8309)
> +	gd->usbdr_clk = usbdr_clk;
>  #endif

this change generates this new compiler warning:

Configuring for MPC8308RDB board...
   text	   data	    bss	    dec	    hex	filename
 261821	   6860	 235952	 504633	  7b339	./u-boot
speed.c: In function 'get_clocks':
speed.c:472:16: warning: 'usbdr_clk' may be used uninitialized in this function [-Wuninitialized]

> +++ b/arch/powerpc/include/asm/immap_83xx.h
> @@ -73,12 +73,19 @@ typedef struct sysconf83xx {
>  	u32 obir;		/* Output Buffer Impedance Register */
>  	u8 res8[0xC];
>  	u32 pecr1;		/* PCI Express control register 1 */
> -#ifdef CONFIG_MPC8308
> -	u32 sdhccr;		/* eSDHC Control Registers for MPC8308 */
> +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8309)

MPC830x

> @@ -389,6 +390,86 @@
>  #define SICRH_TSOBI1_V2P5		(1 << 1)
>  #define SICRH_TSOBI2_V3P3		(0 << 0)
>  #define SICRH_TSOBI2_V2P5		(1 << 0)
> +
> +#elif defined(CONFIG_MPC8309)
> +/* SICR_1 */
> +#define SICR_1_UART1_UART1S		(0 << (30-2))
> +#define SICR_1_UART1_UART1RTS		(1 << (30-2))
> +#define SICR_1_I2C_I2C			(0 << (30-4))
> +#define SICR_1_I2C_CKSTOP		(1 << (30-4))
> +#define SICR_1_IRQ_A_IRQ		(0 << (30-6))
> +#define SICR_1_IRQ_A_MCP		(1 << (30-6))
> +#define SICR_1_IRQ_B_IRQ		(0 << (30-8))
> +#define SICR_1_IRQ_B_CKSTOP		(1 << (30-8))
> +#define SICR_1_GPIO_A_GPIO		(0 << (30-10))
> +#define SICR_1_GPIO_A_SD		(2 << (30-10))
> +#define SICR_1_GPIO_A_DDR		(3 << (30-10))
> +#define SICR_1_GPIO_B_GPIO		(0 << (30-12))
> +#define SICR_1_GPIO_B_SD		(2 << (30-12))
> +#define SICR_1_GPIO_B_QE		(3 << (30-12))
> +#define SICR_1_GPIO_C_GPIO		(0 << (30-14))
> +#define SICR_1_GPIO_C_CAN		(1 << (30-14))
> +#define SICR_1_GPIO_C_DDR		(2 << (30-14))
> +#define SICR_1_GPIO_C_LCS		(3 << (30-14))
> +#define SICR_1_GPIO_D_GPIO		(0 << (30-16))
> +#define SICR_1_GPIO_D_CAN		(1 << (30-16))
> +#define SICR_1_GPIO_D_DDR		(2 << (30-16))
> +#define SICR_1_GPIO_D_LCS		(3 << (30-16))
> +#define SICR_1_GPIO_E_GPIO		(0 << (30-18))
> +#define SICR_1_GPIO_E_CAN		(1 << (30-18))
> +#define SICR_1_GPIO_E_DDR		(2 << (30-18))
> +#define SICR_1_GPIO_E_LCS		(3 << (30-18))
> +#define SICR_1_GPIO_F_GPIO		(0 << (30-20))
> +#define SICR_1_GPIO_F_CAN		(1 << (30-20))
> +#define SICR_1_GPIO_F_CK		(2 << (30-20))
> +#define SICR_1_USB_A_USBDR		(0 << (30-22))
> +#define SICR_1_USB_A_UART2S		(1 << (30-22))
> +#define SICR_1_USB_B_USBDR		(0 << (30-24))
> +#define SICR_1_USB_B_UART2S		(1 << (30-24))
> +#define SICR_1_USB_B_UART2RTS		(2 << (30-24))
> +#define SICR_1_USB_C_USBDR		(0 << (30-26))
> +#define SICR_1_USB_C_QE_EXT		(3 << (30-26))
> +#define SICR_1_FEC1_FEC1		(0 << (30-28))
> +#define SICR_1_FEC1_GTM			(1 << (30-28))
> +#define SICR_1_FEC1_GPIO		(2 << (30-28))
> +#define SICR_1_FEC2_FEC2		(0 << (30-30))
> +#define SICR_1_FEC2_GTM			(1 << (30-30))
> +#define SICR_1_FEC2_GPIO		(2 << (30-30))
> +/* SICR_2 */
> +#define SICR_2_FEC3_FEC3		(0 << (30-0))
> +#define SICR_2_FEC3_TMR			(1 << (30-0))
> +#define SICR_2_FEC3_GPIO		(2 << (30-0))
> +#define SICR_2_HDLC1_A_HDLC1		(0 << (30-2))
> +#define SICR_2_HDLC1_A_GPIO		(1 << (30-2))
> +#define SICR_2_HDLC1_A_TDM1		(2 << (30-2))
> +#define SICR_2_ELBC_A_LA		(0 << (30-4))
> +#define SICR_2_ELBC_B_LCLK		(0 << (30-6))
> +#define SICR_2_HDLC2_A_HDLC2		(0 << (30-8))
> +#define SICR_2_HDLC2_A_GPIO		(0 << (30-8))
> +#define SICR_2_HDLC2_A_TDM2		(0 << (30-8))
> +/* bits 10-11 unused */
> +#define SICR_2_USB_D_USBDR		(0 << (30-12))
> +#define SICR_2_USB_D_GPIO		(2 << (30-12))
> +#define SICR_2_USB_D_QE_BRG		(3 << (30-12))
> +#define SICR_2_PCI_PCI			(0 << (30-14))
> +#define SICR_2_PCI_CPCI_HS		(2 << (30-14))
> +#define SICR_2_HDLC1_B_HDLC1		(0 << (30-16))
> +#define SICR_2_HDLC1_B_GPIO		(1 << (30-16))
> +#define SICR_2_HDLC1_B_QE_BRG		(2 << (30-16))
> +#define SICR_2_HDLC1_B_TDM1		(3 << (30-16))
> +#define SICR_2_HDLC1_C_HDLC1		(0 << (30-18))
> +#define SICR_2_HDLC1_C_GPIO		(1 << (30-18))
> +#define SICR_2_HDLC1_C_TDM1		(2 << (30-18))
> +#define SICR_2_HDLC2_B_HDLC2		(0 << (30-20))
> +#define SICR_2_HDLC2_B_GPIO		(1 << (30-20))
> +#define SICR_2_HDLC2_B_QE_BRG		(2 << (30-20))
> +#define SICR_2_HDLC2_B_TDM2		(3 << (30-20))
> +#define SICR_2_HDLC2_C_HDLC2		(0 << (30-22))
> +#define SICR_2_HDLC2_C_GPIO		(1 << (30-22))
> +#define SICR_2_HDLC2_C_TDM2		(2 << (30-22))
> +#define SICR_2_HDLC2_C_QE_BRG		(3 << (30-22))
> +#define SICR_2_QUIESCE_B		(0 << (30-24))
> +
>  #endif

was there an inadequacy in the other SoCs' SICRL/H_ naming
convention and/or value definition in this area?  If not, then why
should the 8309 get its own reinvented SICR_1/2_ etc.?  Just looking
for some consistency here...

Kim

[U-Boot] [PATCH v1 2/4] mpc83xx: add support for mpc8309

[Gerlando Falauto]

On 09/27/2012 03:22 AM, Kim Phillips wrote:
> On Wed, 26 Sep 2012 10:28:08 +0200
> Gerlando Falauto<gerlando.falauto@keymile.com>  wrote:
>
>> This processor, though very similar to other members of the
>> PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
>> yet another feature set than any supported sibling.
>>
>> So we add a bunch of new #ifdefs (or complicate the existing ones)
>> to arch/powerpc/cpu/mpc83xx/speed.c.
>>
>> Perhaps it would be worth to refactor the whole file so to first
>> identify the featureset of the given CPU, and enclose each block within
>>   #ifdef CONFIG_MPC83XX_FEAT_XXXX
>> for instance:
>>   - CONFIG_MPC83XX_FEAT_USBDR
>
> this is CONFIG_HAS_FSL_DR_USB
>
>>   - CONFIG_MPC83XX_FEAT_QE
>
> this could be CONFIG_QE but should probably be CONFIG_HAS_FSL_QE
> which doesn't exist.

Assuming we keep CONFIG_QE, do you think that could replace the whole:

#if defined(CONFIG_MPC8309) || defined(CONFIG_MPC8360) || 
defined(CONFIG_MPC832x)

which I am not very happy with?

>>   - CONFIG_MPC83XX_FEAT_DDRSEC
>> ...etc...
>
> it still wouldn't help that much with the cases like one SoC getting
> its tsec clock from somewhere completely different than the others.

It doesn't have to cover all cases, but some simplification could still 
be an improvement, I think.

> Plus, the mpc8309 should be the last of the Mohicans...

I'll take your word for it. :-)
Well in that case it's not so crucial then.

>> @@ -120,14 +122,17 @@ int get_clocks(void)
>>   #if defined(CONFIG_FSL_ESDHC)
>>   	u32 sdhc_clk;
>>   #endif
>> +#if !defined(CONFIG_MPC8309)
>>   	u32 enc_clk;
>> +#endif
>
> the 8309 is supposed to be similar to the 8308, which also doesn't
> have enc_clk (even though it doesn't do this).  I'm thinking
> CONFIG_MPC8308 should be renamed _MPC830x before adding support for
> the 8309.

Wouldn't that be confusing? The way I understand it we'd also need some 
way to distinguish between the two, so we'd have:

#define CONFIG_MPC83xx          1
#define CONFIG_MPC830x		1
#define CONFIG_MPC8309          1

Plus (assuming my patch is functionally correct), there's only a couple 
of occurences of:

#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8309)

>> @@ -457,6 +470,8 @@ int get_clocks(void)
>>   	gd->tsec1_clk = tsec1_clk;
>>   	gd->tsec2_clk = tsec2_clk;
>>   	gd->usbdr_clk = usbdr_clk;
>> +#elif defined(CONFIG_MPC8309)
>> +	gd->usbdr_clk = usbdr_clk;
>>   #endif
>
> this change generates this new compiler warning:
>
> Configuring for MPC8308RDB board...
>     text	   data	    bss	    dec	    hex	filename
>   261821	   6860	 235952	 504633	  7b339	./u-boot
> speed.c: In function 'get_clocks':
> speed.c:472:16: warning: 'usbdr_clk' may be used uninitialized in this function [-Wuninitialized]

Actually it's this one:

@@ -185,7 +190,10 @@ int get_clocks(void)
                 /* unkown SCCR_TSEC1CM value */
                 return -2;
         }
+#endif

+#if defined(CONFIG_MPC8309) || defined(CONFIG_MPC831x) || \
+       defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
         switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
         case 0:
                 usbdr_clk = 0;

where the code gets dropped in the case of 8308.
So, do you think CONFIG_HAS_FSL_DR_USB would do the trick in that case?

>
>> +++ b/arch/powerpc/include/asm/immap_83xx.h
>> @@ -73,12 +73,19 @@ typedef struct sysconf83xx {
>>   	u32 obir;		/* Output Buffer Impedance Register */
>>   	u8 res8[0xC];
>>   	u32 pecr1;		/* PCI Express control register 1 */
>> -#ifdef CONFIG_MPC8308
>> -	u32 sdhccr;		/* eSDHC Control Registers for MPC8308 */
>> +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8309)
>
> MPC830x

See above.

>
>> @@ -389,6 +390,86 @@
>>   #define SICRH_TSOBI1_V2P5		(1<<  1)
>>   #define SICRH_TSOBI2_V3P3		(0<<  0)
>>   #define SICRH_TSOBI2_V2P5		(1<<  0)
>> +
>> +#elif defined(CONFIG_MPC8309)
>> +/* SICR_1 */
>> +#define SICR_1_UART1_UART1S		(0<<  (30-2))
>> +#define SICR_1_UART1_UART1RTS		(1<<  (30-2))
>> +#define SICR_1_I2C_I2C			(0<<  (30-4))
>> +#define SICR_1_I2C_CKSTOP		(1<<  (30-4))
>> +#define SICR_1_IRQ_A_IRQ		(0<<  (30-6))
>> +#define SICR_1_IRQ_A_MCP		(1<<  (30-6))
>> +#define SICR_1_IRQ_B_IRQ		(0<<  (30-8))
>> +#define SICR_1_IRQ_B_CKSTOP		(1<<  (30-8))
>> +#define SICR_1_GPIO_A_GPIO		(0<<  (30-10))
>> +#define SICR_1_GPIO_A_SD		(2<<  (30-10))
>> +#define SICR_1_GPIO_A_DDR		(3<<  (30-10))
>> +#define SICR_1_GPIO_B_GPIO		(0<<  (30-12))
>> +#define SICR_1_GPIO_B_SD		(2<<  (30-12))
>> +#define SICR_1_GPIO_B_QE		(3<<  (30-12))
>> +#define SICR_1_GPIO_C_GPIO		(0<<  (30-14))
>> +#define SICR_1_GPIO_C_CAN		(1<<  (30-14))
>> +#define SICR_1_GPIO_C_DDR		(2<<  (30-14))
>> +#define SICR_1_GPIO_C_LCS		(3<<  (30-14))
>> +#define SICR_1_GPIO_D_GPIO		(0<<  (30-16))
>> +#define SICR_1_GPIO_D_CAN		(1<<  (30-16))
>> +#define SICR_1_GPIO_D_DDR		(2<<  (30-16))
>> +#define SICR_1_GPIO_D_LCS		(3<<  (30-16))
>> +#define SICR_1_GPIO_E_GPIO		(0<<  (30-18))
>> +#define SICR_1_GPIO_E_CAN		(1<<  (30-18))
>> +#define SICR_1_GPIO_E_DDR		(2<<  (30-18))
>> +#define SICR_1_GPIO_E_LCS		(3<<  (30-18))
>> +#define SICR_1_GPIO_F_GPIO		(0<<  (30-20))
>> +#define SICR_1_GPIO_F_CAN		(1<<  (30-20))
>> +#define SICR_1_GPIO_F_CK		(2<<  (30-20))
>> +#define SICR_1_USB_A_USBDR		(0<<  (30-22))
>> +#define SICR_1_USB_A_UART2S		(1<<  (30-22))
>> +#define SICR_1_USB_B_USBDR		(0<<  (30-24))
>> +#define SICR_1_USB_B_UART2S		(1<<  (30-24))
>> +#define SICR_1_USB_B_UART2RTS		(2<<  (30-24))
>> +#define SICR_1_USB_C_USBDR		(0<<  (30-26))
>> +#define SICR_1_USB_C_QE_EXT		(3<<  (30-26))
>> +#define SICR_1_FEC1_FEC1		(0<<  (30-28))
>> +#define SICR_1_FEC1_GTM			(1<<  (30-28))
>> +#define SICR_1_FEC1_GPIO		(2<<  (30-28))
>> +#define SICR_1_FEC2_FEC2		(0<<  (30-30))
>> +#define SICR_1_FEC2_GTM			(1<<  (30-30))
>> +#define SICR_1_FEC2_GPIO		(2<<  (30-30))
>> +/* SICR_2 */
>> +#define SICR_2_FEC3_FEC3		(0<<  (30-0))
>> +#define SICR_2_FEC3_TMR			(1<<  (30-0))
>> +#define SICR_2_FEC3_GPIO		(2<<  (30-0))
>> +#define SICR_2_HDLC1_A_HDLC1		(0<<  (30-2))
>> +#define SICR_2_HDLC1_A_GPIO		(1<<  (30-2))
>> +#define SICR_2_HDLC1_A_TDM1		(2<<  (30-2))
>> +#define SICR_2_ELBC_A_LA		(0<<  (30-4))
>> +#define SICR_2_ELBC_B_LCLK		(0<<  (30-6))
>> +#define SICR_2_HDLC2_A_HDLC2		(0<<  (30-8))
>> +#define SICR_2_HDLC2_A_GPIO		(0<<  (30-8))
>> +#define SICR_2_HDLC2_A_TDM2		(0<<  (30-8))
>> +/* bits 10-11 unused */
>> +#define SICR_2_USB_D_USBDR		(0<<  (30-12))
>> +#define SICR_2_USB_D_GPIO		(2<<  (30-12))
>> +#define SICR_2_USB_D_QE_BRG		(3<<  (30-12))
>> +#define SICR_2_PCI_PCI			(0<<  (30-14))
>> +#define SICR_2_PCI_CPCI_HS		(2<<  (30-14))
>> +#define SICR_2_HDLC1_B_HDLC1		(0<<  (30-16))
>> +#define SICR_2_HDLC1_B_GPIO		(1<<  (30-16))
>> +#define SICR_2_HDLC1_B_QE_BRG		(2<<  (30-16))
>> +#define SICR_2_HDLC1_B_TDM1		(3<<  (30-16))
>> +#define SICR_2_HDLC1_C_HDLC1		(0<<  (30-18))
>> +#define SICR_2_HDLC1_C_GPIO		(1<<  (30-18))
>> +#define SICR_2_HDLC1_C_TDM1		(2<<  (30-18))
>> +#define SICR_2_HDLC2_B_HDLC2		(0<<  (30-20))
>> +#define SICR_2_HDLC2_B_GPIO		(1<<  (30-20))
>> +#define SICR_2_HDLC2_B_QE_BRG		(2<<  (30-20))
>> +#define SICR_2_HDLC2_B_TDM2		(3<<  (30-20))
>> +#define SICR_2_HDLC2_C_HDLC2		(0<<  (30-22))
>> +#define SICR_2_HDLC2_C_GPIO		(1<<  (30-22))
>> +#define SICR_2_HDLC2_C_TDM2		(2<<  (30-22))
>> +#define SICR_2_HDLC2_C_QE_BRG		(3<<  (30-22))
>> +#define SICR_2_QUIESCE_B		(0<<  (30-24))
>> +
>>   #endif
>
> was there an inadequacy in the other SoCs' SICRL/H_ naming
> convention and/or value definition in this area?  If not, then why
> should the 8309 get its own reinvented SICR_1/2_ etc.?

As for the naming, I used SICR_1/2 as opposed to SICRL/H because that's 
how the registers are called in the datasheet.
As for the value definition, I added my own (third, at least!) 
convention so to match the bit numbering in the datasheet.
This should makes double checking a trivial task.

 > Just looking for some consistency here...

Thanks a lot for your review!
Gerlando

[U-Boot] [PATCH v1 2/4] mpc83xx: add support for mpc8309

[Kim Phillips]

On Thu, 27 Sep 2012 09:21:19 +0200
Gerlando Falauto <gerlando.falauto@keymile.com> wrote:

> On 09/27/2012 03:22 AM, Kim Phillips wrote:
> > On Wed, 26 Sep 2012 10:28:08 +0200
> > Gerlando Falauto<gerlando.falauto@keymile.com>  wrote:
> >
> >>   - CONFIG_MPC83XX_FEAT_QE
> >
> > this could be CONFIG_QE but should probably be CONFIG_HAS_FSL_QE
> > which doesn't exist.
> 
> Assuming we keep CONFIG_QE, do you think that could replace the whole:
> 
> #if defined(CONFIG_MPC8309) || defined(CONFIG_MPC8360) || 
> defined(CONFIG_MPC832x)
> 
> which I am not very happy with?

sure, since that's what's protecting qe_clk in asm/global_data.h.

> >> @@ -120,14 +122,17 @@ int get_clocks(void)
> >>   #if defined(CONFIG_FSL_ESDHC)
> >>   	u32 sdhc_clk;
> >>   #endif
> >> +#if !defined(CONFIG_MPC8309)
> >>   	u32 enc_clk;
> >> +#endif
> >
> > the 8309 is supposed to be similar to the 8308, which also doesn't
> > have enc_clk (even though it doesn't do this).  I'm thinking
> > CONFIG_MPC8308 should be renamed _MPC830x before adding support for
> > the 8309.
> 
> Wouldn't that be confusing? The way I understand it we'd also need some 
> way to distinguish between the two, so we'd have:
> 
> #define CONFIG_MPC83xx          1
> #define CONFIG_MPC830x		1
> #define CONFIG_MPC8309          1

yes, I didn't mean all 8308 be renamed, only the relevant ones here.

> Plus (assuming my patch is functionally correct), there's only a couple 
> of occurences of:
> 
> #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8309)

so far the 8308 and the 8360 are the only SoCs that don't have a
'tens'/MPC83Xx defines.  The 8360 can get away with it, since it's
very close to the 8358 (and we can avoid that marketing-imposed
snafu).  The 8308 and 9 are more different (QE vs TSEC), but as seen
here, there are other commonalities.

> >> @@ -457,6 +470,8 @@ int get_clocks(void)
> >>   	gd->tsec1_clk = tsec1_clk;
> >>   	gd->tsec2_clk = tsec2_clk;
> >>   	gd->usbdr_clk = usbdr_clk;
> >> +#elif defined(CONFIG_MPC8309)
> >> +	gd->usbdr_clk = usbdr_clk;
> >>   #endif
> >
> > this change generates this new compiler warning:
> >
> > Configuring for MPC8308RDB board...
> >     text	   data	    bss	    dec	    hex	filename
> >   261821	   6860	 235952	 504633	  7b339	./u-boot
> > speed.c: In function 'get_clocks':
> > speed.c:472:16: warning: 'usbdr_clk' may be used uninitialized in this function [-Wuninitialized]
> 
> Actually it's this one:
> 
> @@ -185,7 +190,10 @@ int get_clocks(void)
>                  /* unkown SCCR_TSEC1CM value */
>                  return -2;
>          }
> +#endif
> 
> +#if defined(CONFIG_MPC8309) || defined(CONFIG_MPC831x) || \
> +       defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
>          switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
>          case 0:
>                  usbdr_clk = 0;
> 
> where the code gets dropped in the case of 8308.
> So, do you think CONFIG_HAS_FSL_DR_USB would do the trick in that case?

now that I take a closer look, not all 831/4/7x boards set
HAS_FSL_DR_USB, and I'm afraid that might break something.

But I also think MPC830x would do the trick nicely, since it'd be
a step toward 8308 usb enablement.

> >> +#define SICR_2_QUIESCE_B		(0<<  (30-24))
> >> +
> >>   #endif
> >
> > was there an inadequacy in the other SoCs' SICRL/H_ naming
> > convention and/or value definition in this area?  If not, then why
> > should the 8309 get its own reinvented SICR_1/2_ etc.?
> 
> As for the naming, I used SICR_1/2 as opposed to SICRL/H because that's 
> how the registers are called in the datasheet.

Hadn't realized that.  Wunderbar.  I suppose documentation people
don't need to have the same sense of consistency we do.

> As for the value definition, I added my own (third, at least!) 
> convention so to match the bit numbering in the datasheet.
> This should makes double checking a trivial task.

I suppose, as I say:

>  > Just looking for some consistency here...

but, ok - SICRs aren't used that much and we're at the end of the
83xx line.

> Thanks a lot for your review!

Cheers,

Kim

[U-Boot] [PATCH v1 2/4] mpc83xx: add support for mpc8309

[Gerlando Falauto]

On 09/28/2012 01:18 AM, Kim Phillips wrote:
> On Thu, 27 Sep 2012 09:21:19 +0200
> Gerlando Falauto<gerlando.falauto@keymile.com>  wrote:
>
>> On 09/27/2012 03:22 AM, Kim Phillips wrote:
[...]
> so far the 8308 and the 8360 are the only SoCs that don't have a
> 'tens'/MPC83Xx defines.  The 8360 can get away with it, since it's
> very close to the 8358 (and we can avoid that marketing-imposed
> snafu).  The 8308 and 9 are more different (QE vs TSEC), but as seen
> here, there are other commonalities.

I personally don't think adding a new 830x symbol would lead to that 
much saving. Plus it should be the last one of the series so there won't 
be much use in the future either.
So unless you think that's absolutely necessary, I'd submit a v2 without 
this.

Thanks again,
Gerlando

[U-Boot] [PATCH v1 2/4] mpc83xx: add support for mpc8309

[Kim Phillips]

On Fri, 28 Sep 2012 16:08:39 +0200
Gerlando Falauto <gerlando.falauto@keymile.com> wrote:

> On 09/28/2012 01:18 AM, Kim Phillips wrote:
> > On Thu, 27 Sep 2012 09:21:19 +0200
> > Gerlando Falauto<gerlando.falauto@keymile.com>  wrote:
> >
> >> On 09/27/2012 03:22 AM, Kim Phillips wrote:
> [...]
> > so far the 8308 and the 8360 are the only SoCs that don't have a
> > 'tens'/MPC83Xx defines.  The 8360 can get away with it, since it's
> > very close to the 8358 (and we can avoid that marketing-imposed
> > snafu).  The 8308 and 9 are more different (QE vs TSEC), but as seen
> > here, there are other commonalities.
> 
> I personally don't think adding a new 830x symbol would lead to that 
> much saving. Plus it should be the last one of the series so there won't 
> be much use in the future either.
> So unless you think that's absolutely necessary, I'd submit a v2 without 
> this.

I must be missing something - wouldn't it benefit things like
SCCR_USBDRCM for the 8308, which is still being actively developed?

Kim

[U-Boot] [PATCH v1 3/4] km83xx: add common support for km8309 boards

[Gerlando Falauto]

Add support for Keymile boards based on mpc8309
(it would be only kmvect1 for now)

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
---
 board/keymile/km83xx/km83xx.c      |    2 +-
 include/configs/km/km8309-common.h |  174 ++++++++++++++++++++++++++++++++++++
 include/configs/km/km83xx-common.h |    6 ++
 3 files changed, 181 insertions(+), 1 deletion(-)
 create mode 100644 include/configs/km/km8309-common.h

diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index e01a633..83a8753 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -56,7 +56,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{5,  2, 1, 0, 1}, /* UART2_RTS */
 	{5,  3, 2, 0, 2}, /* UART2_SIN */
 	{5,  1, 2, 0, 3}, /* UART2_CTS */
-#else
+#elif !defined(CONFIG_MPC8309)
 	/* Local Bus */
 	{0, 16, 1, 0, 3}, /* LA00 */
 	{0, 17, 1, 0, 3}, /* LA01 */
diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h
new file mode 100644
index 0000000..cfb8c96
--- /dev/null
+++ b/include/configs/km/km8309-common.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2012 Keymile AG
+ *                    Gerlando Falauto <gerlando.falauto@keymile.com>
+ *
+ * Based on km8321-common.h, see respective copyright notice for credits
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_KM8309_COMMON_H
+#define __CONFIG_KM8309_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 family */
+#define CONFIG_QE		1	/* Has QE */
+#define CONFIG_MPC83xx		1	/* MPC83xx family */
+#define CONFIG_MPC8309		1	/* MPC8309 CPU specific */
+
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_8xx\0"
+#define CONFIG_CMD_DIAG		1
+
+/* include common defines/options for all 83xx Keymile boards */
+#include "km83xx-common.h"
+
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+/* at end of uboot partition, before env */
+#define CONFIG_SYS_QE_FMAN_FW_ADDR   0xF00B0000
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * System IO Config
+ */
+/* 0x14000180 SICR_1 */
+#define CONFIG_SYS_SICRL ( 0			\
+		| SICR_1_UART1_UART1RTS		\
+		| SICR_1_I2C_CKSTOP		\
+		| SICR_1_IRQ_A_IRQ		\
+		| SICR_1_IRQ_B_IRQ		\
+		| SICR_1_GPIO_A_GPIO		\
+		| SICR_1_GPIO_B_GPIO		\
+		| SICR_1_GPIO_C_GPIO		\
+		| SICR_1_GPIO_D_GPIO		\
+		| SICR_1_GPIO_E_GPIO		\
+		| SICR_1_GPIO_F_GPIO		\
+		| SICR_1_USB_A_UART2S		\
+		| SICR_1_USB_B_UART2RTS		\
+		| SICR_1_FEC1_FEC1		\
+		| SICR_1_FEC2_FEC2		\
+               )
+
+/* 0x00080400 SICR_2 */
+#define CONFIG_SYS_SICRH ( 0			\
+		| SICR_2_FEC3_FEC3		\
+		| SICR_2_HDLC1_A_HDLC1		\
+		| SICR_2_ELBC_A_LA		\
+		| SICR_2_ELBC_B_LCLK		\
+		| SICR_2_HDLC2_A_HDLC2		\
+		| SICR_2_USB_D_GPIO		\
+		| SICR_2_PCI_PCI		\
+		| SICR_2_HDLC1_B_HDLC1		\
+		| SICR_2_HDLC1_C_HDLC1		\
+		| SICR_2_HDLC2_B_GPIO		\
+		| SICR_2_HDLC2_C_HDLC2		\
+		| SICR_2_QUIESCE_B		\
+               )
+
+#define CONFIG_SYS_GPR1  0x50008060 // GPR_1
+
+#define CONFIG_SYS_GP1DIR 0x00000000
+#define CONFIG_SYS_GP1ODR 0x00000000
+#define CONFIG_SYS_GP2DIR 0xFF000000
+#define CONFIG_SYS_GP2ODR 0x00000000
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
+	HRCWL_DDR_TO_SCB_CLK_2X1 | \
+	HRCWL_CSB_TO_CLKIN_2X1 | \
+	HRCWL_CORE_TO_CSB_2X1 | \
+	HRCWL_CE_PLL_VCO_DIV_2 | \
+	HRCWL_CE_TO_PLL_1X3)
+
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_AGENT | \
+	HRCWH_PCI_ARBITER_DISABLE | \
+	HRCWH_CORE_ENABLE | \
+	HRCWH_FROM_0X00000100 | \
+	HRCWH_BOOTSEQ_DISABLE | \
+	HRCWH_SW_WATCHDOG_DISABLE | \
+	HRCWH_ROM_LOC_LOCAL_16BIT | \
+	HRCWH_BIG_ENDIAN | \
+	HRCWH_LALE_NORMAL)
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+					 SDRAM_CFG_32_BE | \
+					 SDRAM_CFG_SREN | \
+					 SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+					 CSCONFIG_ODT_RD_NEVER | \
+					 CSCONFIG_ODT_WR_ONLY_CURRENT | \
+					 CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE	0x47860242
+#define CONFIG_SYS_DDR_MODE2	0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP	0x80000000
+#define CONFIG_SYS_LCRR_EADC	0x00010000
+#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
+
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#endif /* __CONFIG_KM8309_COMMON_H */
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index 877d841..f1f5815 100644
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -169,9 +169,15 @@
 #define UEC_VERBOSE_DEBUG	1
 
 #ifdef CONFIG_UEC_ETH1
+#if defined (CONFIG_MPC8309)
+#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK12
+#else
 #define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
 #define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
+#endif
 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	0
 #define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
-- 
1.7.10.1

[U-Boot] [PATCH v1 4/4] km83xx: add kmvect1 board

[Gerlando Falauto]

Add support for the new kmvect1 board powered by the mpc8309 processor.
As this board is very similar to the existing suvd3, instead of adding a
new config header file, just add a new config option to suvd3.h

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
---
 boards.cfg              |    3 ++-
 include/configs/suvd3.h |   15 ++++++++++++---
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index 1af87c0..28b0091 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -639,7 +639,8 @@ MVBLM7                       powerpc     mpc83xx     mvblm7              matrix_
 SIMPC8313_LP                 powerpc     mpc83xx     simpc8313           sheldon        -           SIMPC8313:NAND_LP
 SIMPC8313_SP                 powerpc     mpc83xx     simpc8313           sheldon        -           SIMPC8313:NAND_SP
 TQM834x                      powerpc     mpc83xx     tqm834x             tqc
-suvd3                        powerpc     mpc83xx     km83xx              keymile
+suvd3                        powerpc     mpc83xx     km83xx              keymile        -           suvd3:SUVD3
+kmvect1                      powerpc     mpc83xx     km83xx              keymile        -           suvd3:KMVECT1
 tuge1                        powerpc     mpc83xx     km83xx              keymile        -           tuxx1:KM_DISABLE_APP2,TUGE1
 tuxx1                        powerpc     mpc83xx     km83xx              keymile
 kmsupx5                      powerpc     mpc83xx     km83xx              keymile        -           tuxx1:KM_DISABLE_APP2,KMSUPX5
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 68680c5..c50832c 100644
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -23,14 +23,23 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_SUVD3		/* SUVD3 board specific */
-#define CONFIG_HOSTNAME		suvd3
-#define CONFIG_KM_BOARD_NAME   "suvd3"
 
+/* This needs to be set prior to including km/km83xx-common.h */
 #define	CONFIG_SYS_TEXT_BASE	0xF0000000
 
+#if defined(CONFIG_SUVD3)	/* SUVD3 board specific */
+#define CONFIG_HOSTNAME		suvd3
+#define CONFIG_KM_BOARD_NAME   "suvd3"
 /* include common defines/options for all 8321 Keymile boards */
 #include "km/km8321-common.h"
+#elif defined(CONFIG_KMVECT1)   /* VECT1 board specific */
+#define CONFIG_HOSTNAME		kmvect1
+#define CONFIG_KM_BOARD_NAME   "kmvect1"
+/* include common defines/options for all 8309 Keymile boards */
+#include "km/km8309-common.h"
+#else
+#error Supported boards are: SUVD3, KMVECT1
+#endif
 
 #define CONFIG_SYS_APP1_BASE		0xA0000000
 #define CONFIG_SYS_APP1_SIZE		256 /* Megabytes */
-- 
1.7.10.1

[U-Boot] [PATCH v2 0/6] introducing vect1: mpc8309 keymile board

[Gerlando Falauto]

This patch series adds support for VECT1, an mpc8309-powered Keymile board.
MPC8309 is not currently supported by u-boot, so we first add support for
this processor.
VECT1 is somewhat similar to suvd3, albeit powered by a different processor,
so we use its config file as opposed to introducing a new one.

Difference from v1:
 - added preliminary cleanup patches #2/3 to simplify #if conditions in speed.c
 - fixed #ifdef so to restore code block assigning to usbdr_clk
 - removed checkpatch errors

Gerlando Falauto (6):
  cosmetic: suvd3: align #defines
  cleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832x
  cleanup: introduce CONFIG_MPC830x
  mpc83xx: add support for mpc8309
  km83xx: add common support for km8309 boards
  km83xx: add kmvect1 board

 arch/powerpc/cpu/mpc83xx/cpu.c         |    1 +
 arch/powerpc/cpu/mpc83xx/cpu_init.c    |    3 +
 arch/powerpc/cpu/mpc83xx/speed.c       |   27 ++++-
 arch/powerpc/include/asm/global_data.h |    2 +
 arch/powerpc/include/asm/immap_83xx.h  |   65 +++++++++++-
 arch/powerpc/include/asm/immap_qe.h    |    2 +-
 board/keymile/km83xx/km83xx.c          |    2 +-
 boards.cfg                             |    3 +-
 drivers/qe/qe.c                        |   21 ++--
 include/configs/MPC8308RDB.h           |    1 +
 include/configs/km/km8309-common.h     |  176 ++++++++++++++++++++++++++++++++
 include/configs/km/km8321-common.h     |    2 +-
 include/configs/km/km83xx-common.h     |    6 ++
 include/configs/mpc8308_p1m.h          |    1 +
 include/configs/suvd3.h                |   19 +++-
 include/mpc83xx.h                      |  155 +++++++++++++++++++++++++++-
 16 files changed, 461 insertions(+), 25 deletions(-)
 create mode 100644 include/configs/km/km8309-common.h

-- 
1.7.10.1

[U-Boot] [PATCH v2 1/6] cosmetic: suvd3: align #defines

[Gerlando Falauto]

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
---
 include/configs/km/km8321-common.h |    2 +-
 include/configs/suvd3.h            |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h
index 580b72f..8ad6fc3 100644
--- a/include/configs/km/km8321-common.h
+++ b/include/configs/km/km8321-common.h
@@ -115,7 +115,7 @@
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 
 #define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
-#define	CONFIG_SYS_KMBEC_FPGA_SIZE	128
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
 
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index ae19701..68680c5 100644
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -33,9 +33,9 @@
 #include "km/km8321-common.h"
 
 #define CONFIG_SYS_APP1_BASE		0xA0000000
-#define	CONFIG_SYS_APP1_SIZE		256 /* Megabytes */
+#define CONFIG_SYS_APP1_SIZE		256 /* Megabytes */
 #define CONFIG_SYS_APP2_BASE		0xB0000000
-#define	CONFIG_SYS_APP2_SIZE		256 /* Megabytes */
+#define CONFIG_SYS_APP2_SIZE		256 /* Megabytes */
 
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-- 
1.7.10.1

[U-Boot] [PATCH v2 2/6] cleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832x

[Gerlando Falauto]

simplify #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
for qe variables
with #if defined(CONFIG_QE)

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
---
 arch/powerpc/cpu/mpc83xx/speed.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index f78099d..3383568 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -127,7 +127,7 @@ int get_clocks(void)
 #if defined(CONFIG_MPC8360)
 	u32 mem_sec_clk;
 #endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
 	u32 qepmf;
 	u32 qepdf;
 	u32 qe_clk;
@@ -444,7 +444,7 @@ int get_clocks(void)
 		return -13;
 	}
 
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
 	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
 	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
 	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
@@ -479,7 +479,7 @@ int get_clocks(void)
 #if defined(CONFIG_MPC8360)
 	gd->mem_sec_clk = mem_sec_clk;
 #endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
 	gd->qe_clk = qe_clk;
 	gd->brg_clk = brg_clk;
 #endif
@@ -523,7 +523,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 	printf("Clock configuration:\n");
 	printf("  Core:                %-4s MHz\n", strmhz(buf, gd->core_clk));
 	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
 	printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
 	printf("  BRG:                 %-4s MHz\n", strmhz(buf, gd->brg_clk));
 #endif
-- 
1.7.10.1

[U-Boot] [PATCH v2 3/6] cleanup: introduce CONFIG_MPC830x

[Gerlando Falauto]

Introduce a new configuration token CONFIG_MPC830x to be shared among
mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor
existing common code so to make future introduction of 8309 simpler.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
---
 arch/powerpc/cpu/mpc83xx/speed.c      |    3 +++
 arch/powerpc/include/asm/immap_83xx.h |    4 ++--
 include/configs/MPC8308RDB.h          |    1 +
 include/configs/mpc8308_p1m.h         |    1 +
 include/mpc83xx.h                     |    2 +-
 5 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 3383568..4ad3ec3 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -185,7 +185,10 @@ int get_clocks(void)
 		/* unkown SCCR_TSEC1CM value */
 		return -2;
 	}
+#endif
 
+#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
 	case 0:
 		usbdr_clk = 0;
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 2ba502a..b7d4c59 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -73,8 +73,8 @@ typedef struct sysconf83xx {
 	u32 obir;		/* Output Buffer Impedance Register */
 	u8 res8[0xC];
 	u32 pecr1;		/* PCI Express control register 1 */
-#ifdef CONFIG_MPC8308
-	u32 sdhccr;		/* eSDHC Control Registers for MPC8308 */
+#if defined(CONFIG_MPC830x)
+	u32 sdhccr;		/* eSDHC Control Registers for MPC830x */
 #else
 	u32 pecr2;		/* PCI Express control register 2 */
 #endif
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 2d48dde..ed62608 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -30,6 +30,7 @@
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_MPC83xx		1 /* MPC83xx family */
+#define CONFIG_MPC830x		1 /* MPC830x family */
 #define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
 #define CONFIG_MPC8308RDB	1 /* MPC8308RDB board specific */
 
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 806ed64..dd249b0 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -30,6 +30,7 @@
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_MPC83xx		1 /* MPC83xx family */
+#define CONFIG_MPC830x		1 /* MPC830x family */
 #define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
 #define CONFIG_MPC8308_P1M	1 /* mpc8308_p1m board specific */
 
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index a78f1a2..7a19740 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -969,7 +969,7 @@
  */
 #define CSCONFIG_EN			0x80000000
 #define CSCONFIG_AP			0x00800000
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x)
 #define CSCONFIG_ODT_RD_NEVER		0x00000000
 #define CSCONFIG_ODT_RD_ONLY_CURRENT	0x00100000
 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS	0x00200000
-- 
1.7.10.1

[U-Boot] [PATCH v2 4/6] mpc83xx: add support for mpc8309

[Gerlando Falauto]

This processor, though very similar to other members of the
PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
yet another feature set than any supported sibling.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
---
 arch/powerpc/cpu/mpc83xx/cpu.c         |    1 +
 arch/powerpc/cpu/mpc83xx/cpu_init.c    |    3 +
 arch/powerpc/cpu/mpc83xx/speed.c       |   16 ++++
 arch/powerpc/include/asm/global_data.h |    2 +
 arch/powerpc/include/asm/immap_83xx.h  |   61 +++++++++++++
 arch/powerpc/include/asm/immap_qe.h    |    2 +-
 drivers/qe/qe.c                        |   21 +++--
 include/mpc83xx.h                      |  153 ++++++++++++++++++++++++++++++++
 8 files changed, 249 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 6635109..e64b0c3 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -56,6 +56,7 @@ int checkcpu(void)
 		u32 partid;
 	} cpu_type_list [] = {
 		CPU_TYPE_ENTRY(8308),
+		CPU_TYPE_ENTRY(8309),
 		CPU_TYPE_ENTRY(8311),
 		CPU_TYPE_ENTRY(8313),
 		CPU_TYPE_ENTRY(8314),
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 76afba5..20d0600 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -268,6 +268,9 @@ void cpu_init_f (volatile immap_t * im)
 #ifdef CONFIG_SYS_SICRL
 	__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 #endif
+#ifdef CONFIG_SYS_GPR1
+	__raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
+#endif
 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 	__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 #endif
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 4ad3ec3..fb0f7aa 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -105,6 +105,8 @@ int get_clocks(void)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+	u32 usbdr_clk;
 #endif
 #ifdef CONFIG_MPC834x
 	u32 usbmph_clk;
@@ -120,7 +122,9 @@ int get_clocks(void)
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
+#if !defined(CONFIG_MPC8309)
 	u32 enc_clk;
+#endif
 	u32 lbiu_clk;
 	u32 lclk_clk;
 	u32 mem_clk;
@@ -263,6 +267,7 @@ int get_clocks(void)
 		return -6;
 	}
 #endif
+#if !defined(CONFIG_MPC8309)
 	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
 	case 0:
 		enc_clk = 0;
@@ -280,6 +285,7 @@ int get_clocks(void)
 		/* unkown SCCR_ENCCM value */
 		return -7;
 	}
+#endif
 
 #if defined(CONFIG_FSL_ESDHC)
 	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
@@ -332,6 +338,8 @@ int get_clocks(void)
 	i2c1_clk = sdhc_clk;
 #elif defined(CONFIG_MPC837x)
 	i2c1_clk = enc_clk;
+#elif defined(CONFIG_MPC8309)
+	i2c1_clk = csb_clk;
 #endif
 #if !defined(CONFIG_MPC832x)
 	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
@@ -460,6 +468,8 @@ int get_clocks(void)
 	gd->tsec1_clk = tsec1_clk;
 	gd->tsec2_clk = tsec2_clk;
 	gd->usbdr_clk = usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+	gd->usbdr_clk = usbdr_clk;
 #endif
 #if defined(CONFIG_MPC834x)
 	gd->usbmph_clk = usbmph_clk;
@@ -475,7 +485,9 @@ int get_clocks(void)
 #if !defined(CONFIG_MPC832x)
 	gd->i2c2_clk = i2c2_clk;
 #endif
+#if !defined(CONFIG_MPC8309)
 	gd->enc_clk = enc_clk;
+#endif
 	gd->lbiu_clk = lbiu_clk;
 	gd->lclk_clk = lclk_clk;
 	gd->mem_clk = mem_clk;
@@ -536,7 +548,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_MPC8360)
 	printf("  DDR Secondary:       %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
 #endif
+#if !defined(CONFIG_MPC8309)
 	printf("  SEC:                 %-4s MHz\n", strmhz(buf, gd->enc_clk));
+#endif
 	printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
 #if !defined(CONFIG_MPC832x)
 	printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
@@ -552,6 +566,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 	printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
 	printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
 	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+#elif defined(CONFIG_MPC8309)
+	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
 #endif
 #if defined(CONFIG_MPC834x)
 	printf("  USB MPH:             %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 5a5877f..cd4a54a 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -63,6 +63,8 @@ typedef	struct	global_data {
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+	u32 usbdr_clk;
 #endif
 #if defined (CONFIG_MPC834x)
 	u32 usbmph_clk;
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index b7d4c59..679832c 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -78,7 +78,14 @@ typedef struct sysconf83xx {
 #else
 	u32 pecr2;		/* PCI Express control register 2 */
 #endif
+#if defined(CONFIG_MPC8309)
+	u32 can_dbg_ctrl;
+	u32 res9a;
+	u32 gpr1;
+	u8 res9b[0xAC];
+#else
 	u8 res9[0xB8];
+#endif
 } sysconf83xx_t;
 
 /*
@@ -708,7 +715,11 @@ typedef struct serdes83xx {
  * On Chip ROM
  */
 typedef struct rom83xx {
+#if defined(CONFIG_MPC8309)
+	u8 mem[0x8000];
+#else
 	u8 mem[0x10000];
+#endif
 } rom83xx_t;
 
 /*
@@ -972,6 +983,56 @@ typedef struct immap {
 	u8			res8[0xC0000];
 	u8			qe[0x100000];	/* QE block */
 } immap_t;
+#elif defined(CONFIG_MPC8309)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[2];	/* General purpose I/O module */
+	u8			res0[0x500];	/* res0 1.25 KBytes added for 8309 */
+	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
+	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
+	u8			res1[0x800];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res2[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res3[0x200];
+	duart83xx_t		duart1[2];	/* DUART */
+	u8			res4[0x500];
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
+	u8			res5[0x1000];
+	u8			spi[0x100];
+	u8			res6[0xf00];
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Configuration Registers */
+	u8			res7[0x80];
+	ios83xx_t		ios;		/* Sequencer (IOS) */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Control & Status Registers */
+	u8			res8[0x13A00];
+	u8			can1[0x1000];	/* Flexcan 1 */
+	u8			can2[0x1000];	/* Flexcan 2 */
+	u8			res9[0x5000];
+	usb83xx_t		usb;
+	u8			res10[0x5000];
+	u8			can3[0x1000];	/* Flexcan 3 */
+	u8			can4[0x1000];	/* Flexcan 4 */
+	u8			res11[0x1000];
+	u8			dma1[0x2000];	/* DMA */
+	sdhc83xx_t		sdhc;		/* SDHC Controller */
+	u8			res12[0xC1000];
+	rom83xx_t		rom;		/* On Chip ROM */
+	u8			res13[0x8000];
+	u8			qe[0x100000];	/* QE block */
+	u8			res14[0xE00000];/* Added for 8309 */
+} immap_t;
 #endif
 
 #define CONFIG_SYS_MPC83xx_DDR_OFFSET	(0x2000)
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
index 9be9dca..f0b989a 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -20,7 +20,7 @@
 #define QE_MURAM_SIZE		0xc000UL
 #define MAX_QE_RISC		2
 #define QE_NUM_OF_SNUM		28
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
 #define QE_MURAM_SIZE		0x4000UL
 #define MAX_QE_RISC		1
 #define QE_NUM_OF_SNUM		28
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 9f71151..345587b 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -113,18 +113,21 @@ static void qe_sdma_init(void)
  * we just need to know what the SNUMs are for the threads.
  */
 static u8 thread_snum[] = {
+/* Evthreads 16-29 are not supported in MPC8309 */
+#if !defined(CONFIG_MPC8309)
 	0x04, 0x05, 0x0c, 0x0d,
 	0x14, 0x15, 0x1c, 0x1d,
 	0x24, 0x25, 0x2c, 0x2d,
-	0x34, 0x35, 0x88, 0x89,
-	0x98, 0x99, 0xa8, 0xa9,
-	0xb8, 0xb9, 0xc8, 0xc9,
-	0xd8, 0xd9, 0xe8, 0xe9,
-	0x08, 0x09, 0x18, 0x19,
-	0x28, 0x29, 0x38, 0x39,
-	0x48, 0x49, 0x58, 0x59,
-	0x68, 0x69, 0x78, 0x79,
-	0x80, 0x81
+	0x34, 0x35,
+#endif
+	0x88, 0x89, 0x98, 0x99,
+	0xa8, 0xa9, 0xb8, 0xb9,
+	0xc8, 0xc9, 0xd8, 0xd9,
+	0xe8, 0xe9, 0x08, 0x09,
+	0x18, 0x19, 0x28, 0x29,
+	0x38, 0x39, 0x48, 0x49,
+	0x58, 0x59, 0x68, 0x69,
+	0x78, 0x79, 0x80, 0x81
 };
 
 static void qe_snums_init(void)
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 7a19740..b295d6d 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -74,6 +74,7 @@
 #define SPR_FAMILY(spridr)		((spridr & 0xFFF00000) >> 20)
 
 #define SPR_8308			0x8100
+#define SPR_8309			0x8110
 #define SPR_831X_FAMILY			0x80B
 #define SPR_8311			0x80B2
 #define SPR_8313			0x80B0
@@ -389,6 +390,86 @@
 #define SICRH_TSOBI1_V2P5		(1 << 1)
 #define SICRH_TSOBI2_V3P3		(0 << 0)
 #define SICRH_TSOBI2_V2P5		(1 << 0)
+
+#elif defined(CONFIG_MPC8309)
+/* SICR_1 */
+#define SICR_1_UART1_UART1S		(0 << (30-2))
+#define SICR_1_UART1_UART1RTS		(1 << (30-2))
+#define SICR_1_I2C_I2C			(0 << (30-4))
+#define SICR_1_I2C_CKSTOP		(1 << (30-4))
+#define SICR_1_IRQ_A_IRQ		(0 << (30-6))
+#define SICR_1_IRQ_A_MCP		(1 << (30-6))
+#define SICR_1_IRQ_B_IRQ		(0 << (30-8))
+#define SICR_1_IRQ_B_CKSTOP		(1 << (30-8))
+#define SICR_1_GPIO_A_GPIO		(0 << (30-10))
+#define SICR_1_GPIO_A_SD		(2 << (30-10))
+#define SICR_1_GPIO_A_DDR		(3 << (30-10))
+#define SICR_1_GPIO_B_GPIO		(0 << (30-12))
+#define SICR_1_GPIO_B_SD		(2 << (30-12))
+#define SICR_1_GPIO_B_QE		(3 << (30-12))
+#define SICR_1_GPIO_C_GPIO		(0 << (30-14))
+#define SICR_1_GPIO_C_CAN		(1 << (30-14))
+#define SICR_1_GPIO_C_DDR		(2 << (30-14))
+#define SICR_1_GPIO_C_LCS		(3 << (30-14))
+#define SICR_1_GPIO_D_GPIO		(0 << (30-16))
+#define SICR_1_GPIO_D_CAN		(1 << (30-16))
+#define SICR_1_GPIO_D_DDR		(2 << (30-16))
+#define SICR_1_GPIO_D_LCS		(3 << (30-16))
+#define SICR_1_GPIO_E_GPIO		(0 << (30-18))
+#define SICR_1_GPIO_E_CAN		(1 << (30-18))
+#define SICR_1_GPIO_E_DDR		(2 << (30-18))
+#define SICR_1_GPIO_E_LCS		(3 << (30-18))
+#define SICR_1_GPIO_F_GPIO		(0 << (30-20))
+#define SICR_1_GPIO_F_CAN		(1 << (30-20))
+#define SICR_1_GPIO_F_CK		(2 << (30-20))
+#define SICR_1_USB_A_USBDR		(0 << (30-22))
+#define SICR_1_USB_A_UART2S		(1 << (30-22))
+#define SICR_1_USB_B_USBDR		(0 << (30-24))
+#define SICR_1_USB_B_UART2S		(1 << (30-24))
+#define SICR_1_USB_B_UART2RTS		(2 << (30-24))
+#define SICR_1_USB_C_USBDR		(0 << (30-26))
+#define SICR_1_USB_C_QE_EXT		(3 << (30-26))
+#define SICR_1_FEC1_FEC1		(0 << (30-28))
+#define SICR_1_FEC1_GTM			(1 << (30-28))
+#define SICR_1_FEC1_GPIO		(2 << (30-28))
+#define SICR_1_FEC2_FEC2		(0 << (30-30))
+#define SICR_1_FEC2_GTM			(1 << (30-30))
+#define SICR_1_FEC2_GPIO		(2 << (30-30))
+/* SICR_2 */
+#define SICR_2_FEC3_FEC3		(0 << (30-0))
+#define SICR_2_FEC3_TMR			(1 << (30-0))
+#define SICR_2_FEC3_GPIO		(2 << (30-0))
+#define SICR_2_HDLC1_A_HDLC1		(0 << (30-2))
+#define SICR_2_HDLC1_A_GPIO		(1 << (30-2))
+#define SICR_2_HDLC1_A_TDM1		(2 << (30-2))
+#define SICR_2_ELBC_A_LA		(0 << (30-4))
+#define SICR_2_ELBC_B_LCLK		(0 << (30-6))
+#define SICR_2_HDLC2_A_HDLC2		(0 << (30-8))
+#define SICR_2_HDLC2_A_GPIO		(0 << (30-8))
+#define SICR_2_HDLC2_A_TDM2		(0 << (30-8))
+/* bits 10-11 unused */
+#define SICR_2_USB_D_USBDR		(0 << (30-12))
+#define SICR_2_USB_D_GPIO		(2 << (30-12))
+#define SICR_2_USB_D_QE_BRG		(3 << (30-12))
+#define SICR_2_PCI_PCI			(0 << (30-14))
+#define SICR_2_PCI_CPCI_HS		(2 << (30-14))
+#define SICR_2_HDLC1_B_HDLC1		(0 << (30-16))
+#define SICR_2_HDLC1_B_GPIO		(1 << (30-16))
+#define SICR_2_HDLC1_B_QE_BRG		(2 << (30-16))
+#define SICR_2_HDLC1_B_TDM1		(3 << (30-16))
+#define SICR_2_HDLC1_C_HDLC1		(0 << (30-18))
+#define SICR_2_HDLC1_C_GPIO		(1 << (30-18))
+#define SICR_2_HDLC1_C_TDM1		(2 << (30-18))
+#define SICR_2_HDLC2_B_HDLC2		(0 << (30-20))
+#define SICR_2_HDLC2_B_GPIO		(1 << (30-20))
+#define SICR_2_HDLC2_B_QE_BRG		(2 << (30-20))
+#define SICR_2_HDLC2_B_TDM2		(3 << (30-20))
+#define SICR_2_HDLC2_C_HDLC2		(0 << (30-22))
+#define SICR_2_HDLC2_C_GPIO		(1 << (30-22))
+#define SICR_2_HDLC2_C_TDM2		(2 << (30-22))
+#define SICR_2_HDLC2_C_QE_BRG		(3 << (30-22))
+#define SICR_2_QUIESCE_B		(0 << (30-24))
+
 #endif
 
 /*
@@ -580,6 +661,63 @@
 #define HRCWL_SVCOD_DIV_8		0x10000000
 #define HRCWL_SVCOD_DIV_2		0x20000000
 #define HRCWL_SVCOD_DIV_1		0x30000000
+#elif defined(CONFIG_MPC8309)
+
+#define HRCWL_CEVCOD			0x000000C0
+#define HRCWL_CEVCOD_SHIFT		6
+/*
+ * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
+ * these are different than with 8360, 832x
+ */
+#define HRCWL_CE_PLL_VCO_DIV_2		0x00000000
+#define HRCWL_CE_PLL_VCO_DIV_4		0x00000040
+#define HRCWL_CE_PLL_VCO_DIV_8		0x00000080
+
+#define HRCWL_CEPDF			0x00000020
+#define HRCWL_CEPDF_SHIFT		5
+#define HRCWL_CE_PLL_DIV_1X1		0x00000000
+#define HRCWL_CE_PLL_DIV_2X1		0x00000020
+
+#define HRCWL_CEPMF			0x0000001F
+#define HRCWL_CEPMF_SHIFT		0
+#define HRCWL_CE_TO_PLL_1X16_		0x00000000
+#define HRCWL_CE_TO_PLL_1X2		0x00000002
+#define HRCWL_CE_TO_PLL_1X3		0x00000003
+#define HRCWL_CE_TO_PLL_1X4		0x00000004
+#define HRCWL_CE_TO_PLL_1X5		0x00000005
+#define HRCWL_CE_TO_PLL_1X6		0x00000006
+#define HRCWL_CE_TO_PLL_1X7		0x00000007
+#define HRCWL_CE_TO_PLL_1X8		0x00000008
+#define HRCWL_CE_TO_PLL_1X9		0x00000009
+#define HRCWL_CE_TO_PLL_1X10		0x0000000A
+#define HRCWL_CE_TO_PLL_1X11		0x0000000B
+#define HRCWL_CE_TO_PLL_1X12		0x0000000C
+#define HRCWL_CE_TO_PLL_1X13		0x0000000D
+#define HRCWL_CE_TO_PLL_1X14		0x0000000E
+#define HRCWL_CE_TO_PLL_1X15		0x0000000F
+#define HRCWL_CE_TO_PLL_1X16		0x00000010
+#define HRCWL_CE_TO_PLL_1X17		0x00000011
+#define HRCWL_CE_TO_PLL_1X18		0x00000012
+#define HRCWL_CE_TO_PLL_1X19		0x00000013
+#define HRCWL_CE_TO_PLL_1X20		0x00000014
+#define HRCWL_CE_TO_PLL_1X21		0x00000015
+#define HRCWL_CE_TO_PLL_1X22		0x00000016
+#define HRCWL_CE_TO_PLL_1X23		0x00000017
+#define HRCWL_CE_TO_PLL_1X24		0x00000018
+#define HRCWL_CE_TO_PLL_1X25		0x00000019
+#define HRCWL_CE_TO_PLL_1X26		0x0000001A
+#define HRCWL_CE_TO_PLL_1X27		0x0000001B
+#define HRCWL_CE_TO_PLL_1X28		0x0000001C
+#define HRCWL_CE_TO_PLL_1X29		0x0000001D
+#define HRCWL_CE_TO_PLL_1X30		0x0000001E
+#define HRCWL_CE_TO_PLL_1X31		0x0000001F
+
+#define HRCWL_SVCOD			0x30000000
+#define HRCWL_SVCOD_SHIFT		28
+#define HRCWL_SVCOD_DIV_2		0x00000000
+#define HRCWL_SVCOD_DIV_4		0x10000000
+#define HRCWL_SVCOD_DIV_8		0x20000000
+#define HRCWL_SVCOD_DIV_1		0x30000000
 #endif
 
 /*
@@ -940,6 +1078,21 @@
 #define SCCR_SATACM_1			0x00000055
 #define SCCR_SATACM_2			0x000000aa
 #define SCCR_SATACM_3			0x000000ff
+#elif defined(CONFIG_MPC8309)
+/* SCCR bits - MPC8309 specific */
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+
+#define SCCR_USBDRCM			0x00c00000
+#define SCCR_USBDRCM_SHIFT		22
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00400000
+#define SCCR_USBDRCM_2			0x00800000
+#define SCCR_USBDRCM_3			0x00c00000
 #endif
 
 #define SCCR_PCIEXP1CM			0x00300000
-- 
1.7.10.1

[U-Boot] [PATCH v2 5/6] km83xx: add common support for km8309 boards

[Gerlando Falauto]

Add support for Keymile boards based on mpc8309
(it would be only kmvect1 for now)

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
---
 board/keymile/km83xx/km83xx.c      |    2 +-
 include/configs/km/km8309-common.h |  176 ++++++++++++++++++++++++++++++++++++
 include/configs/km/km83xx-common.h |    6 ++
 3 files changed, 183 insertions(+), 1 deletion(-)
 create mode 100644 include/configs/km/km8309-common.h

diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index e01a633..0d59ce6 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -56,7 +56,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{5,  2, 1, 0, 1}, /* UART2_RTS */
 	{5,  3, 2, 0, 2}, /* UART2_SIN */
 	{5,  1, 2, 0, 3}, /* UART2_CTS */
-#else
+#elseif !defined(CONFIG_MPC8309)
 	/* Local Bus */
 	{0, 16, 1, 0, 3}, /* LA00 */
 	{0, 17, 1, 0, 3}, /* LA01 */
diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h
new file mode 100644
index 0000000..b36e892
--- /dev/null
+++ b/include/configs/km/km8309-common.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2012 Keymile AG
+ *                    Gerlando Falauto <gerlando.falauto@keymile.com>
+ *
+ * Based on km8321-common.h, see respective copyright notice for credits
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_KM8309_COMMON_H
+#define __CONFIG_KM8309_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 family */
+#define CONFIG_QE		1	/* Has QE */
+#define CONFIG_MPC83xx		1	/* MPC83xx family */
+#define CONFIG_MPC830x		1	/* MPC830x family */
+#define CONFIG_MPC8309		1	/* MPC8309 CPU specific */
+
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_8xx\0"
+#define CONFIG_CMD_DIAG		1
+
+/* include common defines/options for all 83xx Keymile boards */
+#include "km83xx-common.h"
+
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+/* at end of uboot partition, before env */
+#define CONFIG_SYS_QE_FMAN_FW_ADDR   0xF00B0000
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * System IO Config
+ */
+/* 0x14000180 SICR_1 */
+#define CONFIG_SYS_SICRL (0			\
+		| SICR_1_UART1_UART1RTS		\
+		| SICR_1_I2C_CKSTOP		\
+		| SICR_1_IRQ_A_IRQ		\
+		| SICR_1_IRQ_B_IRQ		\
+		| SICR_1_GPIO_A_GPIO		\
+		| SICR_1_GPIO_B_GPIO		\
+		| SICR_1_GPIO_C_GPIO		\
+		| SICR_1_GPIO_D_GPIO		\
+		| SICR_1_GPIO_E_GPIO		\
+		| SICR_1_GPIO_F_GPIO		\
+		| SICR_1_USB_A_UART2S		\
+		| SICR_1_USB_B_UART2RTS		\
+		| SICR_1_FEC1_FEC1		\
+		| SICR_1_FEC2_FEC2		\
+		)
+
+/* 0x00080400 SICR_2 */
+#define CONFIG_SYS_SICRH (0			\
+		| SICR_2_FEC3_FEC3		\
+		| SICR_2_HDLC1_A_HDLC1		\
+		| SICR_2_ELBC_A_LA		\
+		| SICR_2_ELBC_B_LCLK		\
+		| SICR_2_HDLC2_A_HDLC2		\
+		| SICR_2_USB_D_GPIO		\
+		| SICR_2_PCI_PCI		\
+		| SICR_2_HDLC1_B_HDLC1		\
+		| SICR_2_HDLC1_C_HDLC1		\
+		| SICR_2_HDLC2_B_GPIO		\
+		| SICR_2_HDLC2_C_HDLC2		\
+		| SICR_2_QUIESCE_B		\
+		)
+
+/* GPR_1 */
+#define CONFIG_SYS_GPR1  0x50008060
+
+#define CONFIG_SYS_GP1DIR 0x00000000
+#define CONFIG_SYS_GP1ODR 0x00000000
+#define CONFIG_SYS_GP2DIR 0xFF000000
+#define CONFIG_SYS_GP2ODR 0x00000000
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
+	HRCWL_DDR_TO_SCB_CLK_2X1 | \
+	HRCWL_CSB_TO_CLKIN_2X1 | \
+	HRCWL_CORE_TO_CSB_2X1 | \
+	HRCWL_CE_PLL_VCO_DIV_2 | \
+	HRCWL_CE_TO_PLL_1X3)
+
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_AGENT | \
+	HRCWH_PCI_ARBITER_DISABLE | \
+	HRCWH_CORE_ENABLE | \
+	HRCWH_FROM_0X00000100 | \
+	HRCWH_BOOTSEQ_DISABLE | \
+	HRCWH_SW_WATCHDOG_DISABLE | \
+	HRCWH_ROM_LOC_LOCAL_16BIT | \
+	HRCWH_BIG_ENDIAN | \
+	HRCWH_LALE_NORMAL)
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+					 SDRAM_CFG_32_BE | \
+					 SDRAM_CFG_SREN | \
+					 SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+					 CSCONFIG_ODT_RD_NEVER | \
+					 CSCONFIG_ODT_WR_ONLY_CURRENT | \
+					 CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE	0x47860242
+#define CONFIG_SYS_DDR_MODE2	0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP	0x80000000
+#define CONFIG_SYS_LCRR_EADC	0x00010000
+#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
+
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#endif /* __CONFIG_KM8309_COMMON_H */
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index 877d841..a9823d6 100644
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -169,9 +169,15 @@
 #define UEC_VERBOSE_DEBUG	1
 
 #ifdef CONFIG_UEC_ETH1
+#if defined(CONFIG_MPC8309)
+#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK12
+#else
 #define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
 #define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
+#endif
 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	0
 #define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
-- 
1.7.10.1

[U-Boot] [PATCH v2 5/6] km83xx: add common support for km8309 boards

[Kim Phillips]

On Thu, 11 Oct 2012 10:13:09 +0200
Gerlando Falauto <gerlando.falauto@keymile.com> wrote:

> +++ b/board/keymile/km83xx/km83xx.c
> @@ -56,7 +56,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
>  	{5,  2, 1, 0, 1}, /* UART2_RTS */
>  	{5,  3, 2, 0, 2}, /* UART2_SIN */
>  	{5,  1, 2, 0, 3}, /* UART2_CTS */
> -#else
> +#elseif !defined(CONFIG_MPC8309)

Applied 6 out of 6 patches, and fixed the build errors this caused
for kmcoge5ne and kmeter1:

Configuring for kmcoge5ne - Board: km8360, Options: KMCOGE5NE
km83xx.c:59:2: error: invalid preprocessing directive #elseif
make: *** [board/keymile/km83xx/libkm83xx.o] Error 2
powerpc-linux-size: './u-boot': No such file
km83xx.c:59:2: error: invalid preprocessing directive #elseif
make[1]: *** No rule to make target `.depend', needed by `libkm83xx.o'.  Stop.
make: *** [board/keymile/km83xx/libkm83xx.o] Error 2
Configuring for kmeter1 - Board: km8360, Options: KMETER1
km83xx.c:59:2: error: invalid preprocessing directive #elseif
make: *** [board/keymile/km83xx/libkm83xx.o] Error 2
powerpc-linux-size: './u-boot': No such file
km83xx.c:59:2: error: invalid preprocessing directive #elseif
make[1]: *** No rule to make target `.depend', needed by `libkm83xx.o'.  Stop.
make: *** [board/keymile/km83xx/libkm83xx.o] Error 2

please be more careful in the future.

Thanks,

Kim

[U-Boot] [PATCH v2 6/6] km83xx: add kmvect1 board

[Gerlando Falauto]

Add support for the new kmvect1 board powered by the mpc8309 processor.
As this board is very similar to the existing suvd3, instead of adding a
new config header file, just add a new config option to suvd3.h

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
---
 boards.cfg              |    3 ++-
 include/configs/suvd3.h |   15 ++++++++++++---
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index 7c1fc74..6781969 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -676,7 +676,8 @@ MVBLM7                       powerpc     mpc83xx     mvblm7              matrix_
 SIMPC8313_LP                 powerpc     mpc83xx     simpc8313           sheldon        -           SIMPC8313:NAND_LP
 SIMPC8313_SP                 powerpc     mpc83xx     simpc8313           sheldon        -           SIMPC8313:NAND_SP
 TQM834x                      powerpc     mpc83xx     tqm834x             tqc
-suvd3                        powerpc     mpc83xx     km83xx              keymile
+suvd3                        powerpc     mpc83xx     km83xx              keymile        -           suvd3:SUVD3
+kmvect1                      powerpc     mpc83xx     km83xx              keymile        -           suvd3:KMVECT1
 tuge1                        powerpc     mpc83xx     km83xx              keymile        -           tuxx1:KM_DISABLE_APP2,TUGE1
 tuxx1                        powerpc     mpc83xx     km83xx              keymile
 kmsupx5                      powerpc     mpc83xx     km83xx              keymile        -           tuxx1:KM_DISABLE_APP2,KMSUPX5
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 68680c5..c50832c 100644
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -23,14 +23,23 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_SUVD3		/* SUVD3 board specific */
-#define CONFIG_HOSTNAME		suvd3
-#define CONFIG_KM_BOARD_NAME   "suvd3"
 
+/* This needs to be set prior to including km/km83xx-common.h */
 #define	CONFIG_SYS_TEXT_BASE	0xF0000000
 
+#if defined(CONFIG_SUVD3)	/* SUVD3 board specific */
+#define CONFIG_HOSTNAME		suvd3
+#define CONFIG_KM_BOARD_NAME   "suvd3"
 /* include common defines/options for all 8321 Keymile boards */
 #include "km/km8321-common.h"
+#elif defined(CONFIG_KMVECT1)   /* VECT1 board specific */
+#define CONFIG_HOSTNAME		kmvect1
+#define CONFIG_KM_BOARD_NAME   "kmvect1"
+/* include common defines/options for all 8309 Keymile boards */
+#include "km/km8309-common.h"
+#else
+#error Supported boards are: SUVD3, KMVECT1
+#endif
 
 #define CONFIG_SYS_APP1_BASE		0xA0000000
 #define CONFIG_SYS_APP1_SIZE		256 /* Megabytes */
-- 
1.7.10.1