[Qemu-devel] [0/4] Pending ppc and pseries patches

[Qemu-devel] [0/4] Pending ppc and pseries patches

[David Gibson]

Hi Alex,

Here are some assorted pending pseries patches which should be ready
to go.  This clears the decks ready for a big series to add
savevm/migration support for pseries.

[Qemu-devel] [PATCH 1/4] pseries: Don't allow duplicate registration of hcalls or RTAS calls

[David Gibson]

Currently the pseries machine code allows a callback to be registered
for a hypercall number twice, as long as it's the same callback the second
time.  We don't test for duplicate registrations of RTAS callbacks at all
so it will effectively be last registratiojn wins.

This was originally done because it was awkward to ensure that the
registration happened exactly once, but the code has since been
restructured so that's no longer the case.

Duplicate registration of a hypercall or RTAS call could well suggest
a duplicate initialization which could cause other problems, so this patch
makes duplicate registrations a bug, to prevent the old behaviour from
hiding other bugs.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/spapr_hcall.c |    3 +--
 hw/spapr_rtas.c  |    9 +++++++++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c
index 194d9c2..762493a 100644
--- a/hw/spapr_hcall.c
+++ b/hw/spapr_hcall.c
@@ -670,11 +670,10 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
     } else {
         assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
 
-
         slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
     }
 
-    assert(!(*slot) || (fn == *slot));
+    assert(!(*slot));
     *slot = fn;
 }
 
diff --git a/hw/spapr_rtas.c b/hw/spapr_rtas.c
index b808f80..b96078b 100644
--- a/hw/spapr_rtas.c
+++ b/hw/spapr_rtas.c
@@ -241,6 +241,15 @@ target_ulong spapr_rtas_call(sPAPREnvironment *spapr,
 
 void spapr_rtas_register(const char *name, spapr_rtas_fn fn)
 {
+    int i;
+
+    for (i = 0; i < (rtas_next - rtas_table); i++) {
+        if (strcmp(name, rtas_table[i].name) == 0) {
+            fprintf(stderr, "RTAS call \"%s\" registered twice\n", name);
+            exit(1);
+        }
+    }
+
     assert(rtas_next < (rtas_table + TOKEN_MAX));
 
     rtas_next->name = name;
-- 
1.7.10.4

[Qemu-devel] [PATCH 2/4] target-ppc: Extend FPU state for newer POWER CPUs

[David Gibson]

This patch adds some extra FPU state to CPUPPCState.  Specifically,
fpscr is extended to a target_ulong bits, since some recent (64 bit)
CPUs now have more status bits than fit inside 32 bits.  Also, we add
the 32 VSR registers present on CPUs with VSX (these extend the
standard FP regs, which together with the Altivec/VMX registers form a
64 x 128bit register file for VSX).

We don't actually support the instructions using these extra registers
in TCG yet, but we still need a place to store the state so we can
sync it with KVM and savevm/loadvm it.  This patch updates the savevm
code to not fail on the extended state, but also does not actually
save it - that's a project for another patch.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---

v2:
 * Used target_ulong instead of uint64_t, since the extended state is used
only on ppc64 targets.
 * Fixed the TCG mapping of fpscr to match the new type.
---
 target-ppc/cpu.h       |    4 +++-
 target-ppc/machine.c   |    8 ++++++--
 target-ppc/translate.c |    4 ++--
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index faf4404..7627722 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -963,7 +963,7 @@ struct CPUPPCState {
     /* floating point registers */
     float64 fpr[32];
     /* floating point status and control register */
-    uint32_t fpscr;
+    target_ulong fpscr;
 
     /* Next instruction pointer */
     target_ulong nip;
@@ -1014,6 +1014,8 @@ struct CPUPPCState {
     /* Altivec registers */
     ppc_avr_t avr[32];
     uint32_t vscr;
+    /* VSX registers */
+    uint64_t vsr[32];
     /* SPE registers */
     uint64_t spe_acc;
     uint32_t spe_fscr;
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index 21ce757..5e7bc00 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -6,6 +6,7 @@ void cpu_save(QEMUFile *f, void *opaque)
 {
     CPUPPCState *env = (CPUPPCState *)opaque;
     unsigned int i, j;
+    uint32_t fpscr;
 
     for (i = 0; i < 32; i++)
         qemu_put_betls(f, &env->gpr[i]);
@@ -30,7 +31,8 @@ void cpu_save(QEMUFile *f, void *opaque)
         u.d = env->fpr[i];
         qemu_put_be64(f, u.l);
     }
-    qemu_put_be32s(f, &env->fpscr);
+    fpscr = env->fpscr;
+    qemu_put_be32s(f, &fpscr);
     qemu_put_sbe32s(f, &env->access_type);
 #if defined(TARGET_PPC64)
     qemu_put_betls(f, &env->asr);
@@ -90,6 +92,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     CPUPPCState *env = (CPUPPCState *)opaque;
     unsigned int i, j;
     target_ulong sdr1;
+    uint32_t fpscr;
 
     for (i = 0; i < 32; i++)
         qemu_get_betls(f, &env->gpr[i]);
@@ -114,7 +117,8 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
         u.l = qemu_get_be64(f);
         env->fpr[i] = u.d;
     }
-    qemu_get_be32s(f, &env->fpscr);
+    qemu_get_be32s(f, &fpscr);
+    env->fpscr = fpscr;
     qemu_get_sbe32s(f, &env->access_type);
 #if defined(TARGET_PPC64)
     qemu_get_betls(f, &env->asr);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1042268..01c2907 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -68,7 +68,7 @@ static TCGv cpu_cfar;
 #endif
 static TCGv cpu_xer;
 static TCGv cpu_reserve;
-static TCGv_i32 cpu_fpscr;
+static TCGv cpu_fpscr;
 static TCGv_i32 cpu_access_type;
 
 #include "gen-icount.h"
@@ -9463,7 +9463,7 @@ void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
         if ((i & (RFPL - 1)) == (RFPL - 1))
             cpu_fprintf(f, "\n");
     }
-    cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
+    cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
 #if !defined(CONFIG_USER_ONLY)
     cpu_fprintf(f, " SRR0 " TARGET_FMT_lx "  SRR1 " TARGET_FMT_lx
                    "    PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
-- 
1.7.10.4

Re: [Qemu-devel] [PATCH 2/4] target-ppc: Extend FPU state for newer POWER CPUs

[Alexander Graf]

On 09.10.2012, at 06:17, David Gibson wrote:

> This patch adds some extra FPU state to CPUPPCState.  Specifically,
> fpscr is extended to a target_ulong bits, since some recent (64 bit)
> CPUs now have more status bits than fit inside 32 bits.  Also, we add
> the 32 VSR registers present on CPUs with VSX (these extend the
> standard FP regs, which together with the Altivec/VMX registers form a
> 64 x 128bit register file for VSX).
> 
> We don't actually support the instructions using these extra registers
> in TCG yet, but we still need a place to store the state so we can
> sync it with KVM and savevm/loadvm it.  This patch updates the savevm
> code to not fail on the extended state, but also does not actually
> save it - that's a project for another patch.
> 
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> 
> v2:
> * Used target_ulong instead of uint64_t, since the extended state is used
> only on ppc64 targets.
> * Fixed the TCG mapping of fpscr to match the new type.
> ---
> target-ppc/cpu.h       |    4 +++-
> target-ppc/machine.c   |    8 ++++++--
> target-ppc/translate.c |    4 ++--
> 3 files changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index faf4404..7627722 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -963,7 +963,7 @@ struct CPUPPCState {
>     /* floating point registers */
>     float64 fpr[32];
>     /* floating point status and control register */
> -    uint32_t fpscr;
> +    target_ulong fpscr;

This will still break TCG for qemu-system-ppc64, no?


Alex

> 
>     /* Next instruction pointer */
>     target_ulong nip;
> @@ -1014,6 +1014,8 @@ struct CPUPPCState {
>     /* Altivec registers */
>     ppc_avr_t avr[32];
>     uint32_t vscr;
> +    /* VSX registers */
> +    uint64_t vsr[32];
>     /* SPE registers */
>     uint64_t spe_acc;
>     uint32_t spe_fscr;
> diff --git a/target-ppc/machine.c b/target-ppc/machine.c
> index 21ce757..5e7bc00 100644
> --- a/target-ppc/machine.c
> +++ b/target-ppc/machine.c
> @@ -6,6 +6,7 @@ void cpu_save(QEMUFile *f, void *opaque)
> {
>     CPUPPCState *env = (CPUPPCState *)opaque;
>     unsigned int i, j;
> +    uint32_t fpscr;
> 
>     for (i = 0; i < 32; i++)
>         qemu_put_betls(f, &env->gpr[i]);
> @@ -30,7 +31,8 @@ void cpu_save(QEMUFile *f, void *opaque)
>         u.d = env->fpr[i];
>         qemu_put_be64(f, u.l);
>     }
> -    qemu_put_be32s(f, &env->fpscr);
> +    fpscr = env->fpscr;
> +    qemu_put_be32s(f, &fpscr);
>     qemu_put_sbe32s(f, &env->access_type);
> #if defined(TARGET_PPC64)
>     qemu_put_betls(f, &env->asr);
> @@ -90,6 +92,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
>     CPUPPCState *env = (CPUPPCState *)opaque;
>     unsigned int i, j;
>     target_ulong sdr1;
> +    uint32_t fpscr;
> 
>     for (i = 0; i < 32; i++)
>         qemu_get_betls(f, &env->gpr[i]);
> @@ -114,7 +117,8 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
>         u.l = qemu_get_be64(f);
>         env->fpr[i] = u.d;
>     }
> -    qemu_get_be32s(f, &env->fpscr);
> +    qemu_get_be32s(f, &fpscr);
> +    env->fpscr = fpscr;
>     qemu_get_sbe32s(f, &env->access_type);
> #if defined(TARGET_PPC64)
>     qemu_get_betls(f, &env->asr);
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 1042268..01c2907 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -68,7 +68,7 @@ static TCGv cpu_cfar;
> #endif
> static TCGv cpu_xer;
> static TCGv cpu_reserve;
> -static TCGv_i32 cpu_fpscr;
> +static TCGv cpu_fpscr;
> static TCGv_i32 cpu_access_type;
> 
> #include "gen-icount.h"
> @@ -9463,7 +9463,7 @@ void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
>         if ((i & (RFPL - 1)) == (RFPL - 1))
>             cpu_fprintf(f, "\n");
>     }
> -    cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
> +    cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
> #if !defined(CONFIG_USER_ONLY)
>     cpu_fprintf(f, " SRR0 " TARGET_FMT_lx "  SRR1 " TARGET_FMT_lx
>                    "    PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
> -- 
> 1.7.10.4
> 

Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/4] target-ppc: Extend FPU state for newer POWER CPUs

[Alexander Graf]

On 09.10.2012, at 13:38, Alexander Graf wrote:

> 
> On 09.10.2012, at 06:17, David Gibson wrote:
> 
>> This patch adds some extra FPU state to CPUPPCState.  Specifically,
>> fpscr is extended to a target_ulong bits, since some recent (64 bit)
>> CPUs now have more status bits than fit inside 32 bits.  Also, we add
>> the 32 VSR registers present on CPUs with VSX (these extend the
>> standard FP regs, which together with the Altivec/VMX registers form a
>> 64 x 128bit register file for VSX).
>> 
>> We don't actually support the instructions using these extra registers
>> in TCG yet, but we still need a place to store the state so we can
>> sync it with KVM and savevm/loadvm it.  This patch updates the savevm
>> code to not fail on the extended state, but also does not actually
>> save it - that's a project for another patch.
>> 
>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>> 
>> v2:
>> * Used target_ulong instead of uint64_t, since the extended state is used
>> only on ppc64 targets.
>> * Fixed the TCG mapping of fpscr to match the new type.
>> ---
>> target-ppc/cpu.h       |    4 +++-
>> target-ppc/machine.c   |    8 ++++++--
>> target-ppc/translate.c |    4 ++--
>> 3 files changed, 11 insertions(+), 5 deletions(-)
>> 
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index faf4404..7627722 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -963,7 +963,7 @@ struct CPUPPCState {
>>    /* floating point registers */
>>    float64 fpr[32];
>>    /* floating point status and control register */
>> -    uint32_t fpscr;
>> +    target_ulong fpscr;
> 
> This will still break TCG for qemu-system-ppc64, no?

To be more precise:

agraf@lychee:/home/agraf/release/qemu> grep -R cpu_fpscr target-ppc
target-ppc/translate.c:static TCGv_i32 cpu_fpscr;
target-ppc/translate.c:    cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
target-ppc/translate.c:    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
target-ppc/translate.c:    tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
target-ppc/translate.c:    tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);

All those functions assume cpu_fpscr is a TCGv32. They need to be adjusted to work on tl instead.

Please test compile your code with configure --enable-tcg-debug.


Alex

Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/4] target-ppc: Extend FPU state for newer POWER CPUs

[David Gibson]

On Tue, Oct 09, 2012 at 01:41:02PM +0200, Alexander Graf wrote:
> On 09.10.2012, at 13:38, Alexander Graf wrote:
> > On 09.10.2012, at 06:17, David Gibson wrote:
[snip]
> > This will still break TCG for qemu-system-ppc64, no?
> 
> To be more precise:
> 
> agraf@lychee:/home/agraf/release/qemu> grep -R cpu_fpscr target-ppc
> target-ppc/translate.c:static TCGv_i32 cpu_fpscr;

I did update the type of cpu_fpscr..

> target-ppc/translate.c:    cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
> target-ppc/translate.c:    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
> target-ppc/translate.c:    tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
> target-ppc/translate.c:    tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
> target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
> target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
> target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
> target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
> 
> All those functions assume cpu_fpscr is a TCGv32. They need to be
> adjusted to work on tl instead.

But I didn't spot the type dependent calls.  I figured type checking
would catch that sort of thing, but apparently not.

> Please test compile your code with configure --enable-tcg-debug.

Ok, will do.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/4] target-ppc: Extend FPU state for newer POWER CPUs

[Alexander Graf]

On 10/09/2012 02:50 PM, David Gibson wrote:
> On Tue, Oct 09, 2012 at 01:41:02PM +0200, Alexander Graf wrote:
>> On 09.10.2012, at 13:38, Alexander Graf wrote:
>>> On 09.10.2012, at 06:17, David Gibson wrote:
> [snip]
>>> This will still break TCG for qemu-system-ppc64, no?
>> To be more precise:
>>
>> agraf@lychee:/home/agraf/release/qemu>  grep -R cpu_fpscr target-ppc
>> target-ppc/translate.c:static TCGv_i32 cpu_fpscr;
> I did update the type of cpu_fpscr..
>
>> target-ppc/translate.c:    cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
>> target-ppc/translate.c:    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
>> target-ppc/translate.c:    tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF<<  bfa));
>> target-ppc/translate.c:    tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
>> target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
>> target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
>> target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
>> target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
>>
>> All those functions assume cpu_fpscr is a TCGv32. They need to be
>> adjusted to work on tl instead.
> But I didn't spot the type dependent calls.  I figured type checking
> would catch that sort of thing, but apparently not.

Type checking only happens with enable-tcg-debug :)


Alex

[Qemu-devel] [PATCH 3/4] target-ppc: Rework storage of VPA registration state

[David Gibson]

With PAPR guests, hypercalls allow registration of the Virtual Processor
Area (VPA), SLB shadow and dispatch trace log (DTL), each of which allow
for certain communication between the guest and hypervisor.  Currently, we
store the addresses of the three areas and the size of the dtl in
CPUPPCState.

The SLB shadow and DTL are variable sized, with the size being retrieved
from within the registered memory area at the hypercall time.  This size
can later be overwritten with other information, however, so we need to
save the size as of registration time.  We already do this for the DTL,
but not for the SLB shadow, so this patch fixes that.

In addition, we change the storage of the VPA information to use fixed
size integer types which will make life easier for syncing this data with
KVM, which we will need in future.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/spapr_hcall.c            |   26 ++++++++++++++------------
 target-ppc/cpu.h            |    7 +++----
 target-ppc/translate_init.c |    7 ++++---
 3 files changed, 21 insertions(+), 19 deletions(-)

diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c
index 762493a..621dabd 100644
--- a/hw/spapr_hcall.c
+++ b/hw/spapr_hcall.c
@@ -366,26 +366,26 @@ static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
         return H_PARAMETER;
     }
 
-    env->vpa = vpa;
+    env->vpa_addr = vpa;
 
-    tmp = ldub_phys(env->vpa + VPA_SHARED_PROC_OFFSET);
+    tmp = ldub_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET);
     tmp |= VPA_SHARED_PROC_VAL;
-    stb_phys(env->vpa + VPA_SHARED_PROC_OFFSET, tmp);
+    stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
 
     return H_SUCCESS;
 }
 
 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
 {
-    if (env->slb_shadow) {
+    if (env->slb_shadow_addr) {
         return H_RESOURCE;
     }
 
-    if (env->dispatch_trace_log) {
+    if (env->dtl_addr) {
         return H_RESOURCE;
     }
 
-    env->vpa = 0;
+    env->vpa_addr = 0;
     return H_SUCCESS;
 }
 
@@ -407,18 +407,20 @@ static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
         return H_PARAMETER;
     }
 
-    if (!env->vpa) {
+    if (!env->vpa_addr) {
         return H_RESOURCE;
     }
 
-    env->slb_shadow = addr;
+    env->slb_shadow_addr = addr;
+    env->slb_shadow_size = size;
 
     return H_SUCCESS;
 }
 
 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
 {
-    env->slb_shadow = 0;
+    env->slb_shadow_addr = 0;
+    env->slb_shadow_size = 0;
     return H_SUCCESS;
 }
 
@@ -437,11 +439,11 @@ static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
         return H_PARAMETER;
     }
 
-    if (!env->vpa) {
+    if (!env->vpa_addr) {
         return H_RESOURCE;
     }
 
-    env->dispatch_trace_log = addr;
+    env->dtl_addr = addr;
     env->dtl_size = size;
 
     return H_SUCCESS;
@@ -449,7 +451,7 @@ static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
 
 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr)
 {
-    env->dispatch_trace_log = 0;
+    env->dtl_addr = 0;
     env->dtl_size = 0;
 
     return H_SUCCESS;
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 7627722..cde6da0 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1047,10 +1047,9 @@ struct CPUPPCState {
 #endif
 
 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-    target_phys_addr_t vpa;
-    target_phys_addr_t slb_shadow;
-    target_phys_addr_t dispatch_trace_log;
-    uint32_t dtl_size;
+    uint64_t vpa_addr;
+    uint64_t slb_shadow_addr, slb_shadow_size;
+    uint64_t dtl_addr, dtl_size;
 #endif /* TARGET_PPC64 */
 
     int error_code;
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index a972287..831b169 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -10425,9 +10425,10 @@ static void ppc_cpu_reset(CPUState *s)
     env->error_code = 0;
 
 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-    env->vpa = 0;
-    env->slb_shadow = 0;
-    env->dispatch_trace_log = 0;
+    env->vpa_addr = 0;
+    env->slb_shadow_addr = 0;
+    env->slb_shadow_size = 0;
+    env->dtl_addr = 0;
     env->dtl_size = 0;
 #endif /* TARGET_PPC64 */
 
-- 
1.7.10.4

[Qemu-devel] [PATCH 4/4] pseries: Implement qemu initiated shutdowns using EPOW events

[David Gibson]

At present, using 'system_powerdown' from the monitor or otherwise
instructing qemu to (cleanly) shut down a pseries guest will not work,
because we did not have a method of signalling the shutdown request to the
guest.

PAPR does include a usable mechanism for this, though it is rather more
involved than the equivalent on x86.  This involves sending an EPOW
(Environmental and POwer Warning) event through the PAPR event and error
logging mechanism, which also has a number of other functions.

This patch implements just enough of the event/error logging functionality
to be able to send a shutdown event to the guest.  At least with modern
guest kernels and a userspace that is up and running, this means that
system_powerdown from the qemu monitor should now work correctly on pseries
guests.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/ppc/Makefile.objs |    1 +
 hw/spapr.c           |   14 ++-
 hw/spapr.h           |    8 ++
 hw/spapr_events.c    |  321 ++++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 342 insertions(+), 2 deletions(-)
 create mode 100644 hw/spapr_events.c

diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index 951e407..8fe2123 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -11,6 +11,7 @@ obj-y += ppc_newworld.o
 obj-$(CONFIG_PSERIES) += spapr.o spapr_hcall.o spapr_rtas.o spapr_vio.o
 obj-$(CONFIG_PSERIES) += xics.o spapr_vty.o spapr_llan.o spapr_vscsi.o
 obj-$(CONFIG_PSERIES) += spapr_pci.o pci-hotplug.o spapr_iommu.o
+obj-$(CONFIG_PSERIES) += spapr_events.o
 # PowerPC 4xx boards
 obj-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
 obj-y += ppc440_bamboo.o
diff --git a/hw/spapr.c b/hw/spapr.c
index 09b8e99..64c35a8 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -232,7 +232,8 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
                                    target_phys_addr_t initrd_size,
                                    target_phys_addr_t kernel_size,
                                    const char *boot_device,
-                                   const char *kernel_cmdline)
+                                   const char *kernel_cmdline,
+                                   uint32_t epow_irq)
 {
     void *fdt;
     CPUPPCState *env;
@@ -403,6 +404,8 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
     _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
         refpoints, sizeof(refpoints))));
 
+    _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
+
     _FDT((fdt_end_node(fdt)));
 
     /* interrupt controller */
@@ -433,6 +436,9 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
 
     _FDT((fdt_end_node(fdt)));
 
+    /* event-sources */
+    spapr_events_fdt_skel(fdt, epow_irq);
+
     _FDT((fdt_end_node(fdt))); /* close root node */
     _FDT((fdt_finish(fdt)));
 
@@ -794,6 +800,9 @@ static void ppc_spapr_init(ram_addr_t ram_size,
     spapr->icp = xics_system_init(XICS_IRQS);
     spapr->next_irq = 16;
 
+    /* Set up EPOW events infrastructure */
+    spapr_events_init(spapr);
+
     /* Set up IOMMU */
     spapr_iommu_init();
 
@@ -902,7 +911,8 @@ static void ppc_spapr_init(ram_addr_t ram_size,
     spapr->fdt_skel = spapr_create_fdt_skel(cpu_model,
                                             initrd_base, initrd_size,
                                             kernel_size,
-                                            boot_device, kernel_cmdline);
+                                            boot_device, kernel_cmdline,
+                                            spapr->epow_irq);
     assert(spapr->fdt_skel != NULL);
 }
 
diff --git a/hw/spapr.h b/hw/spapr.h
index e984e3f..54960f3 100644
--- a/hw/spapr.h
+++ b/hw/spapr.h
@@ -26,6 +26,9 @@ typedef struct sPAPREnvironment {
     int rtc_offset;
     char *cpu_model;
     bool has_graphics;
+
+    uint32_t epow_irq;
+    Notifier epow_notifier;
 } sPAPREnvironment;
 
 #define H_SUCCESS         0
@@ -335,7 +338,12 @@ typedef struct sPAPRTCE {
 #define SPAPR_VIO_BASE_LIOBN    0x00000000
 #define SPAPR_PCI_BASE_LIOBN    0x80000000
 
+#define RTAS_ERROR_LOG_MAX      2048
+
+
 void spapr_iommu_init(void);
+void spapr_events_init(sPAPREnvironment *spapr);
+void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq);
 DMAContext *spapr_tce_new_dma_context(uint32_t liobn, size_t window_size);
 void spapr_tce_free(DMAContext *dma);
 void spapr_tce_reset(DMAContext *dma);
diff --git a/hw/spapr_events.c b/hw/spapr_events.c
new file mode 100644
index 0000000..18ccd4a
--- /dev/null
+++ b/hw/spapr_events.c
@@ -0,0 +1,321 @@
+/*
+ * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
+ *
+ * RTAS events handling
+ *
+ * Copyright (c) 2012 David Gibson, IBM Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+#include "cpu.h"
+#include "sysemu.h"
+#include "qemu-char.h"
+#include "hw/qdev.h"
+#include "device_tree.h"
+
+#include "hw/spapr.h"
+#include "hw/spapr_vio.h"
+
+#include <libfdt.h>
+
+struct rtas_error_log {
+    uint32_t summary;
+#define RTAS_LOG_VERSION_MASK                   0xff000000
+#define   RTAS_LOG_VERSION_6                    0x06000000
+#define RTAS_LOG_SEVERITY_MASK                  0x00e00000
+#define   RTAS_LOG_SEVERITY_ALREADY_REPORTED    0x00c00000
+#define   RTAS_LOG_SEVERITY_FATAL               0x00a00000
+#define   RTAS_LOG_SEVERITY_ERROR               0x00800000
+#define   RTAS_LOG_SEVERITY_ERROR_SYNC          0x00600000
+#define   RTAS_LOG_SEVERITY_WARNING             0x00400000
+#define   RTAS_LOG_SEVERITY_EVENT               0x00200000
+#define   RTAS_LOG_SEVERITY_NO_ERROR            0x00000000
+#define RTAS_LOG_DISPOSITION_MASK               0x00180000
+#define   RTAS_LOG_DISPOSITION_FULLY_RECOVERED  0x00000000
+#define   RTAS_LOG_DISPOSITION_LIMITED_RECOVERY 0x00080000
+#define   RTAS_LOG_DISPOSITION_NOT_RECOVERED    0x00100000
+#define RTAS_LOG_OPTIONAL_PART_PRESENT          0x00040000
+#define RTAS_LOG_INITIATOR_MASK                 0x0000f000
+#define   RTAS_LOG_INITIATOR_UNKNOWN            0x00000000
+#define   RTAS_LOG_INITIATOR_CPU                0x00001000
+#define   RTAS_LOG_INITIATOR_PCI                0x00002000
+#define   RTAS_LOG_INITIATOR_MEMORY             0x00004000
+#define   RTAS_LOG_INITIATOR_HOTPLUG            0x00006000
+#define RTAS_LOG_TARGET_MASK                    0x00000f00
+#define   RTAS_LOG_TARGET_UNKNOWN               0x00000000
+#define   RTAS_LOG_TARGET_CPU                   0x00000100
+#define   RTAS_LOG_TARGET_PCI                   0x00000200
+#define   RTAS_LOG_TARGET_MEMORY                0x00000400
+#define   RTAS_LOG_TARGET_HOTPLUG               0x00000600
+#define RTAS_LOG_TYPE_MASK                      0x000000ff
+#define   RTAS_LOG_TYPE_OTHER                   0x00000000
+#define   RTAS_LOG_TYPE_RETRY                   0x00000001
+#define   RTAS_LOG_TYPE_TCE_ERR                 0x00000002
+#define   RTAS_LOG_TYPE_INTERN_DEV_FAIL         0x00000003
+#define   RTAS_LOG_TYPE_TIMEOUT                 0x00000004
+#define   RTAS_LOG_TYPE_DATA_PARITY             0x00000005
+#define   RTAS_LOG_TYPE_ADDR_PARITY             0x00000006
+#define   RTAS_LOG_TYPE_CACHE_PARITY            0x00000007
+#define   RTAS_LOG_TYPE_ADDR_INVALID            0x00000008
+#define   RTAS_LOG_TYPE_ECC_UNCORR              0x00000009
+#define   RTAS_LOG_TYPE_ECC_CORR                0x0000000a
+#define   RTAS_LOG_TYPE_EPOW                    0x00000040
+    uint32_t extended_length;
+} QEMU_PACKED;
+
+struct rtas_event_log_v6 {
+    uint8_t b0;
+#define RTAS_LOG_V6_B0_VALID                          0x80
+#define RTAS_LOG_V6_B0_UNRECOVERABLE_ERROR            0x40
+#define RTAS_LOG_V6_B0_RECOVERABLE_ERROR              0x20
+#define RTAS_LOG_V6_B0_DEGRADED_OPERATION             0x10
+#define RTAS_LOG_V6_B0_PREDICTIVE_ERROR               0x08
+#define RTAS_LOG_V6_B0_NEW_LOG                        0x04
+#define RTAS_LOG_V6_B0_BIGENDIAN                      0x02
+    uint8_t _resv1;
+    uint8_t b2;
+#define RTAS_LOG_V6_B2_POWERPC_FORMAT                 0x80
+#define RTAS_LOG_V6_B2_LOG_FORMAT_MASK                0x0f
+#define   RTAS_LOG_V6_B2_LOG_FORMAT_PLATFORM_EVENT    0x0e
+    uint8_t _resv2[9];
+    uint32_t company;
+#define RTAS_LOG_V6_COMPANY_IBM                 0x49424d00 /* IBM<null> */
+} QEMU_PACKED;
+
+struct rtas_event_log_v6_section_header {
+    uint16_t section_id;
+    uint16_t section_length;
+    uint8_t section_version;
+    uint8_t section_subtype;
+    uint16_t creator_component_id;
+} QEMU_PACKED;
+
+struct rtas_event_log_v6_maina {
+#define RTAS_LOG_V6_SECTION_ID_MAINA                0x5048 /* PH */
+    struct rtas_event_log_v6_section_header hdr;
+    uint32_t creation_date; /* BCD: YYYYMMDD */
+    uint32_t creation_time; /* BCD: HHMMSS00 */
+    uint8_t _platform1[8];
+    char creator_id;
+    uint8_t _resv1[2];
+    uint8_t section_count;
+    uint8_t _resv2[4];
+    uint8_t _platform2[8];
+    uint32_t plid;
+    uint8_t _platform3[4];
+} QEMU_PACKED;
+
+struct rtas_event_log_v6_mainb {
+#define RTAS_LOG_V6_SECTION_ID_MAINB                0x5548 /* UH */
+    struct rtas_event_log_v6_section_header hdr;
+    uint8_t subsystem_id;
+    uint8_t _platform1;
+    uint8_t event_severity;
+    uint8_t event_subtype;
+    uint8_t _platform2[4];
+    uint8_t _resv1[2];
+    uint16_t action_flags;
+    uint8_t _resv2[4];
+} QEMU_PACKED;
+
+struct rtas_event_log_v6_epow {
+#define RTAS_LOG_V6_SECTION_ID_EPOW                 0x4550 /* EP */
+    struct rtas_event_log_v6_section_header hdr;
+    uint8_t sensor_value;
+#define RTAS_LOG_V6_EPOW_ACTION_RESET                    0
+#define RTAS_LOG_V6_EPOW_ACTION_WARN_COOLING             1
+#define RTAS_LOG_V6_EPOW_ACTION_WARN_POWER               2
+#define RTAS_LOG_V6_EPOW_ACTION_SYSTEM_SHUTDOWN          3
+#define RTAS_LOG_V6_EPOW_ACTION_SYSTEM_HALT              4
+#define RTAS_LOG_V6_EPOW_ACTION_MAIN_ENCLOSURE           5
+#define RTAS_LOG_V6_EPOW_ACTION_POWER_OFF                7
+    uint8_t event_modifier;
+#define RTAS_LOG_V6_EPOW_MODIFIER_NORMAL                 1
+#define RTAS_LOG_V6_EPOW_MODIFIER_ON_UPS                 2
+#define RTAS_LOG_V6_EPOW_MODIFIER_CRITICAL               3
+#define RTAS_LOG_V6_EPOW_MODIFIER_TEMPERATURE            4
+    uint8_t extended_modifier;
+#define RTAS_LOG_V6_EPOW_XMODIFIER_SYSTEM_WIDE           0
+#define RTAS_LOG_V6_EPOW_XMODIFIER_PARTITION_SPECIFIC    1
+    uint8_t _resv;
+    uint64_t reason_code;
+} QEMU_PACKED;
+
+struct epow_log_full {
+    struct rtas_error_log hdr;
+    struct rtas_event_log_v6 v6hdr;
+    struct rtas_event_log_v6_maina maina;
+    struct rtas_event_log_v6_mainb mainb;
+    struct rtas_event_log_v6_epow epow;
+} QEMU_PACKED;
+
+#define EVENT_MASK_INTERNAL_ERRORS           0x80000000
+#define EVENT_MASK_EPOW                      0x40000000
+#define EVENT_MASK_HOTPLUG                   0x10000000
+#define EVENT_MASK_IO                        0x08000000
+
+#define _FDT(exp) \
+    do { \
+        int ret = (exp);                                           \
+        if (ret < 0) {                                             \
+            fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
+                    #exp, fdt_strerror(ret));                      \
+            exit(1);                                               \
+        }                                                          \
+    } while (0)
+
+void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq)
+{
+    uint32_t epow_irq_ranges[] = {cpu_to_be32(epow_irq), cpu_to_be32(1)};
+    uint32_t epow_interrupts[] = {cpu_to_be32(epow_irq), 0};
+
+    _FDT((fdt_begin_node(fdt, "event-sources")));
+
+    _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
+    _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
+    _FDT((fdt_property(fdt, "interrupt-ranges",
+                       epow_irq_ranges, sizeof(epow_irq_ranges))));
+
+    _FDT((fdt_begin_node(fdt, "epow-events")));
+    _FDT((fdt_property(fdt, "interrupts",
+                       epow_interrupts, sizeof(epow_interrupts))));
+    _FDT((fdt_end_node(fdt)));
+
+    _FDT((fdt_end_node(fdt)));
+}
+
+static struct epow_log_full *pending_epow;
+static uint32_t next_plid;
+
+static void spapr_powerdown_req(Notifier *n, void *opaque)
+{
+    sPAPREnvironment *spapr = container_of(n, sPAPREnvironment, epow_notifier);
+    struct rtas_error_log *hdr;
+    struct rtas_event_log_v6 *v6hdr;
+    struct rtas_event_log_v6_maina *maina;
+    struct rtas_event_log_v6_mainb *mainb;
+    struct rtas_event_log_v6_epow *epow;
+    struct tm tm;
+    int year;
+
+    if (pending_epow) {
+        /* For now, we just throw away earlier events if two come
+         * along before any are consumed.  This is sufficient for our
+         * powerdown messages, but we'll need more if we do more
+         * general error/event logging */
+        g_free(pending_epow);
+    }
+    pending_epow = g_malloc0(sizeof(*pending_epow));
+    hdr = &pending_epow->hdr;
+    v6hdr = &pending_epow->v6hdr;
+    maina = &pending_epow->maina;
+    mainb = &pending_epow->mainb;
+    epow = &pending_epow->epow;
+
+    hdr->summary = cpu_to_be32(RTAS_LOG_VERSION_6
+                               | RTAS_LOG_SEVERITY_EVENT
+                               | RTAS_LOG_DISPOSITION_NOT_RECOVERED
+                               | RTAS_LOG_OPTIONAL_PART_PRESENT
+                               | RTAS_LOG_TYPE_EPOW);
+    hdr->extended_length = cpu_to_be32(sizeof(*pending_epow)
+                                       - sizeof(pending_epow->hdr));
+
+    v6hdr->b0 = RTAS_LOG_V6_B0_VALID | RTAS_LOG_V6_B0_NEW_LOG
+        | RTAS_LOG_V6_B0_BIGENDIAN;
+    v6hdr->b2 = RTAS_LOG_V6_B2_POWERPC_FORMAT
+        | RTAS_LOG_V6_B2_LOG_FORMAT_PLATFORM_EVENT;
+    v6hdr->company = cpu_to_be32(RTAS_LOG_V6_COMPANY_IBM);
+
+    maina->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINA);
+    maina->hdr.section_length = cpu_to_be16(sizeof(*maina));
+    /* FIXME: section version, subtype and creator id? */
+    qemu_get_timedate(&tm, spapr->rtc_offset);
+    year = tm.tm_year + 1900;
+    maina->creation_date = cpu_to_be32((to_bcd(year / 100) << 24)
+                                       | (to_bcd(year % 100) << 16)
+                                       | (to_bcd(tm.tm_mon + 1) << 8)
+                                       | to_bcd(tm.tm_mday));
+    maina->creation_time = cpu_to_be32((to_bcd(tm.tm_hour) << 24)
+                                       | (to_bcd(tm.tm_min) << 16)
+                                       | (to_bcd(tm.tm_sec) << 8));
+    maina->creator_id = 'H'; /* Hypervisor */
+    maina->section_count = 3; /* Main-A, Main-B and EPOW */
+    maina->plid = next_plid++;
+
+    mainb->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINB);
+    mainb->hdr.section_length = cpu_to_be16(sizeof(*mainb));
+    /* FIXME: section version, subtype and creator id? */
+    mainb->subsystem_id = 0xa0; /* External environment */
+    mainb->event_severity = 0x00; /* Informational / non-error */
+    mainb->event_subtype = 0xd0; /* Normal shutdown */
+
+    epow->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_EPOW);
+    epow->hdr.section_length = cpu_to_be16(sizeof(*epow));
+    epow->hdr.section_version = 2; /* includes extended modifier */
+    /* FIXME: section subtype and creator id? */
+    epow->sensor_value = RTAS_LOG_V6_EPOW_ACTION_SYSTEM_SHUTDOWN;
+    epow->event_modifier = RTAS_LOG_V6_EPOW_MODIFIER_NORMAL;
+    epow->extended_modifier = RTAS_LOG_V6_EPOW_XMODIFIER_PARTITION_SPECIFIC;
+
+    qemu_irq_pulse(xics_get_qirq(spapr->icp, spapr->epow_irq));
+}
+
+static void check_exception(sPAPREnvironment *spapr,
+                            uint32_t token, uint32_t nargs,
+                            target_ulong args,
+                            uint32_t nret, target_ulong rets)
+{
+    uint32_t mask, buf, len;
+    uint64_t xinfo;
+
+    if ((nargs < 6) || (nargs > 7) || nret != 1) {
+        rtas_st(rets, 0, -3);
+        return;
+    }
+
+    xinfo = rtas_ld(args, 1);
+    mask = rtas_ld(args, 2);
+    buf = rtas_ld(args, 4);
+    len = rtas_ld(args, 5);
+    if (nargs == 7) {
+        xinfo |= (uint64_t)rtas_ld(args, 6) << 32;
+    }
+
+    if ((mask & EVENT_MASK_EPOW) && pending_epow) {
+        if (sizeof(*pending_epow) < len) {
+            len = sizeof(*pending_epow);
+        }
+
+        cpu_physical_memory_write(buf, pending_epow, len);
+        g_free(pending_epow);
+        pending_epow = NULL;
+        rtas_st(rets, 0, 0);
+    } else {
+        rtas_st(rets, 0, 1);
+    }
+}
+
+void spapr_events_init(sPAPREnvironment *spapr)
+{
+    spapr->epow_irq = spapr_allocate_msi(0);
+    spapr->epow_notifier.notify = spapr_powerdown_req;
+    qemu_register_powerdown_notifier(&spapr->epow_notifier);
+    spapr_rtas_register("check-exception", check_exception);
+}
-- 
1.7.10.4

Re: [Qemu-devel] [PATCH 4/4] pseries: Implement qemu initiated shutdowns using EPOW events

[Blue Swirl]

On Tue, Oct 9, 2012 at 4:17 AM, David Gibson
<david@gibson.dropbear.id.au> wrote:
> At present, using 'system_powerdown' from the monitor or otherwise
> instructing qemu to (cleanly) shut down a pseries guest will not work,
> because we did not have a method of signalling the shutdown request to the
> guest.
>
> PAPR does include a usable mechanism for this, though it is rather more
> involved than the equivalent on x86.  This involves sending an EPOW
> (Environmental and POwer Warning) event through the PAPR event and error
> logging mechanism, which also has a number of other functions.
>
> This patch implements just enough of the event/error logging functionality
> to be able to send a shutdown event to the guest.  At least with modern
> guest kernels and a userspace that is up and running, this means that
> system_powerdown from the qemu monitor should now work correctly on pseries
> guests.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
>  hw/ppc/Makefile.objs |    1 +
>  hw/spapr.c           |   14 ++-
>  hw/spapr.h           |    8 ++
>  hw/spapr_events.c    |  321 ++++++++++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 342 insertions(+), 2 deletions(-)
>  create mode 100644 hw/spapr_events.c
>
> diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
> index 951e407..8fe2123 100644
> --- a/hw/ppc/Makefile.objs
> +++ b/hw/ppc/Makefile.objs
> @@ -11,6 +11,7 @@ obj-y += ppc_newworld.o
>  obj-$(CONFIG_PSERIES) += spapr.o spapr_hcall.o spapr_rtas.o spapr_vio.o
>  obj-$(CONFIG_PSERIES) += xics.o spapr_vty.o spapr_llan.o spapr_vscsi.o
>  obj-$(CONFIG_PSERIES) += spapr_pci.o pci-hotplug.o spapr_iommu.o
> +obj-$(CONFIG_PSERIES) += spapr_events.o
>  # PowerPC 4xx boards
>  obj-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
>  obj-y += ppc440_bamboo.o
> diff --git a/hw/spapr.c b/hw/spapr.c
> index 09b8e99..64c35a8 100644
> --- a/hw/spapr.c
> +++ b/hw/spapr.c
> @@ -232,7 +232,8 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
>                                     target_phys_addr_t initrd_size,
>                                     target_phys_addr_t kernel_size,
>                                     const char *boot_device,
> -                                   const char *kernel_cmdline)
> +                                   const char *kernel_cmdline,
> +                                   uint32_t epow_irq)
>  {
>      void *fdt;
>      CPUPPCState *env;
> @@ -403,6 +404,8 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
>      _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
>          refpoints, sizeof(refpoints))));
>
> +    _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
> +
>      _FDT((fdt_end_node(fdt)));
>
>      /* interrupt controller */
> @@ -433,6 +436,9 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
>
>      _FDT((fdt_end_node(fdt)));
>
> +    /* event-sources */
> +    spapr_events_fdt_skel(fdt, epow_irq);
> +
>      _FDT((fdt_end_node(fdt))); /* close root node */
>      _FDT((fdt_finish(fdt)));
>
> @@ -794,6 +800,9 @@ static void ppc_spapr_init(ram_addr_t ram_size,
>      spapr->icp = xics_system_init(XICS_IRQS);
>      spapr->next_irq = 16;
>
> +    /* Set up EPOW events infrastructure */
> +    spapr_events_init(spapr);
> +
>      /* Set up IOMMU */
>      spapr_iommu_init();
>
> @@ -902,7 +911,8 @@ static void ppc_spapr_init(ram_addr_t ram_size,
>      spapr->fdt_skel = spapr_create_fdt_skel(cpu_model,
>                                              initrd_base, initrd_size,
>                                              kernel_size,
> -                                            boot_device, kernel_cmdline);
> +                                            boot_device, kernel_cmdline,
> +                                            spapr->epow_irq);
>      assert(spapr->fdt_skel != NULL);
>  }
>
> diff --git a/hw/spapr.h b/hw/spapr.h
> index e984e3f..54960f3 100644
> --- a/hw/spapr.h
> +++ b/hw/spapr.h
> @@ -26,6 +26,9 @@ typedef struct sPAPREnvironment {
>      int rtc_offset;
>      char *cpu_model;
>      bool has_graphics;
> +
> +    uint32_t epow_irq;
> +    Notifier epow_notifier;
>  } sPAPREnvironment;
>
>  #define H_SUCCESS         0
> @@ -335,7 +338,12 @@ typedef struct sPAPRTCE {
>  #define SPAPR_VIO_BASE_LIOBN    0x00000000
>  #define SPAPR_PCI_BASE_LIOBN    0x80000000
>
> +#define RTAS_ERROR_LOG_MAX      2048
> +
> +
>  void spapr_iommu_init(void);
> +void spapr_events_init(sPAPREnvironment *spapr);
> +void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq);
>  DMAContext *spapr_tce_new_dma_context(uint32_t liobn, size_t window_size);
>  void spapr_tce_free(DMAContext *dma);
>  void spapr_tce_reset(DMAContext *dma);
> diff --git a/hw/spapr_events.c b/hw/spapr_events.c
> new file mode 100644
> index 0000000..18ccd4a
> --- /dev/null
> +++ b/hw/spapr_events.c
> @@ -0,0 +1,321 @@
> +/*
> + * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
> + *
> + * RTAS events handling
> + *
> + * Copyright (c) 2012 David Gibson, IBM Corporation.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + *
> + */
> +#include "cpu.h"
> +#include "sysemu.h"
> +#include "qemu-char.h"
> +#include "hw/qdev.h"
> +#include "device_tree.h"
> +
> +#include "hw/spapr.h"
> +#include "hw/spapr_vio.h"
> +
> +#include <libfdt.h>
> +
> +struct rtas_error_log {

CODING_STYLE requires CamelCase for structure names and a typedef.

> +    uint32_t summary;
> +#define RTAS_LOG_VERSION_MASK                   0xff000000
> +#define   RTAS_LOG_VERSION_6                    0x06000000
> +#define RTAS_LOG_SEVERITY_MASK                  0x00e00000
> +#define   RTAS_LOG_SEVERITY_ALREADY_REPORTED    0x00c00000
> +#define   RTAS_LOG_SEVERITY_FATAL               0x00a00000
> +#define   RTAS_LOG_SEVERITY_ERROR               0x00800000
> +#define   RTAS_LOG_SEVERITY_ERROR_SYNC          0x00600000
> +#define   RTAS_LOG_SEVERITY_WARNING             0x00400000
> +#define   RTAS_LOG_SEVERITY_EVENT               0x00200000
> +#define   RTAS_LOG_SEVERITY_NO_ERROR            0x00000000
> +#define RTAS_LOG_DISPOSITION_MASK               0x00180000
> +#define   RTAS_LOG_DISPOSITION_FULLY_RECOVERED  0x00000000
> +#define   RTAS_LOG_DISPOSITION_LIMITED_RECOVERY 0x00080000
> +#define   RTAS_LOG_DISPOSITION_NOT_RECOVERED    0x00100000
> +#define RTAS_LOG_OPTIONAL_PART_PRESENT          0x00040000
> +#define RTAS_LOG_INITIATOR_MASK                 0x0000f000
> +#define   RTAS_LOG_INITIATOR_UNKNOWN            0x00000000
> +#define   RTAS_LOG_INITIATOR_CPU                0x00001000
> +#define   RTAS_LOG_INITIATOR_PCI                0x00002000
> +#define   RTAS_LOG_INITIATOR_MEMORY             0x00004000
> +#define   RTAS_LOG_INITIATOR_HOTPLUG            0x00006000
> +#define RTAS_LOG_TARGET_MASK                    0x00000f00
> +#define   RTAS_LOG_TARGET_UNKNOWN               0x00000000
> +#define   RTAS_LOG_TARGET_CPU                   0x00000100
> +#define   RTAS_LOG_TARGET_PCI                   0x00000200
> +#define   RTAS_LOG_TARGET_MEMORY                0x00000400
> +#define   RTAS_LOG_TARGET_HOTPLUG               0x00000600
> +#define RTAS_LOG_TYPE_MASK                      0x000000ff
> +#define   RTAS_LOG_TYPE_OTHER                   0x00000000
> +#define   RTAS_LOG_TYPE_RETRY                   0x00000001
> +#define   RTAS_LOG_TYPE_TCE_ERR                 0x00000002
> +#define   RTAS_LOG_TYPE_INTERN_DEV_FAIL         0x00000003
> +#define   RTAS_LOG_TYPE_TIMEOUT                 0x00000004
> +#define   RTAS_LOG_TYPE_DATA_PARITY             0x00000005
> +#define   RTAS_LOG_TYPE_ADDR_PARITY             0x00000006
> +#define   RTAS_LOG_TYPE_CACHE_PARITY            0x00000007
> +#define   RTAS_LOG_TYPE_ADDR_INVALID            0x00000008
> +#define   RTAS_LOG_TYPE_ECC_UNCORR              0x00000009
> +#define   RTAS_LOG_TYPE_ECC_CORR                0x0000000a
> +#define   RTAS_LOG_TYPE_EPOW                    0x00000040
> +    uint32_t extended_length;
> +} QEMU_PACKED;
> +
> +struct rtas_event_log_v6 {
> +    uint8_t b0;
> +#define RTAS_LOG_V6_B0_VALID                          0x80
> +#define RTAS_LOG_V6_B0_UNRECOVERABLE_ERROR            0x40
> +#define RTAS_LOG_V6_B0_RECOVERABLE_ERROR              0x20
> +#define RTAS_LOG_V6_B0_DEGRADED_OPERATION             0x10
> +#define RTAS_LOG_V6_B0_PREDICTIVE_ERROR               0x08
> +#define RTAS_LOG_V6_B0_NEW_LOG                        0x04
> +#define RTAS_LOG_V6_B0_BIGENDIAN                      0x02
> +    uint8_t _resv1;

Please don't use identifiers with leading underscores.

> +    uint8_t b2;
> +#define RTAS_LOG_V6_B2_POWERPC_FORMAT                 0x80
> +#define RTAS_LOG_V6_B2_LOG_FORMAT_MASK                0x0f
> +#define   RTAS_LOG_V6_B2_LOG_FORMAT_PLATFORM_EVENT    0x0e
> +    uint8_t _resv2[9];
> +    uint32_t company;
> +#define RTAS_LOG_V6_COMPANY_IBM                 0x49424d00 /* IBM<null> */
> +} QEMU_PACKED;
> +
> +struct rtas_event_log_v6_section_header {
> +    uint16_t section_id;
> +    uint16_t section_length;
> +    uint8_t section_version;
> +    uint8_t section_subtype;
> +    uint16_t creator_component_id;
> +} QEMU_PACKED;
> +
> +struct rtas_event_log_v6_maina {
> +#define RTAS_LOG_V6_SECTION_ID_MAINA                0x5048 /* PH */
> +    struct rtas_event_log_v6_section_header hdr;
> +    uint32_t creation_date; /* BCD: YYYYMMDD */
> +    uint32_t creation_time; /* BCD: HHMMSS00 */
> +    uint8_t _platform1[8];
> +    char creator_id;
> +    uint8_t _resv1[2];
> +    uint8_t section_count;
> +    uint8_t _resv2[4];
> +    uint8_t _platform2[8];
> +    uint32_t plid;
> +    uint8_t _platform3[4];
> +} QEMU_PACKED;
> +
> +struct rtas_event_log_v6_mainb {
> +#define RTAS_LOG_V6_SECTION_ID_MAINB                0x5548 /* UH */
> +    struct rtas_event_log_v6_section_header hdr;
> +    uint8_t subsystem_id;
> +    uint8_t _platform1;
> +    uint8_t event_severity;
> +    uint8_t event_subtype;
> +    uint8_t _platform2[4];
> +    uint8_t _resv1[2];
> +    uint16_t action_flags;
> +    uint8_t _resv2[4];
> +} QEMU_PACKED;
> +
> +struct rtas_event_log_v6_epow {
> +#define RTAS_LOG_V6_SECTION_ID_EPOW                 0x4550 /* EP */
> +    struct rtas_event_log_v6_section_header hdr;
> +    uint8_t sensor_value;
> +#define RTAS_LOG_V6_EPOW_ACTION_RESET                    0
> +#define RTAS_LOG_V6_EPOW_ACTION_WARN_COOLING             1
> +#define RTAS_LOG_V6_EPOW_ACTION_WARN_POWER               2
> +#define RTAS_LOG_V6_EPOW_ACTION_SYSTEM_SHUTDOWN          3
> +#define RTAS_LOG_V6_EPOW_ACTION_SYSTEM_HALT              4
> +#define RTAS_LOG_V6_EPOW_ACTION_MAIN_ENCLOSURE           5
> +#define RTAS_LOG_V6_EPOW_ACTION_POWER_OFF                7
> +    uint8_t event_modifier;
> +#define RTAS_LOG_V6_EPOW_MODIFIER_NORMAL                 1
> +#define RTAS_LOG_V6_EPOW_MODIFIER_ON_UPS                 2
> +#define RTAS_LOG_V6_EPOW_MODIFIER_CRITICAL               3
> +#define RTAS_LOG_V6_EPOW_MODIFIER_TEMPERATURE            4
> +    uint8_t extended_modifier;
> +#define RTAS_LOG_V6_EPOW_XMODIFIER_SYSTEM_WIDE           0
> +#define RTAS_LOG_V6_EPOW_XMODIFIER_PARTITION_SPECIFIC    1
> +    uint8_t _resv;
> +    uint64_t reason_code;
> +} QEMU_PACKED;
> +
> +struct epow_log_full {
> +    struct rtas_error_log hdr;
> +    struct rtas_event_log_v6 v6hdr;
> +    struct rtas_event_log_v6_maina maina;
> +    struct rtas_event_log_v6_mainb mainb;
> +    struct rtas_event_log_v6_epow epow;
> +} QEMU_PACKED;
> +
> +#define EVENT_MASK_INTERNAL_ERRORS           0x80000000
> +#define EVENT_MASK_EPOW                      0x40000000
> +#define EVENT_MASK_HOTPLUG                   0x10000000
> +#define EVENT_MASK_IO                        0x08000000
> +
> +#define _FDT(exp) \
> +    do { \
> +        int ret = (exp);                                           \
> +        if (ret < 0) {                                             \
> +            fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
> +                    #exp, fdt_strerror(ret));                      \
> +            exit(1);                                               \
> +        }                                                          \
> +    } while (0)
> +
> +void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq)
> +{
> +    uint32_t epow_irq_ranges[] = {cpu_to_be32(epow_irq), cpu_to_be32(1)};
> +    uint32_t epow_interrupts[] = {cpu_to_be32(epow_irq), 0};
> +
> +    _FDT((fdt_begin_node(fdt, "event-sources")));
> +
> +    _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
> +    _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
> +    _FDT((fdt_property(fdt, "interrupt-ranges",
> +                       epow_irq_ranges, sizeof(epow_irq_ranges))));
> +
> +    _FDT((fdt_begin_node(fdt, "epow-events")));
> +    _FDT((fdt_property(fdt, "interrupts",
> +                       epow_interrupts, sizeof(epow_interrupts))));
> +    _FDT((fdt_end_node(fdt)));
> +
> +    _FDT((fdt_end_node(fdt)));
> +}
> +
> +static struct epow_log_full *pending_epow;
> +static uint32_t next_plid;

Please don't use globals, I think you should be able to move them to
sPAPREnvironment instead.

> +
> +static void spapr_powerdown_req(Notifier *n, void *opaque)
> +{
> +    sPAPREnvironment *spapr = container_of(n, sPAPREnvironment, epow_notifier);
> +    struct rtas_error_log *hdr;
> +    struct rtas_event_log_v6 *v6hdr;
> +    struct rtas_event_log_v6_maina *maina;
> +    struct rtas_event_log_v6_mainb *mainb;
> +    struct rtas_event_log_v6_epow *epow;
> +    struct tm tm;
> +    int year;
> +
> +    if (pending_epow) {
> +        /* For now, we just throw away earlier events if two come
> +         * along before any are consumed.  This is sufficient for our
> +         * powerdown messages, but we'll need more if we do more
> +         * general error/event logging */
> +        g_free(pending_epow);
> +    }
> +    pending_epow = g_malloc0(sizeof(*pending_epow));
> +    hdr = &pending_epow->hdr;
> +    v6hdr = &pending_epow->v6hdr;
> +    maina = &pending_epow->maina;
> +    mainb = &pending_epow->mainb;
> +    epow = &pending_epow->epow;
> +
> +    hdr->summary = cpu_to_be32(RTAS_LOG_VERSION_6
> +                               | RTAS_LOG_SEVERITY_EVENT
> +                               | RTAS_LOG_DISPOSITION_NOT_RECOVERED
> +                               | RTAS_LOG_OPTIONAL_PART_PRESENT
> +                               | RTAS_LOG_TYPE_EPOW);
> +    hdr->extended_length = cpu_to_be32(sizeof(*pending_epow)
> +                                       - sizeof(pending_epow->hdr));
> +
> +    v6hdr->b0 = RTAS_LOG_V6_B0_VALID | RTAS_LOG_V6_B0_NEW_LOG
> +        | RTAS_LOG_V6_B0_BIGENDIAN;
> +    v6hdr->b2 = RTAS_LOG_V6_B2_POWERPC_FORMAT
> +        | RTAS_LOG_V6_B2_LOG_FORMAT_PLATFORM_EVENT;
> +    v6hdr->company = cpu_to_be32(RTAS_LOG_V6_COMPANY_IBM);
> +
> +    maina->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINA);
> +    maina->hdr.section_length = cpu_to_be16(sizeof(*maina));
> +    /* FIXME: section version, subtype and creator id? */
> +    qemu_get_timedate(&tm, spapr->rtc_offset);
> +    year = tm.tm_year + 1900;
> +    maina->creation_date = cpu_to_be32((to_bcd(year / 100) << 24)
> +                                       | (to_bcd(year % 100) << 16)
> +                                       | (to_bcd(tm.tm_mon + 1) << 8)
> +                                       | to_bcd(tm.tm_mday));
> +    maina->creation_time = cpu_to_be32((to_bcd(tm.tm_hour) << 24)
> +                                       | (to_bcd(tm.tm_min) << 16)
> +                                       | (to_bcd(tm.tm_sec) << 8));
> +    maina->creator_id = 'H'; /* Hypervisor */
> +    maina->section_count = 3; /* Main-A, Main-B and EPOW */
> +    maina->plid = next_plid++;
> +
> +    mainb->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINB);
> +    mainb->hdr.section_length = cpu_to_be16(sizeof(*mainb));
> +    /* FIXME: section version, subtype and creator id? */
> +    mainb->subsystem_id = 0xa0; /* External environment */
> +    mainb->event_severity = 0x00; /* Informational / non-error */
> +    mainb->event_subtype = 0xd0; /* Normal shutdown */
> +
> +    epow->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_EPOW);
> +    epow->hdr.section_length = cpu_to_be16(sizeof(*epow));
> +    epow->hdr.section_version = 2; /* includes extended modifier */
> +    /* FIXME: section subtype and creator id? */
> +    epow->sensor_value = RTAS_LOG_V6_EPOW_ACTION_SYSTEM_SHUTDOWN;
> +    epow->event_modifier = RTAS_LOG_V6_EPOW_MODIFIER_NORMAL;
> +    epow->extended_modifier = RTAS_LOG_V6_EPOW_XMODIFIER_PARTITION_SPECIFIC;
> +
> +    qemu_irq_pulse(xics_get_qirq(spapr->icp, spapr->epow_irq));
> +}
> +
> +static void check_exception(sPAPREnvironment *spapr,
> +                            uint32_t token, uint32_t nargs,
> +                            target_ulong args,
> +                            uint32_t nret, target_ulong rets)
> +{
> +    uint32_t mask, buf, len;
> +    uint64_t xinfo;
> +
> +    if ((nargs < 6) || (nargs > 7) || nret != 1) {
> +        rtas_st(rets, 0, -3);
> +        return;
> +    }
> +
> +    xinfo = rtas_ld(args, 1);
> +    mask = rtas_ld(args, 2);
> +    buf = rtas_ld(args, 4);
> +    len = rtas_ld(args, 5);
> +    if (nargs == 7) {
> +        xinfo |= (uint64_t)rtas_ld(args, 6) << 32;
> +    }
> +
> +    if ((mask & EVENT_MASK_EPOW) && pending_epow) {
> +        if (sizeof(*pending_epow) < len) {
> +            len = sizeof(*pending_epow);
> +        }
> +
> +        cpu_physical_memory_write(buf, pending_epow, len);
> +        g_free(pending_epow);
> +        pending_epow = NULL;
> +        rtas_st(rets, 0, 0);
> +    } else {
> +        rtas_st(rets, 0, 1);
> +    }
> +}
> +
> +void spapr_events_init(sPAPREnvironment *spapr)
> +{
> +    spapr->epow_irq = spapr_allocate_msi(0);
> +    spapr->epow_notifier.notify = spapr_powerdown_req;
> +    qemu_register_powerdown_notifier(&spapr->epow_notifier);
> +    spapr_rtas_register("check-exception", check_exception);
> +}
> --
> 1.7.10.4
>
>

Re: [Qemu-devel] [0/4] Pending ppc and pseries patches

[Alexander Graf]

On 09.10.2012, at 06:17, David Gibson wrote:

> Hi Alex,
> 
> Here are some assorted pending pseries patches which should be ready
> to go.  This clears the decks ready for a big series to add
> savevm/migration support for pseries.
> 

Thanks, applied 1, 3 and 4. The FPU patch is still broken :)


Alex