From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH 0/7] ARM: tegra30: cpuidle: add LP2 support
Date: Tue, 09 Oct 2012 16:26:03 -0600 [thread overview]
Message-ID: <5074A47B.3050906@wwwdotorg.org> (raw)
In-Reply-To: <1349691981-31038-1-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 10/08/2012 04:26 AM, Joseph Lo wrote:
> The CPU idle LP2 is a power gating idle mode for Tegra30. It supports the
> secondary CPUs (i.e., CPU1-CPU3) to go into LP2 dynamically. When any of
> the secondary CPUs go into LP2, it can be power gated alone. There is a
> limitation on CPU0. The CPU0 can go into LP2 only when all secondary CPUs
> are already in LP2. After CPU0 is in LP2, the CPU rail can be turned off.
>
> Verified on Seaboard(Tegra20) and Cardhu(Tegra30).
What's the most comprehensive way to verify this? I booted Cardhu with
these patches applied and saw that all CPU cores did enter both idle
states. However, I'm unsure what the best way to stress the system is,
i.e. how would I stress and test for correct handling of all the L2
caching/SMP coherency issues, etc.
WARNING: multiple messages have this Message-ID (diff)
From: swarren@wwwdotorg.org (Stephen Warren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/7] ARM: tegra30: cpuidle: add LP2 support
Date: Tue, 09 Oct 2012 16:26:03 -0600 [thread overview]
Message-ID: <5074A47B.3050906@wwwdotorg.org> (raw)
In-Reply-To: <1349691981-31038-1-git-send-email-josephl@nvidia.com>
On 10/08/2012 04:26 AM, Joseph Lo wrote:
> The CPU idle LP2 is a power gating idle mode for Tegra30. It supports the
> secondary CPUs (i.e., CPU1-CPU3) to go into LP2 dynamically. When any of
> the secondary CPUs go into LP2, it can be power gated alone. There is a
> limitation on CPU0. The CPU0 can go into LP2 only when all secondary CPUs
> are already in LP2. After CPU0 is in LP2, the CPU rail can be turned off.
>
> Verified on Seaboard(Tegra20) and Cardhu(Tegra30).
What's the most comprehensive way to verify this? I booted Cardhu with
these patches applied and saw that all CPU cores did enter both idle
states. However, I'm unsure what the best way to stress the system is,
i.e. how would I stress and test for correct handling of all the L2
caching/SMP coherency issues, etc.
next prev parent reply other threads:[~2012-10-09 22:26 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-08 10:26 [PATCH 0/7] ARM: tegra30: cpuidle: add LP2 support Joseph Lo
2012-10-08 10:26 ` Joseph Lo
[not found] ` <1349691981-31038-1-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-10-08 10:26 ` [PATCH 1/7] ARM: tegra: cpuidle: separate cpuidle driver for different chips Joseph Lo
2012-10-08 10:26 ` Joseph Lo
[not found] ` <1349691981-31038-2-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-10-09 22:22 ` Stephen Warren
2012-10-09 22:22 ` Stephen Warren
[not found] ` <5074A3C3.1080006-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-11 6:42 ` Joseph Lo
2012-10-11 6:42 ` Joseph Lo
2012-10-08 10:26 ` [PATCH 2/7] ARM: tegra: cpuidle: add LP2 resume function Joseph Lo
2012-10-08 10:26 ` Joseph Lo
[not found] ` <1349691981-31038-3-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-10-09 22:29 ` Stephen Warren
2012-10-09 22:29 ` Stephen Warren
[not found] ` <5074A559.8030206-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-11 7:08 ` Joseph Lo
2012-10-11 7:08 ` Joseph Lo
2012-10-08 10:26 ` [PATCH 3/7] ARM: tegra30: cpuidle: add LP2 driver for secondary CPUs Joseph Lo
2012-10-08 10:26 ` Joseph Lo
[not found] ` <1349691981-31038-4-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-10-08 16:35 ` Lorenzo Pieralisi
2012-10-08 16:35 ` Lorenzo Pieralisi
[not found] ` <20121008163504.GC5377-7AyDDHkRsp3ZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2012-10-09 4:13 ` Joseph Lo
2012-10-09 4:13 ` Joseph Lo
[not found] ` <1349755995.15153.145.camel-yx3yKKdKkHfc7b1ADBJPm0n48jw8i0AO@public.gmane.org>
2012-10-09 8:38 ` Lorenzo Pieralisi
2012-10-09 8:38 ` Lorenzo Pieralisi
[not found] ` <20121009083804.GA11840-7AyDDHkRsp3ZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2012-10-09 9:18 ` Joseph Lo
2012-10-09 9:18 ` Joseph Lo
[not found] ` <1349774337.16173.8.camel-yx3yKKdKkHfc7b1ADBJPm0n48jw8i0AO@public.gmane.org>
2012-10-09 9:42 ` Lorenzo Pieralisi
2012-10-09 9:42 ` Lorenzo Pieralisi
2012-10-09 15:55 ` Antti P Miettinen
2012-10-09 22:38 ` Stephen Warren
2012-10-09 22:38 ` Stephen Warren
[not found] ` <5074A74A.8010803-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-11 9:15 ` Joseph Lo
2012-10-11 9:15 ` Joseph Lo
[not found] ` <1349946918.19413.130.camel-yx3yKKdKkHfc7b1ADBJPm0n48jw8i0AO@public.gmane.org>
2012-10-11 16:24 ` Stephen Warren
2012-10-11 16:24 ` Stephen Warren
[not found] ` <5076F2AE.6030509-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-12 3:21 ` Joseph Lo
2012-10-12 3:21 ` Joseph Lo
2012-10-30 22:03 ` Antti P Miettinen
[not found] ` <87sj8vr517.fsf-sS3DoGclAPwgdTl23f3CEMVPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2012-10-30 22:27 ` Stephen Warren
2012-10-30 22:27 ` Stephen Warren
[not found] ` <5090544D.3020408-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-31 1:26 ` Joseph Lo
2012-10-31 1:26 ` Joseph Lo
2012-10-08 10:26 ` [PATCH 4/7] ARM: tegra30: common: enable csite clock Joseph Lo
2012-10-08 10:26 ` Joseph Lo
[not found] ` <1349691981-31038-5-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-10-09 22:38 ` Stephen Warren
2012-10-09 22:38 ` Stephen Warren
[not found] ` <5074A77D.9080500-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-11 10:28 ` Joseph Lo
2012-10-11 10:28 ` Joseph Lo
2012-10-08 10:26 ` [PATCH 5/7] ARM: tegra30: clocks: add CPU low-power function into tegra_cpu_car_ops Joseph Lo
2012-10-08 10:26 ` Joseph Lo
2012-10-08 10:26 ` [PATCH 6/7] ARM: tegra30: flowctrl: add cpu_suspend_exter/exit function Joseph Lo
2012-10-08 10:26 ` Joseph Lo
2012-10-08 10:26 ` [PATCH 7/7] ARM: tegra30: cpuidle: add LP2 driver for CPU0 Joseph Lo
2012-10-08 10:26 ` Joseph Lo
[not found] ` <1349691981-31038-8-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-10-09 22:49 ` Stephen Warren
2012-10-09 22:49 ` Stephen Warren
[not found] ` <5074AA0E.2080508-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-11 11:24 ` Joseph Lo
2012-10-11 11:24 ` Joseph Lo
[not found] ` <1349954685.19413.207.camel-yx3yKKdKkHfc7b1ADBJPm0n48jw8i0AO@public.gmane.org>
2012-10-11 16:37 ` Stephen Warren
2012-10-11 16:37 ` Stephen Warren
[not found] ` <5076F5CB.4020200-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-11 16:48 ` Colin Cross
2012-10-11 16:48 ` Colin Cross
[not found] ` <CAMbhsRScnEaEeyqGz6tfYQMHXaZva4UeHtFY4C9Vvu1MrKXPNg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2012-10-12 7:11 ` Joseph Lo
2012-10-12 7:11 ` Joseph Lo
2012-10-12 7:40 ` Joseph Lo
2012-10-12 7:40 ` Joseph Lo
2012-10-12 7:54 ` Shawn Guo
2012-10-12 7:54 ` Shawn Guo
[not found] ` <20121012075358.GA4962-rvtDTF3kK1ictlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org>
2012-10-12 8:24 ` Joseph Lo
2012-10-12 8:24 ` Joseph Lo
[not found] ` <1350030264.15495.14.camel-yx3yKKdKkHfc7b1ADBJPm0n48jw8i0AO@public.gmane.org>
2012-10-12 8:30 ` Shawn Guo
2012-10-12 8:30 ` Shawn Guo
[not found] ` <20121012083017.GB4962-rvtDTF3kK1ictlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org>
2012-10-12 20:50 ` Colin Cross
2012-10-12 20:50 ` Colin Cross
2012-10-15 16:28 ` Use coupled cpuidle on imx6q Shawn Guo
2012-10-15 16:28 ` Shawn Guo
[not found] ` <20121015162842.GD24393-rvtDTF3kK1ictlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org>
2012-10-15 22:58 ` Colin Cross
2012-10-15 22:58 ` Colin Cross
2012-10-12 20:46 ` [PATCH 7/7] ARM: tegra30: cpuidle: add LP2 driver for CPU0 Colin Cross
2012-10-12 20:46 ` Colin Cross
2012-10-12 7:07 ` Joseph Lo
2012-10-12 7:07 ` Joseph Lo
[not found] ` <1350025676.20241.82.camel-yx3yKKdKkHfc7b1ADBJPm0n48jw8i0AO@public.gmane.org>
2012-10-12 21:04 ` Stephen Warren
2012-10-12 21:04 ` Stephen Warren
[not found] ` <507885D4.10604-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-15 7:56 ` Joseph Lo
2012-10-15 7:56 ` Joseph Lo
[not found] ` <1350287799.23354.23.camel-yx3yKKdKkHfc7b1ADBJPm0n48jw8i0AO@public.gmane.org>
2012-10-15 15:59 ` Stephen Warren
2012-10-15 15:59 ` Stephen Warren
[not found] ` <507C32E8.1040701-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-15 22:33 ` Colin Cross
2012-10-15 22:33 ` Colin Cross
[not found] ` <CAMbhsRQg3-QwSfvuU1n7mUq1QhtU2Q+yHUpZ7PtRYQot=pijng-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2012-10-16 8:13 ` Peter De Schrijver
2012-10-16 8:13 ` Peter De Schrijver
2012-10-16 8:06 ` Peter De Schrijver
2012-10-16 8:06 ` Peter De Schrijver
[not found] ` <20121016080634.GG3196-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2012-10-16 17:03 ` Stephen Warren
2012-10-16 17:03 ` Stephen Warren
[not found] ` <507D936F.70905-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-18 9:24 ` Peter De Schrijver
2012-10-18 9:24 ` Peter De Schrijver
[not found] ` <20121018092440.GS3196-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2012-10-25 14:08 ` Peter De Schrijver
2012-10-25 14:08 ` Peter De Schrijver
2012-10-09 22:26 ` Stephen Warren [this message]
2012-10-09 22:26 ` [PATCH 0/7] ARM: tegra30: cpuidle: add LP2 support Stephen Warren
[not found] ` <5074A47B.3050906-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-11 6:39 ` Joseph Lo
2012-10-11 6:39 ` Joseph Lo
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