From: Benoit Cousson <b-cousson@ti.com>
To: Sourav <sourav.poddar@ti.com>
Cc: Sebastien Guiriec <s-guiriec@ti.com>,
Tony Lindgren <tony@atomide.com>,
Peter Ujfalusi <peter.ujfalusi@ti.com>,
linux-omap@vger.kernel.org,
Santosh Shilimkar <santosh.shilimkar@ti.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 3/4] ARM/dts: omap5: Update UART with address space and interrupts
Date: Mon, 22 Oct 2012 13:57:00 +0200 [thread overview]
Message-ID: <5085348C.60105@ti.com> (raw)
In-Reply-To: <50852AF9.10703@ti.com>
Hi Sourav,
On 10/22/2012 01:16 PM, Sourav wrote:
> Hi Sebastien,
> On Monday 22 October 2012 03:52 PM, Sebastien Guiriec wrote:
>> Add base address and interrupt line inside Device Tree data for
> Incomplete sentence!
>> Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com>
>> ---
>> arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++--
>> 1 file changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
>> index 6c22e1b..413df94 100644
>> --- a/arch/arm/boot/dts/omap5.dtsi
>> +++ b/arch/arm/boot/dts/omap5.dtsi
>> @@ -237,36 +237,48 @@
>> uart1: serial@4806a000 {
>> compatible = "ti,omap4-uart";
>> + reg = <0x4806a000 0x100>;
>> + interrupts = <0 72 0x4>;
>> ti,hwmods = "uart1";
>> clock-frequency = <48000000>;
>> };
>> uart2: serial@4806c000 {
>> compatible = "ti,omap4-uart";
>> + reg = <0x4806c000 0x100>;
>> + interrupts = <0 73 0x4>;
>> ti,hwmods = "uart2";
>> clock-frequency = <48000000>;
>> };
>> uart3: serial@48020000 {
>> compatible = "ti,omap4-uart";
>> + reg = <0x48020000 0x100>;
>> + interrupts = <0 74 0x4>;
>> ti,hwmods = "uart3";
>> clock-frequency = <48000000>;
>> };
>> uart4: serial@4806e000 {
>> compatible = "ti,omap4-uart";
>> + reg = <0x4806e000 0x100>;
>> + interrupts = <0 70 0x4>;
>> ti,hwmods = "uart4";
>> clock-frequency = <48000000>;
>> };
>> uart5: serial@48066000 {
>> - compatible = "ti,omap5-uart";
>> + compatible = "ti,omap4-uart";
>> + reg = <0x48066000 0x100>;
>> + interrupts = <0 105 0x4>;
> In Omap5 TRM, the interrupt number mentioned for uart5 is 138. How is
> 105 coming?
It is from hwmod and thus from the HW spec. It looks like the TRM is
wrong... or the HW spec :-)
>> ti,hwmods = "uart5";
>> clock-frequency = <48000000>;
>> };
>> uart6: serial@48068000 {
>> - compatible = "ti,omap6-uart";
>> + compatible = "ti,omap4-uart";
>> + reg = <0x48068000 0x100>;
>> + interrupts = <0 106 0x4>;
> Same here, TRM shows this number to be 139 ?
Same source.
Regards,
Benoit
WARNING: multiple messages have this Message-ID (diff)
From: b-cousson@ti.com (Benoit Cousson)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/4] ARM/dts: omap5: Update UART with address space and interrupts
Date: Mon, 22 Oct 2012 13:57:00 +0200 [thread overview]
Message-ID: <5085348C.60105@ti.com> (raw)
In-Reply-To: <50852AF9.10703@ti.com>
Hi Sourav,
On 10/22/2012 01:16 PM, Sourav wrote:
> Hi Sebastien,
> On Monday 22 October 2012 03:52 PM, Sebastien Guiriec wrote:
>> Add base address and interrupt line inside Device Tree data for
> Incomplete sentence!
>> Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com>
>> ---
>> arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++--
>> 1 file changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
>> index 6c22e1b..413df94 100644
>> --- a/arch/arm/boot/dts/omap5.dtsi
>> +++ b/arch/arm/boot/dts/omap5.dtsi
>> @@ -237,36 +237,48 @@
>> uart1: serial at 4806a000 {
>> compatible = "ti,omap4-uart";
>> + reg = <0x4806a000 0x100>;
>> + interrupts = <0 72 0x4>;
>> ti,hwmods = "uart1";
>> clock-frequency = <48000000>;
>> };
>> uart2: serial at 4806c000 {
>> compatible = "ti,omap4-uart";
>> + reg = <0x4806c000 0x100>;
>> + interrupts = <0 73 0x4>;
>> ti,hwmods = "uart2";
>> clock-frequency = <48000000>;
>> };
>> uart3: serial at 48020000 {
>> compatible = "ti,omap4-uart";
>> + reg = <0x48020000 0x100>;
>> + interrupts = <0 74 0x4>;
>> ti,hwmods = "uart3";
>> clock-frequency = <48000000>;
>> };
>> uart4: serial at 4806e000 {
>> compatible = "ti,omap4-uart";
>> + reg = <0x4806e000 0x100>;
>> + interrupts = <0 70 0x4>;
>> ti,hwmods = "uart4";
>> clock-frequency = <48000000>;
>> };
>> uart5: serial at 48066000 {
>> - compatible = "ti,omap5-uart";
>> + compatible = "ti,omap4-uart";
>> + reg = <0x48066000 0x100>;
>> + interrupts = <0 105 0x4>;
> In Omap5 TRM, the interrupt number mentioned for uart5 is 138. How is
> 105 coming?
It is from hwmod and thus from the HW spec. It looks like the TRM is
wrong... or the HW spec :-)
>> ti,hwmods = "uart5";
>> clock-frequency = <48000000>;
>> };
>> uart6: serial at 48068000 {
>> - compatible = "ti,omap6-uart";
>> + compatible = "ti,omap4-uart";
>> + reg = <0x48068000 0x100>;
>> + interrupts = <0 106 0x4>;
> Same here, TRM shows this number to be 139 ?
Same source.
Regards,
Benoit
next prev parent reply other threads:[~2012-10-22 11:57 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-22 10:22 [PATCH 0/4] ARM/dts: Update OMAP5 with address space and interrupts Sebastien Guiriec
2012-10-22 10:22 ` Sebastien Guiriec
2012-10-22 10:22 ` [PATCH 1/4] ARM/dts: omap5: Update GPIO with address space and interrupt Sebastien Guiriec
2012-10-22 10:22 ` Sebastien Guiriec
2012-10-22 10:22 ` [PATCH 2/4] ARM/dts: omap5: Update I2C with address space and interrupts Sebastien Guiriec
2012-10-22 10:22 ` Sebastien Guiriec
2012-10-22 11:14 ` Shubhrajyoti Datta
2012-10-22 11:14 ` Shubhrajyoti Datta
2012-10-22 10:22 ` [PATCH 3/4] ARM/dts: omap5: Update UART " Sebastien Guiriec
2012-10-22 10:22 ` Sebastien Guiriec
2012-10-22 11:16 ` Sourav
2012-10-22 11:16 ` Sourav
2012-10-22 11:57 ` Benoit Cousson [this message]
2012-10-22 11:57 ` Benoit Cousson
2012-10-22 12:07 ` Benoit Cousson
2012-10-22 12:07 ` Benoit Cousson
2012-10-22 12:27 ` Sourav
2012-10-22 12:27 ` Sourav
2012-10-22 12:31 ` Felipe Balbi
2012-10-22 12:31 ` Felipe Balbi
2012-10-22 12:50 ` Benoit Cousson
2012-10-22 12:50 ` Benoit Cousson
2012-10-22 12:56 ` Sourav
2012-10-22 12:56 ` Sourav
2012-10-22 13:55 ` Sourav
2012-10-22 13:55 ` Sourav
2012-10-22 10:22 ` [PATCH 4/4] ARM/dts: omap5: Update MMC " Sebastien Guiriec
2012-10-22 10:22 ` Sebastien Guiriec
2012-10-22 14:11 ` [PATCH 0/4] ARM/dts: Update OMAP5 " Benoit Cousson
2012-10-22 14:11 ` Benoit Cousson
2012-10-22 15:21 ` Sebastien Guiriec
2012-10-22 15:21 ` Sebastien Guiriec
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