From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH V2 1/2] ARM: tegra: dt: add L2 cache controller
Date: Mon, 29 Oct 2012 11:23:59 -0600 [thread overview]
Message-ID: <508EBBAF.6060101@wwwdotorg.org> (raw)
In-Reply-To: <1351506345-32524-1-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 10/29/2012 04:25 AM, Joseph Lo wrote:
> Add L2 cache controller binding into DT for Tegra.
The series applied to Tegra's tree for 3.8. Thanks.
WARNING: multiple messages have this Message-ID (diff)
From: swarren@wwwdotorg.org (Stephen Warren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V2 1/2] ARM: tegra: dt: add L2 cache controller
Date: Mon, 29 Oct 2012 11:23:59 -0600 [thread overview]
Message-ID: <508EBBAF.6060101@wwwdotorg.org> (raw)
In-Reply-To: <1351506345-32524-1-git-send-email-josephl@nvidia.com>
On 10/29/2012 04:25 AM, Joseph Lo wrote:
> Add L2 cache controller binding into DT for Tegra.
The series applied to Tegra's tree for 3.8. Thanks.
next prev parent reply other threads:[~2012-10-29 17:23 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-29 10:25 [PATCH V2 1/2] ARM: tegra: dt: add L2 cache controller Joseph Lo
2012-10-29 10:25 ` Joseph Lo
[not found] ` <1351506345-32524-1-git-send-email-josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-10-29 17:23 ` Stephen Warren [this message]
2012-10-29 17:23 ` Stephen Warren
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