* [PATCH 15/20] MIPS: If KVM is enabled then use the KVM specific routine to flush the TLBs on a ASID wrap
@ 2012-10-31 15:20 Sanjay Lal
2012-11-01 12:08 ` Sergei Shtylyov
0 siblings, 1 reply; 2+ messages in thread
From: Sanjay Lal @ 2012-10-31 15:20 UTC (permalink / raw)
To: kvm, linux-mips
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
---
arch/mips/include/asm/mmu_context.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 9b02cfb..9c7024c 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -112,15 +112,21 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
static inline void
get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
{
+ extern void kvm_local_flush_tlb_all(void);
unsigned long asid = asid_cache(cpu);
if (! ((asid += ASID_INC) & ASID_MASK) ) {
if (cpu_has_vtag_icache)
flush_icache_all();
+#ifdef CONFIG_VIRTUALIZATION
+ kvm_local_flush_tlb_all(); /* start new asid cycle */
+#else
local_flush_tlb_all(); /* start new asid cycle */
+#endif
if (!asid) /* fix version if needed */
asid = ASID_FIRST_VERSION;
}
+
cpu_context(cpu, mm) = asid_cache(cpu) = asid;
}
--
1.7.11.3
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH 15/20] MIPS: If KVM is enabled then use the KVM specific routine to flush the TLBs on a ASID wrap
2012-10-31 15:20 [PATCH 15/20] MIPS: If KVM is enabled then use the KVM specific routine to flush the TLBs on a ASID wrap Sanjay Lal
@ 2012-11-01 12:08 ` Sergei Shtylyov
0 siblings, 0 replies; 2+ messages in thread
From: Sergei Shtylyov @ 2012-11-01 12:08 UTC (permalink / raw)
To: Sanjay Lal; +Cc: kvm, linux-mips
Hello.
On 31-10-2012 19:20, Sanjay Lal wrote:
> Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
> ---
> arch/mips/include/asm/mmu_context.h | 6 ++++++
> 1 file changed, 6 insertions(+)
> diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
> index 9b02cfb..9c7024c 100644
> --- a/arch/mips/include/asm/mmu_context.h
> +++ b/arch/mips/include/asm/mmu_context.h
> @@ -112,15 +112,21 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
> static inline void
> get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
> {
> + extern void kvm_local_flush_tlb_all(void);
> unsigned long asid = asid_cache(cpu);
>
> if (! ((asid += ASID_INC) & ASID_MASK) ) {
> if (cpu_has_vtag_icache)
> flush_icache_all();
> +#ifdef CONFIG_VIRTUALIZATION
> + kvm_local_flush_tlb_all(); /* start new asid cycle */
Please use tabs to indent the code, not spaces.
WBR, Sergei
^ permalink raw reply [flat|nested] 2+ messages in thread
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2012-10-31 15:20 [PATCH 15/20] MIPS: If KVM is enabled then use the KVM specific routine to flush the TLBs on a ASID wrap Sanjay Lal
2012-11-01 12:08 ` Sergei Shtylyov
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