[PATCH 14/20] MIPS: Use the UM bit instead of the CU0 enable bit in the status register to figure out the stack for saving regs.

[PATCH 14/20] MIPS: Use the UM bit instead of the CU0 enable bit in the status register to figure out the stack for saving regs.

[Sanjay Lal]

Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
---
 arch/mips/include/asm/stackframe.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index cb41af5..59c9245 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -30,7 +30,7 @@
 #define STATMASK 0x1f
 #endif
 
-#ifdef CONFIG_MIPS_MT_SMTC
+#if defined(CONFIG_MIPS_MT_SMTC) || defined (CONFIG_MIPS_HW_FIBERS)
 #include <asm/mipsmtregs.h>
 #endif /* CONFIG_MIPS_MT_SMTC */
 
@@ -162,9 +162,9 @@
 		.set	noat
 		.set	reorder
 		mfc0	k0, CP0_STATUS
-		sll	k0, 3		/* extract cu0 bit */
+		andi    k0,k0,0x10 		/* check user mode bit*/
 		.set	noreorder
-		bltz	k0, 8f
+         beq     k0, $0, 8f
 		 move	k1, sp
 		.set	reorder
 		/* Called from user mode, new stack. */
-- 
1.7.11.3

Re: [PATCH 14/20] MIPS: Use the UM bit instead of the CU0 enable bit in the status register to figure out the stack for saving regs.

[Sergei Shtylyov]

Hello.

On 31-10-2012 19:20, Sanjay Lal wrote:

> Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
> ---
>   arch/mips/include/asm/stackframe.h | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)

> diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
> index cb41af5..59c9245 100644
> --- a/arch/mips/include/asm/stackframe.h
> +++ b/arch/mips/include/asm/stackframe.h
[...]
> @@ -162,9 +162,9 @@
>   		.set	noat
>   		.set	reorder
>   		mfc0	k0, CP0_STATUS
> -		sll	k0, 3		/* extract cu0 bit */
> +		andi    k0,k0,0x10 		/* check user mode bit*/
>   		.set	noreorder
> -		bltz	k0, 8f
> +         beq     k0, $0, 8f

    Use tabs, not spaces to indent the code, same as above.

WBR, Sergei

Re: [PATCH 14/20] MIPS: Use the UM bit instead of the CU0 enable bit in the status register to figure out the stack for saving regs.

[Sergei Shtylyov]

On 31-10-2012 19:20, Sanjay Lal wrote:

> Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
> ---
>   arch/mips/include/asm/stackframe.h | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)

> diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
> index cb41af5..59c9245 100644
> --- a/arch/mips/include/asm/stackframe.h
> +++ b/arch/mips/include/asm/stackframe.h
> @@ -30,7 +30,7 @@
>   #define STATMASK 0x1f
>   #endif
>
> -#ifdef CONFIG_MIPS_MT_SMTC
> +#if defined(CONFIG_MIPS_MT_SMTC) || defined (CONFIG_MIPS_HW_FIBERS)

    Does this change have anything to do with the patch subject?

WBR, Sergei

Re: [PATCH 14/20] MIPS: Use the UM bit instead of the CU0 enable bit in the status register to figure out the stack for saving regs.

[Maciej W. Rozycki]

On Wed, 31 Oct 2012, Sanjay Lal wrote:

> diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
> index cb41af5..59c9245 100644
> --- a/arch/mips/include/asm/stackframe.h
> +++ b/arch/mips/include/asm/stackframe.h
> @@ -30,7 +30,7 @@
>  #define STATMASK 0x1f
>  #endif
>  
> -#ifdef CONFIG_MIPS_MT_SMTC
> +#if defined(CONFIG_MIPS_MT_SMTC) || defined (CONFIG_MIPS_HW_FIBERS)
>  #include <asm/mipsmtregs.h>
>  #endif /* CONFIG_MIPS_MT_SMTC */
>  
> @@ -162,9 +162,9 @@
>  		.set	noat
>  		.set	reorder
>  		mfc0	k0, CP0_STATUS
> -		sll	k0, 3		/* extract cu0 bit */
> +		andi    k0,k0,0x10 		/* check user mode bit*/
>  		.set	noreorder
> -		bltz	k0, 8f
> +         beq     k0, $0, 8f
>  		 move	k1, sp
>  		.set	reorder
>  		/* Called from user mode, new stack. */

 Any reason this is needed for?  If so, then given that this is generic 
code a corresponding piece has to be added to support the MIPS I ISA 
processors that have the user mode bit in a different location.  
Presumably you'll update all the other places that fiddle with 
CP0.Status.CU0 too?

  Maciej