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From: gregory.clement@free-electrons.com (Gregory CLEMENT)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V2 1/5] arm: mvebu: Added support for coherency fabric in mach-mvebu
Date: Fri, 16 Nov 2012 20:25:53 +0100	[thread overview]
Message-ID: <50A69341.2090202@free-electrons.com> (raw)
In-Reply-To: <20121116185610.GA1019@mudshark.cambridge.arm.com>

On 11/16/2012 07:56 PM, Will Deacon wrote:
> On Thu, Nov 15, 2012 at 04:49:17PM +0000, Gregory CLEMENT wrote:
>> On 11/15/2012 05:21 PM, Will Deacon wrote:
>>> Anyway, that's by-the-by as this is all called early enough that we
>>> shouldn't care. The thing I don't like now is that the fabric initialisation
>>> is done entirely differently on the primary CPU than the secondaries. The
>>> primary probes the device-tree (well, it's also now hard-coded for v2) and
>>> accesses the registers from a C function(armada_370_xp_set_cpu_coherent) whilst
>>> the secondaries have hardcoded addresses and access via asm
>>> (armada_xp_secondary_startup).
>>
>>
>> Now it is hardcoded in both case as you pointed it. So the last
>> difference is setup from a C function or via asm.
>>
>> The differences between primary and secondary CPU when they enable the
>> coherency, is due to the fact that we really are in a different
>> situation. For primary CPU, as it is the only CPU online it doesn't
>> need to enable the coherency from the beginning, so we can wait to
>> have MMU enable and convenient feature. Whereas for the secondary CPU
>> they need the coherency from the very beginning are by definition they
>> won't be alone. That's why this very first instruction are written in
>> asm and they use physical address.
>>
>> I don't see how to handle it in a different way.
> 
> The code paths are fine, I would just like to see less duplication. Can you
> make the asm function PCS compliant and call it from C for the primary
> (setting the link register to secondary_startup for the secondary cores)?

Have you a pointer on how to do it (make the asm function PCS compliant)?

I will also need to add a parameter, because the base address are not the
same between primary CPU and secondary CPUS. With the first we use virtual
address whereas with the second the physical address.


> 
> Will
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

WARNING: multiple messages have this Message-ID (diff)
From: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
Cc: Lior Amsalem <alior-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
	Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>,
	Ike Pan <ike.pan-Z7WLFzj8eWMS+FvcfC7Uqw@public.gmane.org>,
	Nadav Haklai <nadavh-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
	Ian Molton <ian.molton-4yDnlxn2s6sWdaTGBSpHTA@public.gmane.org>,
	David Marlin <dmarlin-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
	Yehuda Yitschak <yehuday-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
	Jani Monoses
	<jani.monoses-Z7WLFzj8eWMS+FvcfC7Uqw@public.gmane.org>,
	Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
	Tawfik Bayouk <tawfik-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
	Dan Frazier
	<dann.frazier-Z7WLFzj8eWMS+FvcfC7Uqw@public.gmane.org>,
	Eran Ben-Avi <benavi-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
	Leif Lindholm <Leif.Lindholm-5wv7dgnIgG8@public.gmane.org>,
	Sebastian Hesselbarth
	<sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>,
	"jcm-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org"
	<jcm-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
	"devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org"
	<devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org>,
	"rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org"
	<rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>,
	Ben Dooks <ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org>,
	Mike Turquette
	<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWOunwaRDDq4rA@public.gmane.org>
Subject: Re: [PATCH V2 1/5] arm: mvebu: Added support for coherency fabric in mach-mvebu
Date: Fri, 16 Nov 2012 20:25:53 +0100	[thread overview]
Message-ID: <50A69341.2090202@free-electrons.com> (raw)
In-Reply-To: <20121116185610.GA1019-MRww78TxoiP5vMa5CHWGZ34zcgK1vI+I0E9HWUfgJXw@public.gmane.org>

On 11/16/2012 07:56 PM, Will Deacon wrote:
> On Thu, Nov 15, 2012 at 04:49:17PM +0000, Gregory CLEMENT wrote:
>> On 11/15/2012 05:21 PM, Will Deacon wrote:
>>> Anyway, that's by-the-by as this is all called early enough that we
>>> shouldn't care. The thing I don't like now is that the fabric initialisation
>>> is done entirely differently on the primary CPU than the secondaries. The
>>> primary probes the device-tree (well, it's also now hard-coded for v2) and
>>> accesses the registers from a C function(armada_370_xp_set_cpu_coherent) whilst
>>> the secondaries have hardcoded addresses and access via asm
>>> (armada_xp_secondary_startup).
>>
>>
>> Now it is hardcoded in both case as you pointed it. So the last
>> difference is setup from a C function or via asm.
>>
>> The differences between primary and secondary CPU when they enable the
>> coherency, is due to the fact that we really are in a different
>> situation. For primary CPU, as it is the only CPU online it doesn't
>> need to enable the coherency from the beginning, so we can wait to
>> have MMU enable and convenient feature. Whereas for the secondary CPU
>> they need the coherency from the very beginning are by definition they
>> won't be alone. That's why this very first instruction are written in
>> asm and they use physical address.
>>
>> I don't see how to handle it in a different way.
> 
> The code paths are fine, I would just like to see less duplication. Can you
> make the asm function PCS compliant and call it from C for the primary
> (setting the link register to secondary_startup for the secondary cores)?

Have you a pointer on how to do it (make the asm function PCS compliant)?

I will also need to add a parameter, because the base address are not the
same between primary CPU and secondary CPUS. With the first we use virtual
address whereas with the second the physical address.


> 
> Will
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

  reply	other threads:[~2012-11-16 19:25 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-29 21:11 [PATCH V2 0/5] SMP support for Armada XP Gregory CLEMENT
2012-10-29 21:11 ` Gregory CLEMENT
2012-10-29 21:11 ` [PATCH V2 1/5] arm: mvebu: Added support for coherency fabric in mach-mvebu Gregory CLEMENT
2012-10-29 21:11   ` Gregory CLEMENT
2012-11-05 14:02   ` Will Deacon
2012-11-05 14:02     ` Will Deacon
2012-11-05 23:53     ` Gregory CLEMENT
2012-11-05 23:53       ` Gregory CLEMENT
2012-11-12 20:21     ` Gregory CLEMENT
2012-11-12 20:21       ` Gregory CLEMENT
2012-11-13 10:43       ` Will Deacon
2012-11-13 10:43         ` Will Deacon
2012-11-14 20:00         ` Gregory CLEMENT
2012-11-14 20:00           ` Gregory CLEMENT
2012-11-15 10:17           ` Will Deacon
2012-11-15 10:17             ` Will Deacon
2012-11-15 15:54             ` Gregory CLEMENT
2012-11-15 15:54               ` Gregory CLEMENT
2012-11-15 16:21               ` Will Deacon
2012-11-15 16:21                 ` Will Deacon
2012-11-15 16:49                 ` Gregory CLEMENT
2012-11-15 16:49                   ` Gregory CLEMENT
2012-11-16 18:56                   ` Will Deacon
2012-11-16 18:56                     ` Will Deacon
2012-11-16 19:25                     ` Gregory CLEMENT [this message]
2012-11-16 19:25                       ` Gregory CLEMENT
2012-11-19 10:32                       ` Will Deacon
2012-11-19 10:32                         ` Will Deacon
2012-10-29 21:11 ` [PATCH V2 2/5] arm: mvebu: Added initial support for power managmement service unit Gregory CLEMENT
2012-10-29 21:11   ` Gregory CLEMENT
2012-11-05 14:05   ` Will Deacon
2012-11-05 14:05     ` Will Deacon
2012-11-14  0:07     ` Russell King - ARM Linux
2012-11-14  0:07       ` Russell King - ARM Linux
2012-11-14  9:46       ` Will Deacon
2012-11-14  9:46         ` Will Deacon
2012-10-29 21:11 ` [PATCH V2 3/5] arm: mvebu: Added IPI support via doorbells Gregory CLEMENT
2012-10-29 21:11   ` Gregory CLEMENT
2012-10-29 21:11 ` [PATCH V2 4/5] arm: mm: Added support for PJ4B cpu and init routines Gregory CLEMENT
2012-10-29 21:11   ` Gregory CLEMENT
2012-11-13 15:15   ` Gregory CLEMENT
2012-11-13 15:15     ` Gregory CLEMENT
2012-11-13 22:53     ` Will Deacon
2012-11-13 22:53       ` Will Deacon
2012-11-14  0:14   ` Russell King - ARM Linux
2012-11-14  0:14     ` Russell King - ARM Linux
2012-10-29 21:11 ` [PATCH V2 5/5] arm: mvebu: Added SMP support for Armada XP Gregory CLEMENT
2012-10-29 21:11   ` Gregory CLEMENT
2012-11-12 20:49 ` [PATCH V2 0/5] " Gregory CLEMENT
2012-11-12 20:49   ` Gregory CLEMENT
2012-11-12 22:32   ` Arnd Bergmann
2012-11-12 22:32     ` Arnd Bergmann

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