Re: [Qemu-devel] [PATCH for 1.3] target-i386: enable SSSE3 TCG support

["Andreas Färber" <afaerber@suse.de>]

Am 24.11.2012 15:07, schrieb Aurelien Jarno:
> SSSE3 support has been added to TCG more than 4 years ago in commit
> 4242b1bd8acc19aaaacffdaad4ac23213d72a72b. It has been disabled by
> mistake in commit 551a2dec8fa55006a68393b9d6fb63577d2b3f1c.
> 
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Reviewed-by: Andreas Färber <afaerber@suse.de>

Looks okay for 1.3 to me. CC'ing some more people who work on the CPU,
so that the bit does not get lost again during our refactorings.

Aurélien: I have one more patch for x86 CPU in my queue for 1.3
(Haswell), would you be willing to apply both once acked, or should I
queue yours for a combined PULL?

Andreas

> ---
>  target-i386/cpu.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> SSE4.1 and SSE4.2 are wrongly disabled too, but some instructions from
> SSE4.2 (I haven't investigated more yet) are wrongly emulated, which
> causes some crashes now that GLIBC is using them through gnu indirect
> functions.
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 64c3491..68f6f5d 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -315,7 +315,7 @@ typedef struct x86_def_t {
>            /* missing:
>            CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
>  #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
> -          CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
> +          CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
>            CPUID_EXT_HYPERVISOR)
>            /* missing:
>            CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,

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