* [U-Boot] [PATCH 0/4] Add support for SAMSUNG Exynos4 SoCs and ORIGEN_QUAD board
@ 2012-12-12 7:54 Jeong Hyeon Kim
2012-12-12 7:54 ` [U-Boot] [PATCH 1/4] EXYNOS4: Add pinmux support for UART Jeong Hyeon Kim
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Jeong Hyeon Kim @ 2012-12-12 7:54 UTC (permalink / raw)
To: u-boot
This patch series adds support for Exynos4 SoCs and ORIGEN_QUAD board.
Exynos4212/4412 are SAMSUNG's ARM Cortex-A15 boased SoCs and Exynos4 series SoCs.
ORIGEN_QUAD board is based on Exynos4212.
[PATCH 1/4] EXYNOS4: Add pinmux support for UART
[PATCH 2/4] EXYNOS4: Add pinmux support for I2C
[PATCH 3/4] EXYNOS4: Add support for Exynos4x12 SoCs
[PATCH 4/4] EXYNOS4: Add ORIGEN_QUAD board support
Makefile | 2 +-
arch/arm/cpu/armv7/exynos/clock.c | 7 +-
arch/arm/cpu/armv7/exynos/pinmux.c | 92 +++++++++
arch/arm/include/asm/arch-exynos/clock.h | 240 +++++++++++++++++++++++
arch/arm/include/asm/arch-exynos/cpu.h | 1 +
board/samsung/origen_quad/Makefile | 59 ++++++
board/samsung/origen_quad/boot.c | 72 +++++++
board/samsung/origen_quad/clock.c | 103 ++++++++++
board/samsung/origen_quad/dmc.c | 163 ++++++++++++++++
board/samsung/origen_quad/lowlevel_init.S | 151 +++++++++++++++
board/samsung/origen_quad/origen_quad.c | 163 ++++++++++++++++
board/samsung/origen_quad/setup.h | 300 +++++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/origen_quad.h | 179 +++++++++++++++++
tools/Makefile | 2 +
15 files changed, 1533 insertions(+), 2 deletions(-)
create mode 100644 board/samsung/origen_quad/Makefile
create mode 100644 board/samsung/origen_quad/boot.c
create mode 100644 board/samsung/origen_quad/clock.c
create mode 100644 board/samsung/origen_quad/dmc.c
create mode 100644 board/samsung/origen_quad/lowlevel_init.S
create mode 100644 board/samsung/origen_quad/origen_quad.c
create mode 100644 board/samsung/origen_quad/setup.h
create mode 100644 include/configs/origen_quad.h
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 1/4] EXYNOS4: Add pinmux support for UART
2012-12-12 7:54 [U-Boot] [PATCH 0/4] Add support for SAMSUNG Exynos4 SoCs and ORIGEN_QUAD board Jeong Hyeon Kim
@ 2012-12-12 7:54 ` Jeong Hyeon Kim
2012-12-12 7:54 ` [U-Boot] [PATCH 2/4] EXYNOS4: Add pinmux support for I2C Jeong Hyeon Kim
` (2 subsequent siblings)
3 siblings, 0 replies; 11+ messages in thread
From: Jeong Hyeon Kim @ 2012-12-12 7:54 UTC (permalink / raw)
To: u-boot
From: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
This patch adds pinmux support for UART channels
Signed-off-by: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
---
arch/arm/cpu/armv7/exynos/pinmux.c | 41 ++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index f02f441..364ee2a 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -366,6 +366,41 @@ static int exynos4_mmc_config(int peripheral, int flags)
return 0;
}
+static void exynos4_uart_config(int peripheral)
+{
+ struct exynos4_gpio_part1 *gpio1 =
+ (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
+ struct s5p_gpio_bank *bank;
+ int i, start, count;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ bank = &gpio1->a0;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART1:
+ bank = &gpio1->a0;
+ start = 4;
+ count = 4;
+ break;
+ case PERIPH_ID_UART2:
+ bank = &gpio1->a1;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART3:
+ bank = &gpio1->a1;
+ start = 4;
+ count = 2;
+ break;
+ }
+ for (i = start; i < start + count; i++) {
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ }
+}
+
static int exynos4_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
@@ -377,6 +412,12 @@ static int exynos4_pinmux_config(int peripheral, int flags)
case PERIPH_ID_SDMMC4:
printf("SDMMC device %d not implemented\n", peripheral);
return -1;
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ exynos4_uart_config(peripheral);
+ break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 2/4] EXYNOS4: Add pinmux support for I2C
2012-12-12 7:54 [U-Boot] [PATCH 0/4] Add support for SAMSUNG Exynos4 SoCs and ORIGEN_QUAD board Jeong Hyeon Kim
2012-12-12 7:54 ` [U-Boot] [PATCH 1/4] EXYNOS4: Add pinmux support for UART Jeong Hyeon Kim
@ 2012-12-12 7:54 ` Jeong Hyeon Kim
2012-12-12 8:16 ` Heiko Schocher
2012-12-12 7:54 ` [U-Boot] [PATCH 3/4] EXYNOS4: Add support for Exynos4x12 SoCs Jeong Hyeon Kim
2012-12-12 7:54 ` [U-Boot] [PATCH 4/4] EXYNOS4: Add ORIGEN_QUAD board support Jeong Hyeon Kim
3 siblings, 1 reply; 11+ messages in thread
From: Jeong Hyeon Kim @ 2012-12-12 7:54 UTC (permalink / raw)
To: u-boot
From: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
This patch adds pinmux support for I2C channels
Signed-off-by: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
---
arch/arm/cpu/armv7/exynos/pinmux.c | 51 ++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 364ee2a..d778b46 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -401,6 +401,48 @@ static void exynos4_uart_config(int peripheral)
}
}
+static void exynos4_i2c_config(int peripheral, int flags)
+{
+
+ struct exynos4_gpio_part1 *gpio1 =
+ (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ s5p_gpio_cfg_pin(&gpio1->b, 0, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 1, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+ break;
+ }
+}
+
static int exynos4_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
@@ -417,6 +459,15 @@ static int exynos4_pinmux_config(int peripheral, int flags)
case PERIPH_ID_UART2:
case PERIPH_ID_UART3:
exynos4_uart_config(peripheral);
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ exynos4_i2c_config(peripheral, flags);
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 3/4] EXYNOS4: Add support for Exynos4x12 SoCs
2012-12-12 7:54 [U-Boot] [PATCH 0/4] Add support for SAMSUNG Exynos4 SoCs and ORIGEN_QUAD board Jeong Hyeon Kim
2012-12-12 7:54 ` [U-Boot] [PATCH 1/4] EXYNOS4: Add pinmux support for UART Jeong Hyeon Kim
2012-12-12 7:54 ` [U-Boot] [PATCH 2/4] EXYNOS4: Add pinmux support for I2C Jeong Hyeon Kim
@ 2012-12-12 7:54 ` Jeong Hyeon Kim
2012-12-13 6:19 ` Chander Kashyap
2012-12-12 7:54 ` [U-Boot] [PATCH 4/4] EXYNOS4: Add ORIGEN_QUAD board support Jeong Hyeon Kim
3 siblings, 1 reply; 11+ messages in thread
From: Jeong Hyeon Kim @ 2012-12-12 7:54 UTC (permalink / raw)
To: u-boot
From: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
This patch adds the support for Exynos4212/4412.
Samsung's ARM Cortex-A9 based Exynos4x12 SoCs and Exynos4210 are similar.
Address of a few registers are different in CMU part like MPLL.
Signed-off-by: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
---
arch/arm/cpu/armv7/exynos/clock.c | 7 +-
arch/arm/include/asm/arch-exynos/clock.h | 240 ++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-exynos/cpu.h | 1 +
3 files changed, 247 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index fe61f88..47e2e6c 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -94,7 +94,12 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
r = readl(&clk->apll_con0);
break;
case MPLL:
- r = readl(&clk->mpll_con0);
+ if (proid_is_exynos4412()) {
+ struct exynos4412_clock *clk4412 =
+ (struct exynos4412_clock *)samsung_get_base_clock();
+ r = readl(&clk4412->mpll_con0);
+ } else
+ r = readl(&clk->mpll_con0);
break;
case EPLL:
r = readl(&clk->epll_con0);
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index ff6781a..5d4ed5c 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -251,6 +251,246 @@ struct exynos4_clock {
unsigned int div_iem_l1;
};
+struct exynos4412_clock {
+ unsigned char res1[0x4200];
+ unsigned int src_leftbus;
+ unsigned char res2[0x1fc];
+ unsigned int mux_stat_leftbus;
+ unsigned char res3[0xfc];
+ unsigned int div_leftbus;
+ unsigned char res4[0xfc];
+ unsigned int div_stat_leftbus;
+ unsigned char res5[0x1fc];
+ unsigned int gate_ip_leftbus;
+ unsigned char res6[0x12c];
+ unsigned int gate_ip_image;
+ unsigned char res7[0xcc];
+ unsigned int clkout_cmu_leftbus;
+ unsigned int clkout_cmu_leftbus_div_stat;
+ unsigned char res8[0x37f8];
+ unsigned int src_rightbus;
+ unsigned char res9[0x1fc];
+ unsigned int mux_stat_rightbus;
+ unsigned char res10[0xfc];
+ unsigned int div_rightbus;
+ unsigned char res11[0xfc];
+ unsigned int div_stat_rightbus;
+ unsigned char res12[0x1fc];
+ unsigned int gate_ip_rightbus;
+ unsigned char res13[0x15c];
+ unsigned int gate_ip_perir;
+ unsigned char res14[0x9c];
+ unsigned int clkout_cmu_rightbus;
+ unsigned int clkout_cmu_rightbus_div_stat;
+ unsigned char res15[0x3608];
+ unsigned int epll_lock;
+ unsigned char res16[0xc];
+ unsigned int vpll_lock;
+ unsigned char res17[0xec];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int epll_con2;
+ unsigned char res18[0x4];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned int vpll_con2;
+ unsigned char res19[0xe4];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned char res20[0x8];
+ unsigned int src_cam0;
+ unsigned int src_tv;
+ unsigned int src_mfc;
+ unsigned int src_g3d;
+ unsigned char res21[0x4];
+ unsigned int src_lcd0;
+ unsigned int src_isp;
+ unsigned int src_maudio;
+ unsigned int src_fsys;
+ unsigned char res22[0xc];
+ unsigned int src_peril0;
+ unsigned int src_peril1;
+ unsigned int src_cam1;
+ unsigned char res23[0xc4];
+ unsigned int src_mask_cam0;
+ unsigned int src_mask_tv;
+ unsigned char res24[0xc];
+ unsigned int src_mask_lcd;
+ unsigned int src_mask_isp;
+ unsigned int src_mask_maudio;
+ unsigned int src_mask_fsys;
+ unsigned char res25[0xc];
+ unsigned int src_mask_peril0;
+ unsigned int src_mask_peril1;
+ unsigned char res26[0xb8];
+ unsigned int mux_stat_top;
+ unsigned int mux_stat_top1;
+ unsigned char res27[0x10];
+ unsigned int mux_stat_mfc;
+ unsigned int mux_stat_g3d;
+ unsigned char res28[0x28];
+ unsigned int mux_stat_cam1;
+ unsigned char res29[0xb4];
+ unsigned int div_top;
+ unsigned char res30[0xc];
+ unsigned int div_cam0;
+ unsigned int div_tv;
+ unsigned int div_mfc;
+ unsigned int div_g3d;
+ unsigned char res31[0x4];
+ unsigned int div_lcd;
+ unsigned int div_isp;
+ unsigned int div_maudio;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned int div_fsys3;
+ unsigned int div_peril0;
+ unsigned int div_peril1;
+ unsigned int div_peril2;
+ unsigned int div_peril3;
+ unsigned int div_peril4;
+ unsigned int div_peril5;
+ unsigned int div_cam1;
+ unsigned char res32[0x14];
+ unsigned int div2_ratio;
+ unsigned char res33[0x8c];
+ unsigned int div_stat_top;
+ unsigned char res34[0xc];
+ unsigned int div_stat_cam0;
+ unsigned int div_stat_tv;
+ unsigned int div_stat_mfc;
+ unsigned int div_stat_g3d;
+ unsigned char res35[0x4];
+ unsigned int div_stat_lcd;
+ unsigned int div_stat_isp;
+ unsigned int div_stat_maudio;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned int div_stat_fsys3;
+ unsigned int div_stat_peril0;
+ unsigned int div_stat_peril1;
+ unsigned int div_stat_peril2;
+ unsigned int div_stat_peril3;
+ unsigned int div_stat_peril4;
+ unsigned int div_stat_peril5;
+ unsigned int div_stat_cam1;
+ unsigned char res36[0x14];
+ unsigned int div2_stat;
+ unsigned char res37[0xc0];
+ unsigned int gate_bus_fsys1;
+ unsigned char res38[0x1d8];
+ unsigned int gate_ip_cam;
+ unsigned int gate_ip_tv;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned char res39[0x4];
+ unsigned int gate_ip_lcd;
+ unsigned int gate_ip_isp;
+ unsigned char res40[0x4];
+ unsigned int gate_ip_fsys;
+ unsigned char res41[0x8];
+ unsigned int gate_ip_gps;
+ unsigned int gate_ip_peril;
+ unsigned char res42[0x1c];
+ unsigned int gate_block;
+ unsigned char res43[0x8c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res44[0x3600];
+ unsigned int mpll_lock;
+ unsigned char res45[0xfc];
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res46[0xf0];
+ unsigned int src_dmc;
+ unsigned char res47[0xfc];
+ unsigned int src_mask_dmc;
+ unsigned char res48[0xfc];
+ unsigned int mux_stat_dmc;
+ unsigned char res49[0xfc];
+ unsigned int div_dmc0;
+ unsigned int div_dmc1;
+ unsigned char res50[0xf8];
+ unsigned int div_stat_dmc0;
+ unsigned int div_stat_dmc1;
+ unsigned char res51[0x2f8];
+ unsigned int gate_ip_dmc;
+ unsigned int gate_ip_dmc1;
+ unsigned char res52[0xf8];
+ unsigned int clkout_cmu_dmc;
+ unsigned int clkout_cmu_dmc_div_stat;
+ unsigned char res53[0x5f8];
+ unsigned int dcgidx_map0;
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res54[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res55[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res56[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res57[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res58[0xc];
+ unsigned int dmc_puause_ctrl;
+ unsigned int ddrphy_lock_ctrl;
+ unsigned int c2c_state;
+ unsigned char res59[0x2f60];
+ unsigned int apll_lock;
+ unsigned char res60[0xfc];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned char res61[0xf8];
+ unsigned int src_cpu;
+ unsigned char res62[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res63[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res64[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res65[0x2f8];
+ unsigned int gate_ip_cpu;
+ unsigned char res66[0xfc];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res67[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned int atclk_stopctrl;
+ unsigned char res68[0x18];
+ unsigned int pwr_ctrl;
+ unsigned int pwr_ctrl2;
+ unsigned char res69[0x3d8];
+ unsigned int l2_status;
+ unsigned char res70[0xc];
+ unsigned int cpu_status;
+ unsigned char res71[0xc];
+ unsigned int ptm_status;
+ unsigned char res72[0x2edc];
+ unsigned int clk_div_isp0;
+ unsigned int clk_div_isp1;
+ unsigned char res73[0xf8];
+ unsigned int clk_div_stat_isp0;
+ unsigned int clk_div_stat_isp1;
+ unsigned char res74[0x3f8];
+ unsigned int gate_ip_isp0;
+ unsigned int gate_ip_isp1;
+ unsigned char res75[0x1f8];
+ unsigned int clkout_cmu_isp;
+ unsigned int clkout_cmu_isp_stat;
+ unsigned char res76[0xf8];
+ unsigned int clkout_cmu_spare0;
+ unsigned int clkout_cmu_spare1;
+ unsigned int clkout_cmu_spare2;
+ unsigned int clkout_cmu_spare3;
+};
+
struct exynos5_clock {
unsigned int apll_lock;
unsigned char res1[0xfc];
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index d1b2ea8..7ee5366 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -152,6 +152,7 @@ static inline int proid_is_##type(void) \
}
IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
#define SAMSUNG_BASE(device, base) \
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 4/4] EXYNOS4: Add ORIGEN_QUAD board support
2012-12-12 7:54 [U-Boot] [PATCH 0/4] Add support for SAMSUNG Exynos4 SoCs and ORIGEN_QUAD board Jeong Hyeon Kim
` (2 preceding siblings ...)
2012-12-12 7:54 ` [U-Boot] [PATCH 3/4] EXYNOS4: Add support for Exynos4x12 SoCs Jeong Hyeon Kim
@ 2012-12-12 7:54 ` Jeong Hyeon Kim
3 siblings, 0 replies; 11+ messages in thread
From: Jeong Hyeon Kim @ 2012-12-12 7:54 UTC (permalink / raw)
To: u-boot
From: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
ORIGEN_QUAD board is based on Samsung's Exynos4412 SoC.
Signed-off-by: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
---
Makefile | 2 +-
board/samsung/origen_quad/Makefile | 59 ++++++
board/samsung/origen_quad/boot.c | 72 +++++++
board/samsung/origen_quad/clock.c | 103 ++++++++++
board/samsung/origen_quad/dmc.c | 163 ++++++++++++++++
board/samsung/origen_quad/lowlevel_init.S | 151 +++++++++++++++
board/samsung/origen_quad/origen_quad.c | 163 ++++++++++++++++
board/samsung/origen_quad/setup.h | 300 +++++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/origen_quad.h | 179 +++++++++++++++++
tools/Makefile | 2 +
11 files changed, 1194 insertions(+), 1 deletion(-)
create mode 100644 board/samsung/origen_quad/Makefile
create mode 100644 board/samsung/origen_quad/boot.c
create mode 100644 board/samsung/origen_quad/clock.c
create mode 100644 board/samsung/origen_quad/dmc.c
create mode 100644 board/samsung/origen_quad/lowlevel_init.S
create mode 100644 board/samsung/origen_quad/origen_quad.c
create mode 100644 board/samsung/origen_quad/setup.h
create mode 100644 include/configs/origen_quad.h
diff --git a/Makefile b/Makefile
index 44db889..c69f740 100644
--- a/Makefile
+++ b/Makefile
@@ -823,7 +823,7 @@ clean:
$(obj)tools/gdb/{astest,gdbcont,gdbsend} \
$(obj)tools/gen_eth_addr $(obj)tools/img2srec \
$(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
- $(obj)tools/mk{smdk5250,}spl \
+ $(obj)tools/mk{$(SOC),$(BOARD),}spl \
$(obj)tools/mxsboot \
$(obj)tools/ncb $(obj)tools/ubsha1 \
$(obj)tools/kernel-doc/docproc
diff --git a/board/samsung/origen_quad/Makefile b/board/samsung/origen_quad/Makefile
new file mode 100644
index 0000000..c24c921
--- /dev/null
+++ b/board/samsung/origen_quad/Makefile
@@ -0,0 +1,59 @@
+#
+# Copyright (C) 2012 Samsung Electronics
+#
+# Copyright (C) 2012 Insignal
+#
+# Makefile for the Insignal OrigenQUAD board (Exynos4x12)
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+SOBJS := lowlevel_init.o
+
+COBJS := clock.o
+COBJS += dmc.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS += origen_quad.o
+else
+COBJS += boot.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+ALL := $(obj).depend $(LIB)
+
+all: $(ALL)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/board/samsung/origen_quad/boot.c b/board/samsung/origen_quad/boot.c
new file mode 100644
index 0000000..53bbe83
--- /dev/null
+++ b/board/samsung/origen_quad/boot.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Board initialize for the Insignal OrigenQUAD board (Exynos4x12)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include "setup.h"
+
+#define IRAM_ADDRESS 0x02020000
+#define EXTERNAL_FUNC_ADDRESS (IRAM_ADDRESS + 0x0030)
+#define IROM_COPY_FROM_SDMMC (EXTERNAL_FUNC_ADDRESS + 0x0)
+
+typedef u32 (*copy_from_sdmmc_t)(u32 offset, u32 nblock, u32 dest);
+
+void copy_uboot_to_mem(void)
+{
+ copy_from_sdmmc_t from_sdmmc;
+
+ from_sdmmc = *(copy_from_sdmmc_t *)IROM_COPY_FROM_SDMMC;
+ from_sdmmc(BL2_BLK_OFFSET, BL2_BLK_COUNT, CONFIG_SYS_TEXT_BASE);
+}
+
+void board_init_spl(void)
+{
+ /* PS-Hold high */
+ writel(0x5300, EXYNOS4_POWER_BASE + 0x330c);
+}
+
+void board_init_f(unsigned long bootflag)
+{
+ __attribute__((noreturn)) void (*uboot)(void);
+
+ board_init_spl();
+ copy_uboot_to_mem();
+
+ /* Jump to U-Boot image */
+ uboot = (void *)CONFIG_SYS_TEXT_BASE;
+ (*uboot)();
+ /* Never returns Here */
+}
+
+/* Place Holders */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+ /* Function attribute is no-return */
+ /* This Function never executes */
+ while (1);
+}
+
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/board/samsung/origen_quad/clock.c b/board/samsung/origen_quad/clock.c
new file mode 100644
index 0000000..3ed503c
--- /dev/null
+++ b/board/samsung/origen_quad/clock.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Clock setup for the Insignal OrigenQUAD board (Exynos4x12)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include "setup.h"
+
+void clock_ctrl_init(void)
+{
+ struct exynos4412_clock *clk =
+ (struct exynos4412_clock *)EXYNOS4_CLOCK_BASE;
+
+ /* CLK_SRC_CPU */
+ writel(0x00000000, &clk->src_cpu);
+ sdelay(0x10000);
+
+ /* CLK_DIV_DMC */
+ writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
+ writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
+
+ /* CLK_SRC_TOP */
+ writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+ writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+ sdelay(0x10000);
+ writel(CLK_DIV_TOP_VAL, &clk->div_top);
+
+ /* LEFTBUS */
+ writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
+ sdelay(0x10000);
+ writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
+ /* RIGHTBUS */
+ writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
+ sdelay(0x10000);
+ writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
+
+ /* PLL locktime */
+ writel(APLL_LOCK_VAL, &clk->apll_lock);
+ writel(MPLL_LOCK_VAL, &clk->mpll_lock);
+ writel(EPLL_LOCK_VAL, &clk->epll_lock);
+ writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+
+ /* CLK_DIV_CPU0/1 */
+ writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+ writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+
+ /* APLL */
+ writel(APLL_CON1_VAL, &clk->apll_con1);
+ writel(APLL_CON0_VAL, &clk->apll_con0);
+ /* MPLL */
+ writel(MPLL_CON1_VAL, &clk->mpll_con1);
+ writel(MPLL_CON0_VAL, &clk->mpll_con0);
+ /* EPLL */
+ writel(EPLL_CON2_VAL, &clk->epll_con2);
+ writel(EPLL_CON1_VAL, &clk->epll_con1);
+ writel(EPLL_CON0_VAL, &clk->epll_con0);
+ /* VPLL */
+ writel(VPLL_CON2_VAL, &clk->vpll_con2);
+ writel(VPLL_CON1_VAL, &clk->vpll_con1);
+ writel(VPLL_CON0_VAL, &clk->vpll_con0);
+ sdelay(0x40000);
+
+ writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
+ writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
+ writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+ writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+ sdelay(0x10000);
+
+ /* UART */
+ writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
+ writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
+
+ /* for IROM */
+ /* CLK_DIV_FSYS2 */
+ writel(0x0000000F, &clk->div_fsys2); /* MMC2 - SDMMC */
+ /* CLK_DIV_FSYS3 */
+ writel(0x00000100, &clk->div_fsys3); /* MMC4 - eMMC */
+}
+
diff --git a/board/samsung/origen_quad/dmc.c b/board/samsung/origen_quad/dmc.c
new file mode 100644
index 0000000..0bb1164
--- /dev/null
+++ b/board/samsung/origen_quad/dmc.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Memory setup for the Insignal OrigenQUAD board (Exynos4x12)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include "setup.h"
+
+void mem_ctrl_init(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)EXYNOS4_CLOCK_BASE;
+ struct exynos4_dmc *dmc0 =
+ (struct exynos4_dmc *)(EXYNOS4_MIU_BASE);
+ struct exynos4_dmc *dmc1 =
+ (struct exynos4_dmc *)(EXYNOS4_MIU_BASE + 0x10000);
+
+ /* Set DMC to 50MHz for IROM */
+ writel(0x00117713, &clk->div_dmc0);
+
+ /*
+ * DMC 0
+ */
+ writel(0xE3855403, &dmc0->phyzqcontrol);
+ writel(0x71101008, &dmc0->phycontrol0);
+ writel(0x7110100A, &dmc0->phycontrol0);
+ writel(0x00000084, &dmc0->phycontrol1);
+ writel(0x71101008, &dmc0->phycontrol0);
+ writel(0x0000008C, &dmc0->phycontrol1);
+ writel(0x00000084, &dmc0->phycontrol1);
+ writel(0x0000008C, &dmc0->phycontrol1);
+ writel(0x00000084, &dmc0->phycontrol1);
+ writel(0x0FFF30CA, &dmc0->concontrol);
+ writel(0x00202500, &dmc0->memcontrol);
+ writel(0x40C01323, &dmc0->memconfig0);
+ writel(0x80000007, &dmc0->ivcontrol);
+
+ writel(0x64000000, &dmc0->prechconfig);
+ writel(0x9C4000FF, &dmc0->phycontrol0);
+ writel(0x0000005D, &dmc0->timingref);
+
+#if (CONFIG_CLK_MPLL == 330)
+ writel(0x2b47654e, &dmc0->timingrow);
+ writel(0x35330306, &dmc0->timingdata);
+ writel(0x442f0365, &dmc0->timingpower);
+#else
+ writel(0x34498691, &dmc0->timingrow);
+ writel(0x36330306, &dmc0->timingdata);
+ writel(0x50380365, &dmc0->timingpower);
+#endif
+ sdelay(0x100000);
+
+ writel(0x07000000, &dmc0->directcmd);
+ sdelay(0x100000);
+
+ writel(0x00071C00, &dmc0->directcmd);
+ sdelay(0x100000);
+
+ writel(0x00010BFC, &dmc0->directcmd);
+ sdelay(0x100000);
+
+ writel(0x00000608, &dmc0->directcmd);
+ writel(0x00000810, &dmc0->directcmd);
+ writel(0x00000C08, &dmc0->directcmd);
+
+ /*
+ * DMC 1
+ */
+ writel(0xE3855403, &dmc1->phyzqcontrol);
+ writel(0x71101008, &dmc1->phycontrol0);
+ writel(0x7110100A, &dmc1->phycontrol0);
+ writel(0x00000084, &dmc1->phycontrol1);
+ writel(0x71101008, &dmc1->phycontrol0);
+ writel(0x0000008C, &dmc1->phycontrol1);
+ writel(0x00000084, &dmc1->phycontrol1);
+ writel(0x0000008C, &dmc1->phycontrol1);
+ writel(0x00000084, &dmc1->phycontrol1);
+ writel(0x0FFF30CA, &dmc1->concontrol);
+ writel(0x00202500, &dmc1->memcontrol);
+ writel(0x40C01323, &dmc1->memconfig0);
+ writel(0x80000007, &dmc1->ivcontrol);
+ writel(0x64000000, &dmc1->prechconfig);
+ writel(0x9C4000FF, &dmc1->phycontrol0);
+ writel(0x0000005D, &dmc1->timingref);
+
+#if (CONFIG_CLK_MPLL == 330)
+ writel(0x2b47654e, &dmc1->timingrow);
+ writel(0x35330306, &dmc1->timingdata);
+ writel(0x442f0365, &dmc1->timingpower);
+#else
+ writel(0x34498691, &dmc1->timingrow);
+ writel(0x36330306, &dmc1->timingdata);
+ writel(0x50380365, &dmc1->timingpower);
+#endif
+ sdelay(0x100000);
+
+ writel(0x07000000, &dmc1->directcmd);
+ sdelay(0x100000);
+
+ writel(0x00071C00, &dmc1->directcmd);
+ sdelay(0x100000);
+
+ writel(0x00010BFC, &dmc1->directcmd);
+ sdelay(0x100000);
+
+ writel(0x00000608, &dmc1->directcmd);
+ writel(0x00000810, &dmc1->directcmd);
+ writel(0x00000C08, &dmc1->directcmd);
+}
+
+void mem_ctrl_init_2nd(void)
+{
+ struct exynos4_dmc *dmc0 =
+ (struct exynos4_dmc *)(EXYNOS4_MIU_BASE);
+ struct exynos4_dmc *dmc1 =
+ (struct exynos4_dmc *)(EXYNOS4_MIU_BASE + 0x10000);
+
+ writel(0x7F10100A, &dmc0->phycontrol0);
+ writel(0xE0000084, &dmc0->phycontrol1);
+ writel(0x7F10100B, &dmc0->phycontrol0);
+ sdelay(20000);
+ writel(0x0000008C, &dmc0->phycontrol1);
+ writel(0x00000084, &dmc0->phycontrol1);
+ sdelay(20000);
+
+ writel(0x7F10100A, &dmc1->phycontrol0);
+ writel(0xE0000084, &dmc1->phycontrol1);
+ writel(0x7F10100B, &dmc1->phycontrol0);
+ sdelay(20000);
+ writel(0x0000008C, &dmc1->phycontrol1);
+ writel(0x00000084, &dmc1->phycontrol1);
+ sdelay(20000);
+
+ writel(0x0FFF30FA, &dmc0->concontrol);
+ writel(0x0FFF30FA, &dmc1->concontrol);
+ writel(0x00202533, &dmc0->memcontrol);
+ writel(0x00202533, &dmc1->memcontrol);
+}
diff --git a/board/samsung/origen_quad/lowlevel_init.S b/board/samsung/origen_quad/lowlevel_init.S
new file mode 100644
index 0000000..fd30e11
--- /dev/null
+++ b/board/samsung/origen_quad/lowlevel_init.S
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Lowlevel initialize for the Insignal OrigenQUAD board (Exynos4x12)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include "setup.h"
+
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE
+
+ .globl lowlevel_init
+lowlevel_init:
+
+ /* use iRAM stack in bl2 */
+ ldr sp, =0x02060000
+ stmdb r13!, {ip,lr}
+
+ /* check reset status */
+ ldr r0, =(EXYNOS4_POWER_BASE + 0x800) /* INFORM1 */
+ ldr r1, [r0]
+
+ /* AFTR wakeup reset */
+ ldr r2, =S5P_CHECK_DIDLE
+ cmp r1, r2
+ beq exit_wakeup
+
+ /* LPA wakeup reset */
+ ldr r2, =S5P_CHECK_LPA
+ cmp r1, r2
+ beq exit_wakeup
+
+ /* Sleep wakeup reset */
+ ldr r2, =S5P_CHECK_SLEEP
+ cmp r1, r2
+ beq wakeup_reset
+
+ /*
+ * If U-boot is already running in RAM, no need to relocate U-Boot.
+ * Memory controller must be configured before relocating U-Boot
+ * in ram.
+ */
+ ldr r0, =0x0ffffff /* r0 <- Mask Bits*/
+ bic r1, pc, r0 /* pc <- current addr of code */
+ /* r1 <- unmasked bits of pc */
+ ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
+ bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
+ cmp r1, r2 /* compare r1, r2 */
+ beq 1f /* r0 == r1 then skip sdram init */
+
+ /* DMC initialize */
+ bl mem_ctrl_init
+
+ /* CMU initialize */
+ bl clock_ctrl_init
+
+ /* DMC initialize */
+ bl mem_ctrl_init_2nd
+
+1:
+ /* Trust zone initialize */
+ bl tzpc_init
+ ldmia r13!, {ip,pc}
+
+wakeup_reset:
+ bl clock_ctrl_init
+ bl mem_ctrl_init
+ bl tzpc_init
+
+exit_wakeup:
+ /* Load return address and jump to kernel */
+ ldr r0, =(EXYNOS4_POWER_BASE + 0x800) /* INFORM0 */
+
+ /* r1 = physical address of exynos4_cpu_resume function*/
+ ldr r1, [r0]
+
+ /* Jump to kernel */
+ mov pc, r1
+ nop
+ nop
+
+/*
+ * Setting TZPC[TrustZone Protection Controller]
+ */
+tzpc_init:
+
+ ldr r0, =TZPC0_BASE
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ mov r1, #0xbd
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ mov r1, #0xff
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC1_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC2_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC3_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC4_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ ldr r0, =TZPC5_BASE
+ str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+ str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+ mov pc, lr
diff --git a/board/samsung/origen_quad/origen_quad.c b/board/samsung/origen_quad/origen_quad.c
new file mode 100644
index 0000000..583fab0
--- /dev/null
+++ b/board/samsung/origen_quad/origen_quad.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Board initialize for the Insignal OrigenQUAD board (Exynos4x12)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/clock.h>
+#include "setup.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("\nBoard: " CONFIG_BOARDNAME "\n");
+ return 0;
+}
+#endif
+
+
+int board_init(void)
+{
+#ifdef CONFIG_EXYNOS_SPI
+ spi_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
+
+#ifdef CONFIG_RESERVED_DRAM
+ gd->ram_size -= CONFIG_RESERVED_DRAM;
+#endif
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size =
+ get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size =
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size =
+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE);
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size =
+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
+
+#ifdef CONFIG_RESERVED_DRAM
+ gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= CONFIG_RESERVED_DRAM;
+#endif
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_emmc_init(void)
+{
+ int err;
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+ if (err) {
+ debug("SDMMC0 not configured\n");
+ return err;
+ }
+ return s5p_mmc_init(0, 8);
+}
+
+int board_sdmmc_init(void)
+{
+ int err;
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("SDMMC2 not configured\n");
+ return err;
+ }
+ return s5p_mmc_init(2, 4);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int err;
+
+ struct exynos4_power *power =
+ (struct exynos4_power *)samsung_get_base_power();
+
+ if ((power->om_stat & 0x1E) == 0x8) {
+ err = board_emmc_init();
+ err = board_sdmmc_init();
+ } else {
+ err = board_sdmmc_init();
+ err = board_emmc_init();
+ }
+
+ return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SMC911X
+ if (smc9115_pre_init())
+ return -1;
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return 0;
+}
+
+static int board_uart_init(void)
+{
+ int err;
+ err = exynos_pinmux_config(PERIPH_ID_UART, PINMUX_FLAG_NONE);
+ if (err)
+ debug("UART%d not configured\n",
+ PERIPH_ID_UART - PERIPH_ID_UART0);
+ return err;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int err;
+ err = board_uart_init();
+ if (err)
+ debug("UART%d init failed\n",
+ PERIPH_ID_UART - PERIPH_ID_UART0);
+ return err;
+}
+#endif
diff --git a/board/samsung/origen_quad/setup.h b/board/samsung/origen_quad/setup.h
new file mode 100644
index 0000000..6df4341
--- /dev/null
+++ b/board/samsung/origen_quad/setup.h
@@ -0,0 +1,300 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Configuration settings for the Insignal Origen QUAD board (Exynos4412)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SETUP_ORIGEN_QUAD_H
+#define __SETUP_ORIGEN_QUAD_H
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+/* Set PLL */
+#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
+
+/* APLL */
+#define set_clk_div_cpu0(core2, apll, pclk_dbg, atb, periph, corem1, corem0, core) \
+ ((core2 << 28) \
+ |(apll << 24) \
+ |(pclk_dbg << 20) \
+ |(atb << 16) \
+ |(periph <<12) \
+ |(corem1 << 8) \
+ |(corem0 << 4) \
+ |(core))
+#define set_clk_div_cpu1(cores, hpm, copy) \
+ ((cores << 8) \
+ |(hpm << 4) \
+ |(copy))
+
+#if (CONFIG_CLK_APLL == 800)
+#define APLL_CON0_VAL set_pll(0x64, 0x3, 0x0)
+#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 1, 1, 3, 7, 5, 2, 0)
+#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(3, 0, 3)
+#elif (CONFIG_CLK_APLL == 1000)
+#define APLL_CON0_VAL set_pll(0x7D, 0x3, 0x0)
+#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 1, 1, 4, 7, 5, 2, 0)
+#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(3, 0, 4)
+#elif (CONFIG_CLK_APLL == 1100)
+#define APLL_CON0_VAL set_pll(0x113, 0x6, 0x0)
+#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 4, 7, 6, 3, 0)
+#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(4, 0, 4)
+#elif (CONFIG_CLK_APLL == 1200)
+#define APLL_CON0_VAL set_pll(0x96, 0x3, 0x0)
+#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 5, 7, 7, 3, 0)
+#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(4, 0, 4)
+#elif (CONFIG_CLK_APLL == 1300)
+#define APLL_CON0_VAL set_pll(0x145, 0x6, 0x0)
+#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 5, 7, 7, 3, 0)
+#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(5, 0, 5)
+#elif (CONFIG_CLK_APLL == 1400)
+#define APLL_CON0_VAL set_pll(0xAF, 0x3, 0x0)
+#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 6, 7, 7, 3, 0)
+#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(5, 0, 6)
+#elif (CONFIG_CLK_APLL == 1500)
+#define APLL_CON0_VAL set_pll(0xFA, 0x3, 0x0)
+#define CLK_DIV_CPU0_VAL set_clk_div_cpu0(0, 2, 1, 6, 7, 7, 4, 0)
+#define CLK_DIV_CPU1_VAL set_clk_div_cpu1(5, 0, 6)
+#else
+#error Not supported APLL freq
+#endif
+
+#define APLL_CON1_VAL (0x00803800)
+#define APLL_LOCK_VAL (((APLL_CON0_VAL >> 8) & 0x3F) * 270)
+
+/* EPLL */
+#define EPLL_CON0_VAL set_pll(0x40, 0x2, 0x3)
+#define EPLL_CON1_VAL (0x66010000)
+#define EPLL_CON2_VAL (0x00000080)
+#define EPLL_LOCK_VAL (((EPLL_CON0_VAL >> 8) & 0x3F) * 3000)
+
+/* MPLL */
+#if (CONFIG_CLK_MPLL == 200)
+#define MPLL_CON0_VAL set_pll(0x64, 0x3, 0x1)
+#elif (CONFIG_CLK_MPLL == 330)
+#define MPLL_CON0_VAL set_pll(0x116, 0x5, 0x1)
+#elif (CONFIG_CLK_MPLL == 400)
+#define MPLL_CON0_VAL set_pll(0x64, 0x3, 0x0)
+#else
+#error Not supported MPLL freq
+#endif
+#define MPLL_CON1_VAL (0x00803800)
+#define MPLL_LOCK_VAL (((MPLL_CON0_VAL >> 8) & 0x3F) * 270)
+
+/* VPLL */
+#define VPLL_CON0_VAL set_pll(0x48, 0x2, 0x3)
+#define VPLL_CON1_VAL (0x66010000)
+#define VPLL_CON2_VAL (0x00000080)
+#define VPLL_LOCK_VAL (((EPLL_CON0_VAL >> 8) & 0x3F) * 3000)
+
+/* CLK_SRC_CPU */
+#define MUX_MPLL_USER_SEL 1
+#define MUX_HPM_SEL 0
+#define MUX_CORE_SEL 0
+#define MUX_APLL_SEL 1
+#define CLK_SRC_CPU_VAL ((MUX_MPLL_USER_SEL << 24) \
+ |(MUX_HPM_SEL << 20) \
+ |(MUX_CORE_SEL << 16) \
+ |(MUX_APLL_SEL))
+
+/* CLK_SRC_TOP0 */
+#define MUX_ONENAND_SEL 0x0 /* 0 = DOUT133, 1 = DOUT166 */
+#define MUX_ACLK_133_SEL 0x0 /* 0 = SCLKMPLL, 1 = SCLKAPLL */
+#define MUX_ACLK_160_SEL 0x0
+#define MUX_ACLK_100_SEL 0x0
+#define MUX_ACLK_200_SEL 0x0
+#define MUX_VPLL_SEL 0x1
+#define MUX_EPLL_SEL 0x1
+#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL << 28) \
+ |(MUX_ACLK_133_SEL << 24) \
+ |(MUX_ACLK_160_SEL << 20) \
+ |(MUX_ACLK_100_SEL << 16) \
+ |(MUX_ACLK_200_SEL << 12) \
+ |(MUX_VPLL_SEL << 8) \
+ |(MUX_EPLL_SEL << 4))
+
+/* CLK_SRC_TOP1 */
+#define VPLLSRC_SEL 0x0 /* 0 = FINPLL, 1 = SCLKHDMI27M */
+#define CLK_SRC_TOP1_VAL (0x01111000)
+
+/* CLK_DIV_TOP */
+#define ACLK_400_MCUISP_RATIO 0x1
+#define ACLK_266_GPS_RATIO 0x2
+#define ONENAND_RATIO 0x1
+#define ACLK_133_RATIO 0x5
+#define ACLK_160_RATIO 0x4
+#define ACLK_100_RATIO 0x7
+#define ACLK_200_RATIO 0x4
+#define CLK_DIV_TOP_VAL ((ACLK_400_MCUISP_RATIO << 24) \
+ |(ACLK_266_GPS_RATIO << 20) \
+ |(ONENAND_RATIO << 16) \
+ |(ACLK_133_RATIO << 12) \
+ |(ACLK_160_RATIO << 8) \
+ |(ACLK_100_RATIO << 4) \
+ |(ACLK_200_RATIO))
+
+/* CLK_SRC_LEFTBUS */
+#define CLK_SRC_LEFTBUS_VAL (0x10)
+
+/* CLK_DIV_LEFRBUS */
+#define GPL_RATIO 0x1
+#define GDL_RATIO 0x3
+#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4)|(GDL_RATIO))
+
+/* CLK_SRC_RIGHTBUS */
+#define CLK_SRC_RIGHTBUS_VAL (0x10)
+
+/* CLK_DIV_RIGHTBUS */
+#define GPR_RATIO 0x1
+#define GDR_RATIO 0x3
+#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4)|(GDR_RATIO))
+
+/* CLK_SRC_DMC */
+#define MUX_PWI_SEL 0x1
+#define MUX_CORE_TIMERS_SEL 0x1
+#define MUX_DPHY_SEL 0x0
+#define MUX_DMC_BUS_SEL 0x0
+#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL << 16) \
+ |(MUX_CORE_TIMERS_SEL << 12) \
+ |(MUX_DPHY_SEL << 8) \
+ |(MUX_DMC_BUS_SEL << 4))
+
+/* CLK_DIV_DMC0 */
+#define CORE_TIMERS_RATIO 0x0
+#define COPY2_RATIO 0x0
+#define DMCP_RATIO 0x1
+#define DMCD_RATIO 0x1
+#if (CONFIG_CLK_MPLL == 200)
+#define DMC_RATIO 0x3
+#else
+#define DMC_RATIO 0x1
+#endif
+#define DPHY_RATIO 0x1
+#define ACP_PCLK_RATIO 0x1
+#define ACP_RATIO 0x3
+
+#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
+ |(COPY2_RATIO << 24) \
+ |(DMCP_RATIO << 20) \
+ |(DMCD_RATIO << 16) \
+ |(DMC_RATIO << 12) \
+ |(DPHY_RATIO << 8) \
+ |(ACP_PCLK_RATIO << 4) \
+ |(ACP_RATIO))
+
+#define CLK_DIV_DMC1_VAL (0x07071713)
+
+/* CLK_SRC_PERIL0 */
+#define PWM_SEL 0
+#define UART4_SEL 6
+#define UART3_SEL 6
+#define UART2_SEL 6
+#define UART1_SEL 6
+#define UART0_SEL 6
+#define CLK_SRC_PERIL0_VAL ((PWM_SEL << 24) \
+ |(UART4_SEL << 16) \
+ |(UART3_SEL << 12) \
+ |(UART2_SEL<< 8) \
+ |(UART1_SEL << 4) \
+ |(UART0_SEL))
+
+/* CLK_DIV_PERIL0 */
+#define UART4_RATIO 7
+#define UART3_RATIO 7
+#define UART2_RATIO 7
+#define UART1_RATIO 7
+#define UART0_RATIO 7
+#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
+ |(UART3_RATIO << 12) \
+ |(UART2_RATIO << 8) \
+ |(UART1_RATIO << 4) \
+ |(UART0_RATIO))
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP 0x00000BAD
+#define S5P_CHECK_DIDLE 0xBAD00000
+#define S5P_CHECK_LPA 0xABAD0000
+
+/* TZPC */
+#define TZPC_BASE 0x10110000
+#define TZPC_OFFSET 0x10000
+#define TZPC0_BASE (TZPC_BASE)
+#define TZPC1_BASE (TZPC0_BASE + TZPC_OFFSET)
+#define TZPC2_BASE (TZPC1_BASE + TZPC_OFFSET)
+#define TZPC3_BASE (TZPC2_BASE + TZPC_OFFSET)
+#define TZPC4_BASE (TZPC3_BASE + TZPC_OFFSET)
+#define TZPC5_BASE (TZPC4_BASE + TZPC_OFFSET)
+#define TZPC_DECPROT0SET_OFFSET 0x804
+#define TZPC_DECPROT1SET_OFFSET 0x810
+#define TZPC_DECPROT2SET_OFFSET 0x81C
+#define TZPC_DECPROT3SET_OFFSET 0x828
+
+/* IMAGE SIZE (BYTE) */
+#define MBR_BYTE_COUNT CONFIG_MBR_SIZE
+#define SBL_BYTE_COUNT CONFIG_SBL_SIZE
+#define BL1_BYTE_COUNT CONFIG_BL1_SIZE
+#define BL2_BYTE_COUNT CONFIG_BL2_SIZE
+#define ENV_BYTE_COUNT CONFIG_ENV_SIZE
+
+/* IMAGE OFFSET (BYTE) */
+#define MBR_BYTE_OFFSET (0)
+#define SBL_BYTE_OFFSET (MBR_BYTE_OFFSET + MBR_BYTE_COUNT)
+#define BL1_BYTE_OFFSET (SBL_BYTE_OFFSET + SBL_BYTE_COUNT)
+#define BL2_BYTE_OFFSET (BL1_BYTE_OFFSET + BL1_BYTE_COUNT)
+#define ENV_BYTE_OFFSET (Bl2_BYTE_OFFSET + BL2_BYTE_COUNT)
+
+#define SDMMC_BLK_SIZE (512)
+
+/* IMAGE SIZE (BLOCK) */
+#define SBL_BLK_COUNT (SBL_BYTE_COUNT / SDMMC_BLK_SIZE)
+#define BL1_BLK_COUNT (BL1_BYTE_COUNT / SDMMC_BLK_SIZE)
+#define BL2_BLK_COUNT (BL2_BYTE_COUNT / SDMMC_BLK_SIZE)
+#define ENV_BLK_COUNT (ENV_BYTE_COUNT / SDMMC_BLK_SIZE)
+
+/* IMAGE OFFSET (BLOCK) */
+#define SBL_BLK_OFFSET (SBL_BYTE_OFFSET / SDMMC_BLK_SIZE)
+#define BL1_BLK_OFFSET (BL1_BYTE_OFFSET / SDMMC_BLK_SIZE)
+#define BL2_BLK_OFFSET (BL2_BYTE_OFFSET / SDMMC_BLK_SIZE)
+#define ENV_BLK_OFFSET (ENV_BYTE_OFFSET / SDMMC_BLK_SIZE)
+
+/* UART */
+#if defined(CONFIG_SERIAL0)
+#define PERIPH_ID_UART PERIPH_ID_UART0
+#elif defined(CONFIG_SERIAL1)
+#define PERIPH_ID_UART PERIPH_ID_UART1
+#elif defined(CONFIG_SERIAL2)
+#define PERIPH_ID_UART PERIPH_ID_UART2
+#elif defined(CONFIG_SERIAL3)
+#define PERIPH_ID_UART PERIPH_ID_UART3
+#endif
+
+#ifndef __ASSEMBLY__
+void sdelay(unsigned long);
+void clock_ctrl_init(void);
+void mem_ctrl_init(void);
+void tzpc_init(void);
+#endif
+
+#endif /* __SETUP_ORIGEN_QUAD_H */
diff --git a/boards.cfg b/boards.cfg
index 388e4a4..66b9ee3 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -284,6 +284,7 @@ s5pc210_universal arm armv7 universal_c210 samsung
smdk5250 arm armv7 smdk5250 samsung exynos
smdkv310 arm armv7 smdkv310 samsung exynos
trats arm armv7 trats samsung exynos
+origen_quad arm armv7 origen_quad samsung exynos
harmony arm armv7:arm720t harmony nvidia tegra20
seaboard arm armv7:arm720t seaboard nvidia tegra20
ventana arm armv7:arm720t ventana nvidia tegra20
diff --git a/include/configs/origen_quad.h b/include/configs/origen_quad.h
new file mode 100644
index 0000000..d65b470
--- /dev/null
+++ b/include/configs/origen_quad.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Copyright (C) 2012 Insignal
+ *
+ * Configuration settings for the Insignal OrigenQUAD board (Exynos4x12)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_ORIGEN_QUAD_H
+#define __CONFIG_ORIGEN_QUAD_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_S5P /* S5P Family */
+#define CONFIG_EXYNOS4 /* which is in a Exynos4 series */
+#define CONFIG_EXYNOS4412 /* which is in a Exynos4412 */
+#define CONFIG_ORIGEN_QUAD /* which is in a ORIGEN QUAD */
+#define CONFIG_BOARDNAME "Origen"
+#define CONFIG_IDENT_STRING " for Insignal Origen"
+#define CONFIG_MACH_TYPE 3455
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+/*
+ * Clock / PLL
+ */
+#define CONFIG_SYS_CLK_FREQ 24000000 /* 24MHz input clock */
+#define CONFIG_CLK_APLL 1000
+#define CONFIG_CLK_MPLL 400
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_PWM
+
+/*
+ * Memory
+ */
+/* Default address */
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20UL))
+/* Cache */
+#define CONFIG_L2_OFF 1
+#define CONFIG_SYS_DCACHE_OFF /* Keep L2 Cache Disabled */
+/* DRAM */
+#define CONFIG_NR_DRAM_BANKS 4 /* 256 MB * 4 = 1 GB */
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (PHYS_SDRAM_3 + PHYS_SDRAM_3_SIZE)
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
+/* Reserved */
+#define CONFIG_RESERVED_DRAM 0x100000
+/* Mem test */
+#define CONFIG_CMD_MEMORY
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_4 + PHYS_SDRAM_4_SIZE - (8UL << 20UL))
+
+/*
+ * Serial
+ */
+#define CONFIG_SERIAL2 2 /* use SERIAL2 in 0~3 */
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+#define CONFIG_CMD_MMC
+
+/*
+ * File System
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Flash
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Image map on sdmmc/emmc
+ */
+#define CONFIG_SECURE_BL1_ONLY
+#define CONFIG_SPL
+#define CONFIG_MBR_SIZE (512)
+#define CONFIG_SBL_SIZE (8UL << 10) /* 8KB */
+#define CONFIG_BL1_SIZE (16UL << 10) /* 16KB */
+#define CONFIG_BL2_SIZE (512UL << 10) /* 512KB */
+
+/*
+ * Console
+ */
+#define CONFIG_SYS_PROMPT CONFIG_BOARDNAME " # "
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE 384
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+
+/*
+ * Commands
+ */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET (CONFIG_MBR_SIZE \
+ +CONFIG_SBL_SIZE \
+ +CONFIG_BL1_SIZE \
+ +CONFIG_BL2_SIZE)
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
+#define CONFIG_ENV_OVERWRITE
+/* Default */
+#define CONFIG_BOOTCOMMAND "fatload mmc 0 40008000 uImage; bootm 40008000"
+
+/*
+ * Misc
+ */
+/* Initialize */
+#define CONFIG_ARCH_CPU_INIT 1
+#define CONFIG_BOARD_EARLY_INIT_F 1
+/* display information */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+/* Delay */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+/* TAGS */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#endif /* __CONFIG_ORIGEN_QUAD_H */
diff --git a/tools/Makefile b/tools/Makefile
index 686840a..3da314c 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -68,6 +68,7 @@ BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
BIN_FILES-y += mkenvimage$(SFX)
BIN_FILES-y += mkimage$(SFX)
+BIN_FILES-$(CONFIG_EXYNOS4) += mk$(BOARD)spl$(SFX)
BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX)
BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
@@ -97,6 +98,7 @@ NOPED_OBJ_FILES-y += imximage.o
NOPED_OBJ_FILES-y += omapimage.o
NOPED_OBJ_FILES-y += mkenvimage.o
NOPED_OBJ_FILES-y += mkimage.o
+OBJ_FILES-$(CONFIG_EXYNOS4) += mkexynosspl.o
OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 2/4] EXYNOS4: Add pinmux support for I2C
2012-12-12 7:54 ` [U-Boot] [PATCH 2/4] EXYNOS4: Add pinmux support for I2C Jeong Hyeon Kim
@ 2012-12-12 8:16 ` Heiko Schocher
2012-12-12 10:19 ` 김정현
0 siblings, 1 reply; 11+ messages in thread
From: Heiko Schocher @ 2012-12-12 8:16 UTC (permalink / raw)
To: u-boot
Hello Jeong,
On 12.12.2012 08:54, Jeong Hyeon Kim wrote:
> From: Jeong-Hyeon Kim<jhkim@insignal.co.kr>
>
> This patch adds pinmux support for I2C channels
>
> Signed-off-by: Jeong-Hyeon Kim<jhkim@insignal.co.kr>
> ---
> arch/arm/cpu/armv7/exynos/pinmux.c | 51 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
similiar patch is applied to u-boot-i2c, see:
http://git.denx.de/?p=u-boot/u-boot-i2c.git;a=commitdiff;h=4d4628dcaa51b501bec148a9c5c55df3920350dc
and pull request is pending. Can you check, if the above patch fits
your needs?
Thanks!
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 2/4] EXYNOS4: Add pinmux support for I2C
2012-12-12 8:16 ` Heiko Schocher
@ 2012-12-12 10:19 ` 김정현
0 siblings, 0 replies; 11+ messages in thread
From: 김정현 @ 2012-12-12 10:19 UTC (permalink / raw)
To: u-boot
Dear Heiko,
Thanks for your concern.
I didn't know the patch.
It can be replaced my patch.
Thank you,
JHKIM
2012? 12? 12? 17:16, Heiko Schocher ? ?:
> Hello Jeong,
>
> On 12.12.2012 08:54, Jeong Hyeon Kim wrote:
>> From: Jeong-Hyeon Kim<jhkim@insignal.co.kr>
>>
>> This patch adds pinmux support for I2C channels
>>
>> Signed-off-by: Jeong-Hyeon Kim<jhkim@insignal.co.kr>
>> ---
>> arch/arm/cpu/armv7/exynos/pinmux.c | 51
>> ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 51 insertions(+)
>
> similiar patch is applied to u-boot-i2c, see:
>
> http://git.denx.de/?p=u-boot/u-boot-i2c.git;a=commitdiff;h=4d4628dcaa51b501bec148a9c5c55df3920350dc
>
>
> and pull request is pending. Can you check, if the above patch fits
> your needs?
>
> Thanks!
>
> bye,
> Heiko
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 3/4] EXYNOS4: Add support for Exynos4x12 SoCs
2012-12-12 7:54 ` [U-Boot] [PATCH 3/4] EXYNOS4: Add support for Exynos4x12 SoCs Jeong Hyeon Kim
@ 2012-12-13 6:19 ` Chander Kashyap
2012-12-13 6:19 ` Chander Kashyap
0 siblings, 1 reply; 11+ messages in thread
From: Chander Kashyap @ 2012-12-13 6:19 UTC (permalink / raw)
To: u-boot
Dear Kim,
On 12 December 2012 13:24, Jeong Hyeon Kim <snow.jhkim@gmail.com> wrote:
> From: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
>
> This patch adds the support for Exynos4212/4412.
>
> Samsung's ARM Cortex-A9 based Exynos4x12 SoCs and Exynos4210 are similar.
> Address of a few registers are different in CMU part like MPLL.
>
> Signed-off-by: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
> ---
> arch/arm/cpu/armv7/exynos/clock.c | 7 +-
> arch/arm/include/asm/arch-exynos/clock.h | 240 ++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-exynos/cpu.h | 1 +
> 3 files changed, 247 insertions(+), 1 deletion(-)
>
As i discussed with you these changes has been already posted.
http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/148856
Kindly use them and resend yours patches.
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index fe61f88..47e2e6c 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
Please have a look patch at the link.
[PATCH] EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency
> @@ -94,7 +94,12 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
> r = readl(&clk->apll_con0);
> break;
> case MPLL:
> - r = readl(&clk->mpll_con0);
> + if (proid_is_exynos4412()) {
> + struct exynos4412_clock *clk4412 =
> + (struct exynos4412_clock *)samsung_get_base_clock();
> + r = readl(&clk4412->mpll_con0);
> + } else
> + r = readl(&clk->mpll_con0);
> break;
> case EPLL:
> r = readl(&clk->epll_con0);
> diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
> index ff6781a..5d4ed5c 100644
> --- a/arch/arm/include/asm/arch-exynos/clock.h
> +++ b/arch/arm/include/asm/arch-exynos/clock.h
> @@ -251,6 +251,246 @@ struct exynos4_clock {
> unsigned int div_iem_l1;
> };
>
> +struct exynos4412_clock {
> + unsigned char res1[0x4200];
> + unsigned int src_leftbus;
> + unsigned char res2[0x1fc];
> + unsigned int mux_stat_leftbus;
> + unsigned char res3[0xfc];
> + unsigned int div_leftbus;
> + unsigned char res4[0xfc];
> + unsigned int div_stat_leftbus;
> + unsigned char res5[0x1fc];
> + unsigned int gate_ip_leftbus;
> + unsigned char res6[0x12c];
> + unsigned int gate_ip_image;
> + unsigned char res7[0xcc];
> + unsigned int clkout_cmu_leftbus;
> + unsigned int clkout_cmu_leftbus_div_stat;
> + unsigned char res8[0x37f8];
> + unsigned int src_rightbus;
> + unsigned char res9[0x1fc];
> + unsigned int mux_stat_rightbus;
> + unsigned char res10[0xfc];
> + unsigned int div_rightbus;
> + unsigned char res11[0xfc];
> + unsigned int div_stat_rightbus;
> + unsigned char res12[0x1fc];
> + unsigned int gate_ip_rightbus;
> + unsigned char res13[0x15c];
> + unsigned int gate_ip_perir;
> + unsigned char res14[0x9c];
> + unsigned int clkout_cmu_rightbus;
> + unsigned int clkout_cmu_rightbus_div_stat;
> + unsigned char res15[0x3608];
> + unsigned int epll_lock;
> + unsigned char res16[0xc];
> + unsigned int vpll_lock;
> + unsigned char res17[0xec];
> + unsigned int epll_con0;
> + unsigned int epll_con1;
> + unsigned int epll_con2;
> + unsigned char res18[0x4];
> + unsigned int vpll_con0;
> + unsigned int vpll_con1;
> + unsigned int vpll_con2;
> + unsigned char res19[0xe4];
> + unsigned int src_top0;
> + unsigned int src_top1;
> + unsigned char res20[0x8];
> + unsigned int src_cam0;
> + unsigned int src_tv;
> + unsigned int src_mfc;
> + unsigned int src_g3d;
> + unsigned char res21[0x4];
> + unsigned int src_lcd0;
> + unsigned int src_isp;
> + unsigned int src_maudio;
> + unsigned int src_fsys;
> + unsigned char res22[0xc];
> + unsigned int src_peril0;
> + unsigned int src_peril1;
> + unsigned int src_cam1;
> + unsigned char res23[0xc4];
> + unsigned int src_mask_cam0;
> + unsigned int src_mask_tv;
> + unsigned char res24[0xc];
> + unsigned int src_mask_lcd;
> + unsigned int src_mask_isp;
> + unsigned int src_mask_maudio;
> + unsigned int src_mask_fsys;
> + unsigned char res25[0xc];
> + unsigned int src_mask_peril0;
> + unsigned int src_mask_peril1;
> + unsigned char res26[0xb8];
> + unsigned int mux_stat_top;
> + unsigned int mux_stat_top1;
> + unsigned char res27[0x10];
> + unsigned int mux_stat_mfc;
> + unsigned int mux_stat_g3d;
> + unsigned char res28[0x28];
> + unsigned int mux_stat_cam1;
> + unsigned char res29[0xb4];
> + unsigned int div_top;
> + unsigned char res30[0xc];
> + unsigned int div_cam0;
> + unsigned int div_tv;
> + unsigned int div_mfc;
> + unsigned int div_g3d;
> + unsigned char res31[0x4];
> + unsigned int div_lcd;
> + unsigned int div_isp;
> + unsigned int div_maudio;
> + unsigned int div_fsys0;
> + unsigned int div_fsys1;
> + unsigned int div_fsys2;
> + unsigned int div_fsys3;
> + unsigned int div_peril0;
> + unsigned int div_peril1;
> + unsigned int div_peril2;
> + unsigned int div_peril3;
> + unsigned int div_peril4;
> + unsigned int div_peril5;
> + unsigned int div_cam1;
> + unsigned char res32[0x14];
> + unsigned int div2_ratio;
> + unsigned char res33[0x8c];
> + unsigned int div_stat_top;
> + unsigned char res34[0xc];
> + unsigned int div_stat_cam0;
> + unsigned int div_stat_tv;
> + unsigned int div_stat_mfc;
> + unsigned int div_stat_g3d;
> + unsigned char res35[0x4];
> + unsigned int div_stat_lcd;
> + unsigned int div_stat_isp;
> + unsigned int div_stat_maudio;
> + unsigned int div_stat_fsys0;
> + unsigned int div_stat_fsys1;
> + unsigned int div_stat_fsys2;
> + unsigned int div_stat_fsys3;
> + unsigned int div_stat_peril0;
> + unsigned int div_stat_peril1;
> + unsigned int div_stat_peril2;
> + unsigned int div_stat_peril3;
> + unsigned int div_stat_peril4;
> + unsigned int div_stat_peril5;
> + unsigned int div_stat_cam1;
> + unsigned char res36[0x14];
> + unsigned int div2_stat;
> + unsigned char res37[0xc0];
> + unsigned int gate_bus_fsys1;
> + unsigned char res38[0x1d8];
> + unsigned int gate_ip_cam;
> + unsigned int gate_ip_tv;
> + unsigned int gate_ip_mfc;
> + unsigned int gate_ip_g3d;
> + unsigned char res39[0x4];
> + unsigned int gate_ip_lcd;
> + unsigned int gate_ip_isp;
> + unsigned char res40[0x4];
> + unsigned int gate_ip_fsys;
> + unsigned char res41[0x8];
> + unsigned int gate_ip_gps;
> + unsigned int gate_ip_peril;
> + unsigned char res42[0x1c];
> + unsigned int gate_block;
> + unsigned char res43[0x8c];
> + unsigned int clkout_cmu_top;
> + unsigned int clkout_cmu_top_div_stat;
> + unsigned char res44[0x3600];
> + unsigned int mpll_lock;
> + unsigned char res45[0xfc];
> + unsigned int mpll_con0;
> + unsigned int mpll_con1;
> + unsigned char res46[0xf0];
> + unsigned int src_dmc;
> + unsigned char res47[0xfc];
> + unsigned int src_mask_dmc;
> + unsigned char res48[0xfc];
> + unsigned int mux_stat_dmc;
> + unsigned char res49[0xfc];
> + unsigned int div_dmc0;
> + unsigned int div_dmc1;
> + unsigned char res50[0xf8];
> + unsigned int div_stat_dmc0;
> + unsigned int div_stat_dmc1;
> + unsigned char res51[0x2f8];
> + unsigned int gate_ip_dmc;
> + unsigned int gate_ip_dmc1;
> + unsigned char res52[0xf8];
> + unsigned int clkout_cmu_dmc;
> + unsigned int clkout_cmu_dmc_div_stat;
> + unsigned char res53[0x5f8];
> + unsigned int dcgidx_map0;
> + unsigned int dcgidx_map1;
> + unsigned int dcgidx_map2;
> + unsigned char res54[0x14];
> + unsigned int dcgperf_map0;
> + unsigned int dcgperf_map1;
> + unsigned char res55[0x18];
> + unsigned int dvcidx_map;
> + unsigned char res56[0x1c];
> + unsigned int freq_cpu;
> + unsigned int freq_dpm;
> + unsigned char res57[0x18];
> + unsigned int dvsemclk_en;
> + unsigned int maxperf;
> + unsigned char res58[0xc];
> + unsigned int dmc_puause_ctrl;
> + unsigned int ddrphy_lock_ctrl;
> + unsigned int c2c_state;
> + unsigned char res59[0x2f60];
> + unsigned int apll_lock;
> + unsigned char res60[0xfc];
> + unsigned int apll_con0;
> + unsigned int apll_con1;
> + unsigned char res61[0xf8];
> + unsigned int src_cpu;
> + unsigned char res62[0x1fc];
> + unsigned int mux_stat_cpu;
> + unsigned char res63[0xfc];
> + unsigned int div_cpu0;
> + unsigned int div_cpu1;
> + unsigned char res64[0xf8];
> + unsigned int div_stat_cpu0;
> + unsigned int div_stat_cpu1;
> + unsigned char res65[0x2f8];
> + unsigned int gate_ip_cpu;
> + unsigned char res66[0xfc];
> + unsigned int clkout_cmu_cpu;
> + unsigned int clkout_cmu_cpu_div_stat;
> + unsigned char res67[0x5f8];
> + unsigned int armclk_stopctrl;
> + unsigned int atclk_stopctrl;
> + unsigned char res68[0x18];
> + unsigned int pwr_ctrl;
> + unsigned int pwr_ctrl2;
> + unsigned char res69[0x3d8];
> + unsigned int l2_status;
> + unsigned char res70[0xc];
> + unsigned int cpu_status;
> + unsigned char res71[0xc];
> + unsigned int ptm_status;
> + unsigned char res72[0x2edc];
> + unsigned int clk_div_isp0;
> + unsigned int clk_div_isp1;
> + unsigned char res73[0xf8];
> + unsigned int clk_div_stat_isp0;
> + unsigned int clk_div_stat_isp1;
> + unsigned char res74[0x3f8];
> + unsigned int gate_ip_isp0;
> + unsigned int gate_ip_isp1;
> + unsigned char res75[0x1f8];
> + unsigned int clkout_cmu_isp;
> + unsigned int clkout_cmu_isp_stat;
> + unsigned char res76[0xf8];
> + unsigned int clkout_cmu_spare0;
> + unsigned int clkout_cmu_spare1;
> + unsigned int clkout_cmu_spare2;
> + unsigned int clkout_cmu_spare3;
> +};
> +
> struct exynos5_clock {
> unsigned int apll_lock;
> unsigned char res1[0xfc];
> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
> index d1b2ea8..7ee5366 100644
> --- a/arch/arm/include/asm/arch-exynos/cpu.h
> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
> @@ -152,6 +152,7 @@ static inline int proid_is_##type(void) \
> }
>
> IS_EXYNOS_TYPE(exynos4210, 0x4210)
> +IS_EXYNOS_TYPE(exynos4412, 0x4412)
> IS_EXYNOS_TYPE(exynos5250, 0x5250)
>
> #define SAMSUNG_BASE(device, base) \
> --
> 1.7.9.5
>
--
with warm regards,
Chander Kashyap
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 3/4] EXYNOS4: Add support for Exynos4x12 SoCs
2012-12-13 6:19 ` Chander Kashyap
@ 2012-12-13 6:19 ` Chander Kashyap
2012-12-13 8:21 ` 김정현
0 siblings, 1 reply; 11+ messages in thread
From: Chander Kashyap @ 2012-12-13 6:19 UTC (permalink / raw)
To: u-boot
On 13 December 2012 11:49, Chander Kashyap <chander.kashyap@linaro.org> wrote:
> Dear Kim,
>
> On 12 December 2012 13:24, Jeong Hyeon Kim <snow.jhkim@gmail.com> wrote:
>> From: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
>>
>> This patch adds the support for Exynos4212/4412.
>>
>> Samsung's ARM Cortex-A9 based Exynos4x12 SoCs and Exynos4210 are similar.
>> Address of a few registers are different in CMU part like MPLL.
>>
>> Signed-off-by: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
>> ---
>> arch/arm/cpu/armv7/exynos/clock.c | 7 +-
>> arch/arm/include/asm/arch-exynos/clock.h | 240 ++++++++++++++++++++++++++++++
>> arch/arm/include/asm/arch-exynos/cpu.h | 1 +
>> 3 files changed, 247 insertions(+), 1 deletion(-)
>>
> As i discussed with you these changes has been already posted.
> http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/148856
> Kindly use them and resend yours patches.
>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
>> index fe61f88..47e2e6c 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> Please have a look patch at the link.
> [PATCH] EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/143640
>> @@ -94,7 +94,12 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
>> r = readl(&clk->apll_con0);
>> break;
>> case MPLL:
>> - r = readl(&clk->mpll_con0);
>> + if (proid_is_exynos4412()) {
>> + struct exynos4412_clock *clk4412 =
>> + (struct exynos4412_clock *)samsung_get_base_clock();
>> + r = readl(&clk4412->mpll_con0);
>> + } else
>> + r = readl(&clk->mpll_con0);
>> break;
>> case EPLL:
>> r = readl(&clk->epll_con0);
>> diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
>> index ff6781a..5d4ed5c 100644
>> --- a/arch/arm/include/asm/arch-exynos/clock.h
>> +++ b/arch/arm/include/asm/arch-exynos/clock.h
>> @@ -251,6 +251,246 @@ struct exynos4_clock {
>> unsigned int div_iem_l1;
>> };
>>
>> +struct exynos4412_clock {
>> + unsigned char res1[0x4200];
>> + unsigned int src_leftbus;
>> + unsigned char res2[0x1fc];
>> + unsigned int mux_stat_leftbus;
>> + unsigned char res3[0xfc];
>> + unsigned int div_leftbus;
>> + unsigned char res4[0xfc];
>> + unsigned int div_stat_leftbus;
>> + unsigned char res5[0x1fc];
>> + unsigned int gate_ip_leftbus;
>> + unsigned char res6[0x12c];
>> + unsigned int gate_ip_image;
>> + unsigned char res7[0xcc];
>> + unsigned int clkout_cmu_leftbus;
>> + unsigned int clkout_cmu_leftbus_div_stat;
>> + unsigned char res8[0x37f8];
>> + unsigned int src_rightbus;
>> + unsigned char res9[0x1fc];
>> + unsigned int mux_stat_rightbus;
>> + unsigned char res10[0xfc];
>> + unsigned int div_rightbus;
>> + unsigned char res11[0xfc];
>> + unsigned int div_stat_rightbus;
>> + unsigned char res12[0x1fc];
>> + unsigned int gate_ip_rightbus;
>> + unsigned char res13[0x15c];
>> + unsigned int gate_ip_perir;
>> + unsigned char res14[0x9c];
>> + unsigned int clkout_cmu_rightbus;
>> + unsigned int clkout_cmu_rightbus_div_stat;
>> + unsigned char res15[0x3608];
>> + unsigned int epll_lock;
>> + unsigned char res16[0xc];
>> + unsigned int vpll_lock;
>> + unsigned char res17[0xec];
>> + unsigned int epll_con0;
>> + unsigned int epll_con1;
>> + unsigned int epll_con2;
>> + unsigned char res18[0x4];
>> + unsigned int vpll_con0;
>> + unsigned int vpll_con1;
>> + unsigned int vpll_con2;
>> + unsigned char res19[0xe4];
>> + unsigned int src_top0;
>> + unsigned int src_top1;
>> + unsigned char res20[0x8];
>> + unsigned int src_cam0;
>> + unsigned int src_tv;
>> + unsigned int src_mfc;
>> + unsigned int src_g3d;
>> + unsigned char res21[0x4];
>> + unsigned int src_lcd0;
>> + unsigned int src_isp;
>> + unsigned int src_maudio;
>> + unsigned int src_fsys;
>> + unsigned char res22[0xc];
>> + unsigned int src_peril0;
>> + unsigned int src_peril1;
>> + unsigned int src_cam1;
>> + unsigned char res23[0xc4];
>> + unsigned int src_mask_cam0;
>> + unsigned int src_mask_tv;
>> + unsigned char res24[0xc];
>> + unsigned int src_mask_lcd;
>> + unsigned int src_mask_isp;
>> + unsigned int src_mask_maudio;
>> + unsigned int src_mask_fsys;
>> + unsigned char res25[0xc];
>> + unsigned int src_mask_peril0;
>> + unsigned int src_mask_peril1;
>> + unsigned char res26[0xb8];
>> + unsigned int mux_stat_top;
>> + unsigned int mux_stat_top1;
>> + unsigned char res27[0x10];
>> + unsigned int mux_stat_mfc;
>> + unsigned int mux_stat_g3d;
>> + unsigned char res28[0x28];
>> + unsigned int mux_stat_cam1;
>> + unsigned char res29[0xb4];
>> + unsigned int div_top;
>> + unsigned char res30[0xc];
>> + unsigned int div_cam0;
>> + unsigned int div_tv;
>> + unsigned int div_mfc;
>> + unsigned int div_g3d;
>> + unsigned char res31[0x4];
>> + unsigned int div_lcd;
>> + unsigned int div_isp;
>> + unsigned int div_maudio;
>> + unsigned int div_fsys0;
>> + unsigned int div_fsys1;
>> + unsigned int div_fsys2;
>> + unsigned int div_fsys3;
>> + unsigned int div_peril0;
>> + unsigned int div_peril1;
>> + unsigned int div_peril2;
>> + unsigned int div_peril3;
>> + unsigned int div_peril4;
>> + unsigned int div_peril5;
>> + unsigned int div_cam1;
>> + unsigned char res32[0x14];
>> + unsigned int div2_ratio;
>> + unsigned char res33[0x8c];
>> + unsigned int div_stat_top;
>> + unsigned char res34[0xc];
>> + unsigned int div_stat_cam0;
>> + unsigned int div_stat_tv;
>> + unsigned int div_stat_mfc;
>> + unsigned int div_stat_g3d;
>> + unsigned char res35[0x4];
>> + unsigned int div_stat_lcd;
>> + unsigned int div_stat_isp;
>> + unsigned int div_stat_maudio;
>> + unsigned int div_stat_fsys0;
>> + unsigned int div_stat_fsys1;
>> + unsigned int div_stat_fsys2;
>> + unsigned int div_stat_fsys3;
>> + unsigned int div_stat_peril0;
>> + unsigned int div_stat_peril1;
>> + unsigned int div_stat_peril2;
>> + unsigned int div_stat_peril3;
>> + unsigned int div_stat_peril4;
>> + unsigned int div_stat_peril5;
>> + unsigned int div_stat_cam1;
>> + unsigned char res36[0x14];
>> + unsigned int div2_stat;
>> + unsigned char res37[0xc0];
>> + unsigned int gate_bus_fsys1;
>> + unsigned char res38[0x1d8];
>> + unsigned int gate_ip_cam;
>> + unsigned int gate_ip_tv;
>> + unsigned int gate_ip_mfc;
>> + unsigned int gate_ip_g3d;
>> + unsigned char res39[0x4];
>> + unsigned int gate_ip_lcd;
>> + unsigned int gate_ip_isp;
>> + unsigned char res40[0x4];
>> + unsigned int gate_ip_fsys;
>> + unsigned char res41[0x8];
>> + unsigned int gate_ip_gps;
>> + unsigned int gate_ip_peril;
>> + unsigned char res42[0x1c];
>> + unsigned int gate_block;
>> + unsigned char res43[0x8c];
>> + unsigned int clkout_cmu_top;
>> + unsigned int clkout_cmu_top_div_stat;
>> + unsigned char res44[0x3600];
>> + unsigned int mpll_lock;
>> + unsigned char res45[0xfc];
>> + unsigned int mpll_con0;
>> + unsigned int mpll_con1;
>> + unsigned char res46[0xf0];
>> + unsigned int src_dmc;
>> + unsigned char res47[0xfc];
>> + unsigned int src_mask_dmc;
>> + unsigned char res48[0xfc];
>> + unsigned int mux_stat_dmc;
>> + unsigned char res49[0xfc];
>> + unsigned int div_dmc0;
>> + unsigned int div_dmc1;
>> + unsigned char res50[0xf8];
>> + unsigned int div_stat_dmc0;
>> + unsigned int div_stat_dmc1;
>> + unsigned char res51[0x2f8];
>> + unsigned int gate_ip_dmc;
>> + unsigned int gate_ip_dmc1;
>> + unsigned char res52[0xf8];
>> + unsigned int clkout_cmu_dmc;
>> + unsigned int clkout_cmu_dmc_div_stat;
>> + unsigned char res53[0x5f8];
>> + unsigned int dcgidx_map0;
>> + unsigned int dcgidx_map1;
>> + unsigned int dcgidx_map2;
>> + unsigned char res54[0x14];
>> + unsigned int dcgperf_map0;
>> + unsigned int dcgperf_map1;
>> + unsigned char res55[0x18];
>> + unsigned int dvcidx_map;
>> + unsigned char res56[0x1c];
>> + unsigned int freq_cpu;
>> + unsigned int freq_dpm;
>> + unsigned char res57[0x18];
>> + unsigned int dvsemclk_en;
>> + unsigned int maxperf;
>> + unsigned char res58[0xc];
>> + unsigned int dmc_puause_ctrl;
>> + unsigned int ddrphy_lock_ctrl;
>> + unsigned int c2c_state;
>> + unsigned char res59[0x2f60];
>> + unsigned int apll_lock;
>> + unsigned char res60[0xfc];
>> + unsigned int apll_con0;
>> + unsigned int apll_con1;
>> + unsigned char res61[0xf8];
>> + unsigned int src_cpu;
>> + unsigned char res62[0x1fc];
>> + unsigned int mux_stat_cpu;
>> + unsigned char res63[0xfc];
>> + unsigned int div_cpu0;
>> + unsigned int div_cpu1;
>> + unsigned char res64[0xf8];
>> + unsigned int div_stat_cpu0;
>> + unsigned int div_stat_cpu1;
>> + unsigned char res65[0x2f8];
>> + unsigned int gate_ip_cpu;
>> + unsigned char res66[0xfc];
>> + unsigned int clkout_cmu_cpu;
>> + unsigned int clkout_cmu_cpu_div_stat;
>> + unsigned char res67[0x5f8];
>> + unsigned int armclk_stopctrl;
>> + unsigned int atclk_stopctrl;
>> + unsigned char res68[0x18];
>> + unsigned int pwr_ctrl;
>> + unsigned int pwr_ctrl2;
>> + unsigned char res69[0x3d8];
>> + unsigned int l2_status;
>> + unsigned char res70[0xc];
>> + unsigned int cpu_status;
>> + unsigned char res71[0xc];
>> + unsigned int ptm_status;
>> + unsigned char res72[0x2edc];
>> + unsigned int clk_div_isp0;
>> + unsigned int clk_div_isp1;
>> + unsigned char res73[0xf8];
>> + unsigned int clk_div_stat_isp0;
>> + unsigned int clk_div_stat_isp1;
>> + unsigned char res74[0x3f8];
>> + unsigned int gate_ip_isp0;
>> + unsigned int gate_ip_isp1;
>> + unsigned char res75[0x1f8];
>> + unsigned int clkout_cmu_isp;
>> + unsigned int clkout_cmu_isp_stat;
>> + unsigned char res76[0xf8];
>> + unsigned int clkout_cmu_spare0;
>> + unsigned int clkout_cmu_spare1;
>> + unsigned int clkout_cmu_spare2;
>> + unsigned int clkout_cmu_spare3;
>> +};
>> +
>> struct exynos5_clock {
>> unsigned int apll_lock;
>> unsigned char res1[0xfc];
>> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
>> index d1b2ea8..7ee5366 100644
>> --- a/arch/arm/include/asm/arch-exynos/cpu.h
>> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
>> @@ -152,6 +152,7 @@ static inline int proid_is_##type(void) \
>> }
>>
>> IS_EXYNOS_TYPE(exynos4210, 0x4210)
>> +IS_EXYNOS_TYPE(exynos4412, 0x4412)
>> IS_EXYNOS_TYPE(exynos5250, 0x5250)
>>
>> #define SAMSUNG_BASE(device, base) \
>> --
>> 1.7.9.5
>>
>
>
>
> --
> with warm regards,
> Chander Kashyap
--
with warm regards,
Chander Kashyap
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 3/4] EXYNOS4: Add support for Exynos4x12 SoCs
2012-12-13 6:19 ` Chander Kashyap
@ 2012-12-13 8:21 ` 김정현
2012-12-13 8:28 ` Chander Kashyap
0 siblings, 1 reply; 11+ messages in thread
From: 김정현 @ 2012-12-13 8:21 UTC (permalink / raw)
To: u-boot
Dear Chander,
2012? 12? 13? 15:19, Chander Kashyap ? ?:
> On 13 December 2012 11:49, Chander Kashyap <chander.kashyap@linaro.org> wrote:
>> Dear Kim,
>>
>> On 12 December 2012 13:24, Jeong Hyeon Kim <snow.jhkim@gmail.com> wrote:
>>> From: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
>>>
>>> This patch adds the support for Exynos4212/4412.
>>>
>>> Samsung's ARM Cortex-A9 based Exynos4x12 SoCs and Exynos4210 are similar.
>>> Address of a few registers are different in CMU part like MPLL.
>>>
>>> Signed-off-by: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
>>> ---
>>> arch/arm/cpu/armv7/exynos/clock.c | 7 +-
>>> arch/arm/include/asm/arch-exynos/clock.h | 240 ++++++++++++++++++++++++++++++
>>> arch/arm/include/asm/arch-exynos/cpu.h | 1 +
>>> 3 files changed, 247 insertions(+), 1 deletion(-)
>>>
>> As i discussed with you these changes has been already posted.
>> http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/148856
>> Kindly use them and resend yours patches.
>>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
>>> index fe61f88..47e2e6c 100644
>>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>> Please have a look patch at the link.
>> [PATCH] EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency
> http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/143640
I applied it and your resend patches at 7, Dec. to latest u-boot-samsung
tree.
http://patchwork.ozlabs.org/patch/204445/
It made compile error as below.
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h: In
function 'samsung_get_base_i2s':
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:208: error:
'EXYNOS4X12_I2S_BASE' undeclared (first use in this function)
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:208: error:
(Each undeclared identifier is reported only once
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:208: error:
for each function it appears in.)
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h: In
function 'samsung_get_base_spi':
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:226: error:
'EXYNOS4X12_SPI_BASE' undeclared (first use in this function)
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h: In
function 'samsung_get_base_spi_isp':
/workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:227: error:
'EXYNOS4X12_SPI_ISP_BASE' undeclared (first use in this function)
Please resend patches after fix it.
>
>>> @@ -94,7 +94,12 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
>>> r = readl(&clk->apll_con0);
>>> break;
>>> case MPLL:
>>> - r = readl(&clk->mpll_con0);
>>> + if (proid_is_exynos4412()) {
>>> + struct exynos4412_clock *clk4412 =
>>> + (struct exynos4412_clock *)samsung_get_base_clock();
>>> + r = readl(&clk4412->mpll_con0);
>>> + } else
>>> + r = readl(&clk->mpll_con0);
>>> break;
>>> case EPLL:
>>> r = readl(&clk->epll_con0);
>>> diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
>>> index ff6781a..5d4ed5c 100644
>>> --- a/arch/arm/include/asm/arch-exynos/clock.h
>>> +++ b/arch/arm/include/asm/arch-exynos/clock.h
>>> @@ -251,6 +251,246 @@ struct exynos4_clock {
>>> unsigned int div_iem_l1;
>>> };
>>>
>>> +struct exynos4412_clock {
>>> + unsigned char res1[0x4200];
>>> + unsigned int src_leftbus;
>>> + unsigned char res2[0x1fc];
>>> + unsigned int mux_stat_leftbus;
>>> + unsigned char res3[0xfc];
>>> + unsigned int div_leftbus;
>>> + unsigned char res4[0xfc];
>>> + unsigned int div_stat_leftbus;
>>> + unsigned char res5[0x1fc];
>>> + unsigned int gate_ip_leftbus;
>>> + unsigned char res6[0x12c];
>>> + unsigned int gate_ip_image;
>>> + unsigned char res7[0xcc];
>>> + unsigned int clkout_cmu_leftbus;
>>> + unsigned int clkout_cmu_leftbus_div_stat;
>>> + unsigned char res8[0x37f8];
>>> + unsigned int src_rightbus;
>>> + unsigned char res9[0x1fc];
>>> + unsigned int mux_stat_rightbus;
>>> + unsigned char res10[0xfc];
>>> + unsigned int div_rightbus;
>>> + unsigned char res11[0xfc];
>>> + unsigned int div_stat_rightbus;
>>> + unsigned char res12[0x1fc];
>>> + unsigned int gate_ip_rightbus;
>>> + unsigned char res13[0x15c];
>>> + unsigned int gate_ip_perir;
>>> + unsigned char res14[0x9c];
>>> + unsigned int clkout_cmu_rightbus;
>>> + unsigned int clkout_cmu_rightbus_div_stat;
>>> + unsigned char res15[0x3608];
>>> + unsigned int epll_lock;
>>> + unsigned char res16[0xc];
>>> + unsigned int vpll_lock;
>>> + unsigned char res17[0xec];
>>> + unsigned int epll_con0;
>>> + unsigned int epll_con1;
>>> + unsigned int epll_con2;
>>> + unsigned char res18[0x4];
>>> + unsigned int vpll_con0;
>>> + unsigned int vpll_con1;
>>> + unsigned int vpll_con2;
>>> + unsigned char res19[0xe4];
>>> + unsigned int src_top0;
>>> + unsigned int src_top1;
>>> + unsigned char res20[0x8];
>>> + unsigned int src_cam0;
>>> + unsigned int src_tv;
>>> + unsigned int src_mfc;
>>> + unsigned int src_g3d;
>>> + unsigned char res21[0x4];
>>> + unsigned int src_lcd0;
>>> + unsigned int src_isp;
>>> + unsigned int src_maudio;
>>> + unsigned int src_fsys;
>>> + unsigned char res22[0xc];
>>> + unsigned int src_peril0;
>>> + unsigned int src_peril1;
>>> + unsigned int src_cam1;
>>> + unsigned char res23[0xc4];
>>> + unsigned int src_mask_cam0;
>>> + unsigned int src_mask_tv;
>>> + unsigned char res24[0xc];
>>> + unsigned int src_mask_lcd;
>>> + unsigned int src_mask_isp;
>>> + unsigned int src_mask_maudio;
>>> + unsigned int src_mask_fsys;
>>> + unsigned char res25[0xc];
>>> + unsigned int src_mask_peril0;
>>> + unsigned int src_mask_peril1;
>>> + unsigned char res26[0xb8];
>>> + unsigned int mux_stat_top;
>>> + unsigned int mux_stat_top1;
>>> + unsigned char res27[0x10];
>>> + unsigned int mux_stat_mfc;
>>> + unsigned int mux_stat_g3d;
>>> + unsigned char res28[0x28];
>>> + unsigned int mux_stat_cam1;
>>> + unsigned char res29[0xb4];
>>> + unsigned int div_top;
>>> + unsigned char res30[0xc];
>>> + unsigned int div_cam0;
>>> + unsigned int div_tv;
>>> + unsigned int div_mfc;
>>> + unsigned int div_g3d;
>>> + unsigned char res31[0x4];
>>> + unsigned int div_lcd;
>>> + unsigned int div_isp;
>>> + unsigned int div_maudio;
>>> + unsigned int div_fsys0;
>>> + unsigned int div_fsys1;
>>> + unsigned int div_fsys2;
>>> + unsigned int div_fsys3;
>>> + unsigned int div_peril0;
>>> + unsigned int div_peril1;
>>> + unsigned int div_peril2;
>>> + unsigned int div_peril3;
>>> + unsigned int div_peril4;
>>> + unsigned int div_peril5;
>>> + unsigned int div_cam1;
>>> + unsigned char res32[0x14];
>>> + unsigned int div2_ratio;
>>> + unsigned char res33[0x8c];
>>> + unsigned int div_stat_top;
>>> + unsigned char res34[0xc];
>>> + unsigned int div_stat_cam0;
>>> + unsigned int div_stat_tv;
>>> + unsigned int div_stat_mfc;
>>> + unsigned int div_stat_g3d;
>>> + unsigned char res35[0x4];
>>> + unsigned int div_stat_lcd;
>>> + unsigned int div_stat_isp;
>>> + unsigned int div_stat_maudio;
>>> + unsigned int div_stat_fsys0;
>>> + unsigned int div_stat_fsys1;
>>> + unsigned int div_stat_fsys2;
>>> + unsigned int div_stat_fsys3;
>>> + unsigned int div_stat_peril0;
>>> + unsigned int div_stat_peril1;
>>> + unsigned int div_stat_peril2;
>>> + unsigned int div_stat_peril3;
>>> + unsigned int div_stat_peril4;
>>> + unsigned int div_stat_peril5;
>>> + unsigned int div_stat_cam1;
>>> + unsigned char res36[0x14];
>>> + unsigned int div2_stat;
>>> + unsigned char res37[0xc0];
>>> + unsigned int gate_bus_fsys1;
>>> + unsigned char res38[0x1d8];
>>> + unsigned int gate_ip_cam;
>>> + unsigned int gate_ip_tv;
>>> + unsigned int gate_ip_mfc;
>>> + unsigned int gate_ip_g3d;
>>> + unsigned char res39[0x4];
>>> + unsigned int gate_ip_lcd;
>>> + unsigned int gate_ip_isp;
>>> + unsigned char res40[0x4];
>>> + unsigned int gate_ip_fsys;
>>> + unsigned char res41[0x8];
>>> + unsigned int gate_ip_gps;
>>> + unsigned int gate_ip_peril;
>>> + unsigned char res42[0x1c];
>>> + unsigned int gate_block;
>>> + unsigned char res43[0x8c];
>>> + unsigned int clkout_cmu_top;
>>> + unsigned int clkout_cmu_top_div_stat;
>>> + unsigned char res44[0x3600];
>>> + unsigned int mpll_lock;
>>> + unsigned char res45[0xfc];
>>> + unsigned int mpll_con0;
>>> + unsigned int mpll_con1;
>>> + unsigned char res46[0xf0];
>>> + unsigned int src_dmc;
>>> + unsigned char res47[0xfc];
>>> + unsigned int src_mask_dmc;
>>> + unsigned char res48[0xfc];
>>> + unsigned int mux_stat_dmc;
>>> + unsigned char res49[0xfc];
>>> + unsigned int div_dmc0;
>>> + unsigned int div_dmc1;
>>> + unsigned char res50[0xf8];
>>> + unsigned int div_stat_dmc0;
>>> + unsigned int div_stat_dmc1;
>>> + unsigned char res51[0x2f8];
>>> + unsigned int gate_ip_dmc;
>>> + unsigned int gate_ip_dmc1;
>>> + unsigned char res52[0xf8];
>>> + unsigned int clkout_cmu_dmc;
>>> + unsigned int clkout_cmu_dmc_div_stat;
>>> + unsigned char res53[0x5f8];
>>> + unsigned int dcgidx_map0;
>>> + unsigned int dcgidx_map1;
>>> + unsigned int dcgidx_map2;
>>> + unsigned char res54[0x14];
>>> + unsigned int dcgperf_map0;
>>> + unsigned int dcgperf_map1;
>>> + unsigned char res55[0x18];
>>> + unsigned int dvcidx_map;
>>> + unsigned char res56[0x1c];
>>> + unsigned int freq_cpu;
>>> + unsigned int freq_dpm;
>>> + unsigned char res57[0x18];
>>> + unsigned int dvsemclk_en;
>>> + unsigned int maxperf;
>>> + unsigned char res58[0xc];
>>> + unsigned int dmc_puause_ctrl;
>>> + unsigned int ddrphy_lock_ctrl;
>>> + unsigned int c2c_state;
>>> + unsigned char res59[0x2f60];
>>> + unsigned int apll_lock;
>>> + unsigned char res60[0xfc];
>>> + unsigned int apll_con0;
>>> + unsigned int apll_con1;
>>> + unsigned char res61[0xf8];
>>> + unsigned int src_cpu;
>>> + unsigned char res62[0x1fc];
>>> + unsigned int mux_stat_cpu;
>>> + unsigned char res63[0xfc];
>>> + unsigned int div_cpu0;
>>> + unsigned int div_cpu1;
>>> + unsigned char res64[0xf8];
>>> + unsigned int div_stat_cpu0;
>>> + unsigned int div_stat_cpu1;
>>> + unsigned char res65[0x2f8];
>>> + unsigned int gate_ip_cpu;
>>> + unsigned char res66[0xfc];
>>> + unsigned int clkout_cmu_cpu;
>>> + unsigned int clkout_cmu_cpu_div_stat;
>>> + unsigned char res67[0x5f8];
>>> + unsigned int armclk_stopctrl;
>>> + unsigned int atclk_stopctrl;
>>> + unsigned char res68[0x18];
>>> + unsigned int pwr_ctrl;
>>> + unsigned int pwr_ctrl2;
>>> + unsigned char res69[0x3d8];
>>> + unsigned int l2_status;
>>> + unsigned char res70[0xc];
>>> + unsigned int cpu_status;
>>> + unsigned char res71[0xc];
>>> + unsigned int ptm_status;
>>> + unsigned char res72[0x2edc];
>>> + unsigned int clk_div_isp0;
>>> + unsigned int clk_div_isp1;
>>> + unsigned char res73[0xf8];
>>> + unsigned int clk_div_stat_isp0;
>>> + unsigned int clk_div_stat_isp1;
>>> + unsigned char res74[0x3f8];
>>> + unsigned int gate_ip_isp0;
>>> + unsigned int gate_ip_isp1;
>>> + unsigned char res75[0x1f8];
>>> + unsigned int clkout_cmu_isp;
>>> + unsigned int clkout_cmu_isp_stat;
>>> + unsigned char res76[0xf8];
>>> + unsigned int clkout_cmu_spare0;
>>> + unsigned int clkout_cmu_spare1;
>>> + unsigned int clkout_cmu_spare2;
>>> + unsigned int clkout_cmu_spare3;
>>> +};
>>> +
>>> struct exynos5_clock {
>>> unsigned int apll_lock;
>>> unsigned char res1[0xfc];
>>> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
>>> index d1b2ea8..7ee5366 100644
>>> --- a/arch/arm/include/asm/arch-exynos/cpu.h
>>> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
>>> @@ -152,6 +152,7 @@ static inline int proid_is_##type(void) \
>>> }
>>>
>>> IS_EXYNOS_TYPE(exynos4210, 0x4210)
>>> +IS_EXYNOS_TYPE(exynos4412, 0x4412)
>>> IS_EXYNOS_TYPE(exynos5250, 0x5250)
>>>
>>> #define SAMSUNG_BASE(device, base) \
>>> --
>>> 1.7.9.5
>>>
>>
>>
>> --
>> with warm regards,
>> Chander Kashyap
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 3/4] EXYNOS4: Add support for Exynos4x12 SoCs
2012-12-13 8:21 ` 김정현
@ 2012-12-13 8:28 ` Chander Kashyap
0 siblings, 0 replies; 11+ messages in thread
From: Chander Kashyap @ 2012-12-13 8:28 UTC (permalink / raw)
To: u-boot
Dear Kim,
On 13 December 2012 13:51, ??? <jhkim@insignal.co.kr> wrote:
> Dear Chander,
>
> 2012? 12? 13? 15:19, Chander Kashyap ? ?:
>
> On 13 December 2012 11:49, Chander Kashyap <chander.kashyap@linaro.org>
> wrote:
>
> Dear Kim,
>
> On 12 December 2012 13:24, Jeong Hyeon Kim <snow.jhkim@gmail.com> wrote:
>
> From: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
>
> This patch adds the support for Exynos4212/4412.
>
> Samsung's ARM Cortex-A9 based Exynos4x12 SoCs and Exynos4210 are similar.
> Address of a few registers are different in CMU part like MPLL.
>
> Signed-off-by: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
> ---
> arch/arm/cpu/armv7/exynos/clock.c | 7 +-
> arch/arm/include/asm/arch-exynos/clock.h | 240
> ++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-exynos/cpu.h | 1 +
> 3 files changed, 247 insertions(+), 1 deletion(-)
>
> As i discussed with you these changes has been already posted.
> http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/148856
> Kindly use them and resend yours patches.
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index fe61f88..47e2e6c 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>
> Please have a look patch at the link.
> [PATCH] EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency
>
> http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/143640
>
> I applied it and your resend patches at 7, Dec. to latest u-boot-samsung
> tree.
> http://patchwork.ozlabs.org/patch/204445/
>
> It made compile error as below.
> /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h: In
> function 'samsung_get_base_i2s':
> /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:208:
> error: 'EXYNOS4X12_I2S_BASE' undeclared (first use in this function)
> /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:208:
> error: (Each undeclared identifier is reported only once
> /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:208:
> error: for each function it appears in.)
> /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h: In
> function 'samsung_get_base_spi':
> /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:226:
> error: 'EXYNOS4X12_SPI_BASE' undeclared (first use in this function)
> /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h: In
> function 'samsung_get_base_spi_isp':
> /workspace/insignal/bootloader/u-boot-samsung/include/asm/arch/cpu.h:227:
> error: 'EXYNOS4X12_SPI_ISP_BASE' undeclared (first use in this function)
You need apply my patches. Then add these base addresses in cpu.h and
create a patch. Then add yours board specific patches.
>
> Please resend patches after fix it.
>
>
>
> @@ -94,7 +94,12 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
> r = readl(&clk->apll_con0);
> break;
> case MPLL:
> - r = readl(&clk->mpll_con0);
> + if (proid_is_exynos4412()) {
> + struct exynos4412_clock *clk4412 =
> + (struct exynos4412_clock
> *)samsung_get_base_clock();
> + r = readl(&clk4412->mpll_con0);
> + } else
> + r = readl(&clk->mpll_con0);
> break;
> case EPLL:
> r = readl(&clk->epll_con0);
> diff --git a/arch/arm/include/asm/arch-exynos/clock.h
> b/arch/arm/include/asm/arch-exynos/clock.h
> index ff6781a..5d4ed5c 100644
> --- a/arch/arm/include/asm/arch-exynos/clock.h
> +++ b/arch/arm/include/asm/arch-exynos/clock.h
> @@ -251,6 +251,246 @@ struct exynos4_clock {
> unsigned int div_iem_l1;
> };
>
> +struct exynos4412_clock {
> + unsigned char res1[0x4200];
> + unsigned int src_leftbus;
> + unsigned char res2[0x1fc];
> + unsigned int mux_stat_leftbus;
> + unsigned char res3[0xfc];
> + unsigned int div_leftbus;
> + unsigned char res4[0xfc];
> + unsigned int div_stat_leftbus;
> + unsigned char res5[0x1fc];
> + unsigned int gate_ip_leftbus;
> + unsigned char res6[0x12c];
> + unsigned int gate_ip_image;
> + unsigned char res7[0xcc];
> + unsigned int clkout_cmu_leftbus;
> + unsigned int clkout_cmu_leftbus_div_stat;
> + unsigned char res8[0x37f8];
> + unsigned int src_rightbus;
> + unsigned char res9[0x1fc];
> + unsigned int mux_stat_rightbus;
> + unsigned char res10[0xfc];
> + unsigned int div_rightbus;
> + unsigned char res11[0xfc];
> + unsigned int div_stat_rightbus;
> + unsigned char res12[0x1fc];
> + unsigned int gate_ip_rightbus;
> + unsigned char res13[0x15c];
> + unsigned int gate_ip_perir;
> + unsigned char res14[0x9c];
> + unsigned int clkout_cmu_rightbus;
> + unsigned int clkout_cmu_rightbus_div_stat;
> + unsigned char res15[0x3608];
> + unsigned int epll_lock;
> + unsigned char res16[0xc];
> + unsigned int vpll_lock;
> + unsigned char res17[0xec];
> + unsigned int epll_con0;
> + unsigned int epll_con1;
> + unsigned int epll_con2;
> + unsigned char res18[0x4];
> + unsigned int vpll_con0;
> + unsigned int vpll_con1;
> + unsigned int vpll_con2;
> + unsigned char res19[0xe4];
> + unsigned int src_top0;
> + unsigned int src_top1;
> + unsigned char res20[0x8];
> + unsigned int src_cam0;
> + unsigned int src_tv;
> + unsigned int src_mfc;
> + unsigned int src_g3d;
> + unsigned char res21[0x4];
> + unsigned int src_lcd0;
> + unsigned int src_isp;
> + unsigned int src_maudio;
> + unsigned int src_fsys;
> + unsigned char res22[0xc];
> + unsigned int src_peril0;
> + unsigned int src_peril1;
> + unsigned int src_cam1;
> + unsigned char res23[0xc4];
> + unsigned int src_mask_cam0;
> + unsigned int src_mask_tv;
> + unsigned char res24[0xc];
> + unsigned int src_mask_lcd;
> + unsigned int src_mask_isp;
> + unsigned int src_mask_maudio;
> + unsigned int src_mask_fsys;
> + unsigned char res25[0xc];
> + unsigned int src_mask_peril0;
> + unsigned int src_mask_peril1;
> + unsigned char res26[0xb8];
> + unsigned int mux_stat_top;
> + unsigned int mux_stat_top1;
> + unsigned char res27[0x10];
> + unsigned int mux_stat_mfc;
> + unsigned int mux_stat_g3d;
> + unsigned char res28[0x28];
> + unsigned int mux_stat_cam1;
> + unsigned char res29[0xb4];
> + unsigned int div_top;
> + unsigned char res30[0xc];
> + unsigned int div_cam0;
> + unsigned int div_tv;
> + unsigned int div_mfc;
> + unsigned int div_g3d;
> + unsigned char res31[0x4];
> + unsigned int div_lcd;
> + unsigned int div_isp;
> + unsigned int div_maudio;
> + unsigned int div_fsys0;
> + unsigned int div_fsys1;
> + unsigned int div_fsys2;
> + unsigned int div_fsys3;
> + unsigned int div_peril0;
> + unsigned int div_peril1;
> + unsigned int div_peril2;
> + unsigned int div_peril3;
> + unsigned int div_peril4;
> + unsigned int div_peril5;
> + unsigned int div_cam1;
> + unsigned char res32[0x14];
> + unsigned int div2_ratio;
> + unsigned char res33[0x8c];
> + unsigned int div_stat_top;
> + unsigned char res34[0xc];
> + unsigned int div_stat_cam0;
> + unsigned int div_stat_tv;
> + unsigned int div_stat_mfc;
> + unsigned int div_stat_g3d;
> + unsigned char res35[0x4];
> + unsigned int div_stat_lcd;
> + unsigned int div_stat_isp;
> + unsigned int div_stat_maudio;
> + unsigned int div_stat_fsys0;
> + unsigned int div_stat_fsys1;
> + unsigned int div_stat_fsys2;
> + unsigned int div_stat_fsys3;
> + unsigned int div_stat_peril0;
> + unsigned int div_stat_peril1;
> + unsigned int div_stat_peril2;
> + unsigned int div_stat_peril3;
> + unsigned int div_stat_peril4;
> + unsigned int div_stat_peril5;
> + unsigned int div_stat_cam1;
> + unsigned char res36[0x14];
> + unsigned int div2_stat;
> + unsigned char res37[0xc0];
> + unsigned int gate_bus_fsys1;
> + unsigned char res38[0x1d8];
> + unsigned int gate_ip_cam;
> + unsigned int gate_ip_tv;
> + unsigned int gate_ip_mfc;
> + unsigned int gate_ip_g3d;
> + unsigned char res39[0x4];
> + unsigned int gate_ip_lcd;
> + unsigned int gate_ip_isp;
> + unsigned char res40[0x4];
> + unsigned int gate_ip_fsys;
> + unsigned char res41[0x8];
> + unsigned int gate_ip_gps;
> + unsigned int gate_ip_peril;
> + unsigned char res42[0x1c];
> + unsigned int gate_block;
> + unsigned char res43[0x8c];
> + unsigned int clkout_cmu_top;
> + unsigned int clkout_cmu_top_div_stat;
> + unsigned char res44[0x3600];
> + unsigned int mpll_lock;
> + unsigned char res45[0xfc];
> + unsigned int mpll_con0;
> + unsigned int mpll_con1;
> + unsigned char res46[0xf0];
> + unsigned int src_dmc;
> + unsigned char res47[0xfc];
> + unsigned int src_mask_dmc;
> + unsigned char res48[0xfc];
> + unsigned int mux_stat_dmc;
> + unsigned char res49[0xfc];
> + unsigned int div_dmc0;
> + unsigned int div_dmc1;
> + unsigned char res50[0xf8];
> + unsigned int div_stat_dmc0;
> + unsigned int div_stat_dmc1;
> + unsigned char res51[0x2f8];
> + unsigned int gate_ip_dmc;
> + unsigned int gate_ip_dmc1;
> + unsigned char res52[0xf8];
> + unsigned int clkout_cmu_dmc;
> + unsigned int clkout_cmu_dmc_div_stat;
> + unsigned char res53[0x5f8];
> + unsigned int dcgidx_map0;
> + unsigned int dcgidx_map1;
> + unsigned int dcgidx_map2;
> + unsigned char res54[0x14];
> + unsigned int dcgperf_map0;
> + unsigned int dcgperf_map1;
> + unsigned char res55[0x18];
> + unsigned int dvcidx_map;
> + unsigned char res56[0x1c];
> + unsigned int freq_cpu;
> + unsigned int freq_dpm;
> + unsigned char res57[0x18];
> + unsigned int dvsemclk_en;
> + unsigned int maxperf;
> + unsigned char res58[0xc];
> + unsigned int dmc_puause_ctrl;
> + unsigned int ddrphy_lock_ctrl;
> + unsigned int c2c_state;
> + unsigned char res59[0x2f60];
> + unsigned int apll_lock;
> + unsigned char res60[0xfc];
> + unsigned int apll_con0;
> + unsigned int apll_con1;
> + unsigned char res61[0xf8];
> + unsigned int src_cpu;
> + unsigned char res62[0x1fc];
> + unsigned int mux_stat_cpu;
> + unsigned char res63[0xfc];
> + unsigned int div_cpu0;
> + unsigned int div_cpu1;
> + unsigned char res64[0xf8];
> + unsigned int div_stat_cpu0;
> + unsigned int div_stat_cpu1;
> + unsigned char res65[0x2f8];
> + unsigned int gate_ip_cpu;
> + unsigned char res66[0xfc];
> + unsigned int clkout_cmu_cpu;
> + unsigned int clkout_cmu_cpu_div_stat;
> + unsigned char res67[0x5f8];
> + unsigned int armclk_stopctrl;
> + unsigned int atclk_stopctrl;
> + unsigned char res68[0x18];
> + unsigned int pwr_ctrl;
> + unsigned int pwr_ctrl2;
> + unsigned char res69[0x3d8];
> + unsigned int l2_status;
> + unsigned char res70[0xc];
> + unsigned int cpu_status;
> + unsigned char res71[0xc];
> + unsigned int ptm_status;
> + unsigned char res72[0x2edc];
> + unsigned int clk_div_isp0;
> + unsigned int clk_div_isp1;
> + unsigned char res73[0xf8];
> + unsigned int clk_div_stat_isp0;
> + unsigned int clk_div_stat_isp1;
> + unsigned char res74[0x3f8];
> + unsigned int gate_ip_isp0;
> + unsigned int gate_ip_isp1;
> + unsigned char res75[0x1f8];
> + unsigned int clkout_cmu_isp;
> + unsigned int clkout_cmu_isp_stat;
> + unsigned char res76[0xf8];
> + unsigned int clkout_cmu_spare0;
> + unsigned int clkout_cmu_spare1;
> + unsigned int clkout_cmu_spare2;
> + unsigned int clkout_cmu_spare3;
> +};
> +
> struct exynos5_clock {
> unsigned int apll_lock;
> unsigned char res1[0xfc];
> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
> b/arch/arm/include/asm/arch-exynos/cpu.h
> index d1b2ea8..7ee5366 100644
> --- a/arch/arm/include/asm/arch-exynos/cpu.h
> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
> @@ -152,6 +152,7 @@ static inline int proid_is_##type(void)
> \
> }
>
> IS_EXYNOS_TYPE(exynos4210, 0x4210)
> +IS_EXYNOS_TYPE(exynos4412, 0x4412)
> IS_EXYNOS_TYPE(exynos5250, 0x5250)
>
> #define SAMSUNG_BASE(device, base) \
> --
> 1.7.9.5
>
>
>
> --
> with warm regards,
> Chander Kashyap
>
>
>
--
with warm regards,
Chander Kashyap
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2012-12-13 8:28 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-12-12 7:54 [U-Boot] [PATCH 0/4] Add support for SAMSUNG Exynos4 SoCs and ORIGEN_QUAD board Jeong Hyeon Kim
2012-12-12 7:54 ` [U-Boot] [PATCH 1/4] EXYNOS4: Add pinmux support for UART Jeong Hyeon Kim
2012-12-12 7:54 ` [U-Boot] [PATCH 2/4] EXYNOS4: Add pinmux support for I2C Jeong Hyeon Kim
2012-12-12 8:16 ` Heiko Schocher
2012-12-12 10:19 ` 김정현
2012-12-12 7:54 ` [U-Boot] [PATCH 3/4] EXYNOS4: Add support for Exynos4x12 SoCs Jeong Hyeon Kim
2012-12-13 6:19 ` Chander Kashyap
2012-12-13 6:19 ` Chander Kashyap
2012-12-13 8:21 ` 김정현
2012-12-13 8:28 ` Chander Kashyap
2012-12-12 7:54 ` [U-Boot] [PATCH 4/4] EXYNOS4: Add ORIGEN_QUAD board support Jeong Hyeon Kim
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