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From: "Andreas Färber" <afaerber@suse.de>
To: Alexander Graf <agraf@suse.de>
Cc: Bharat Bhushan <bharat.bhushan@freescale.com>,
	"qemu-ppc@nongnu.org List" <qemu-ppc@nongnu.org>,
	qemu-devel qemu-devel <qemu-devel@nongnu.org>,
	Bharat Bhushan <r65777@freescale.com>
Subject: Re: [Qemu-devel] [PATCH 10/40] Adding BAR0 for e500 PCI controller
Date: Fri, 14 Dec 2012 14:49:52 +0100	[thread overview]
Message-ID: <50CB2E80.8010809@suse.de> (raw)
In-Reply-To: <1355487236-27451-11-git-send-email-agraf@suse.de>

Am 14.12.2012 13:13, schrieb Alexander Graf:
> From: Bharat Bhushan <r65777@freescale.com>
> 
> PCI Root complex have TYPE-1 configuration header while PCI endpoint
> have type-0 configuration header. The type-1 configuration header have
> a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
> address space to CCSR address space. This can used for 2 purposes: 1)
> for MSI interrupt generation 2) Allow CCSR registers access when configured
> as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest.
> 
> What I observed is that when guest read the size of BAR0 of host controller
> configuration header (TYPE1 header) then it always reads it as 0. When
> looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller
> device registering BAR0. I do not find any other controller also doing so
> may they do not use BAR0.
> 
> There are two issues when BAR0 is not there (which I can think of):
> 1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) and
> when reading the size of BAR0, it should give size as per real h/w.
> 
> 2) Do we need this BAR0 inbound address translation?
>         When BAR0 is of non-zero size then it will be configured for PCI
> address space to local address(CCSR) space translation on inbound access.
> The primary use case is for MSI interrupt generation. The device is
> configured with an address offsets in PCI address space, which will be
> translated to MSI interrupt generation MPIC registers. Currently I do
> not understand the MSI interrupt generation mechanism in QEMU and also
> IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines.
> But this BAR0 will be used when using MSI on e500.
> 
> I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c,
> but i do not see these being used for address translation.
> So far that works because pci address space and local address space are 1:1
> mapped. BAR0 inbound translation + ATMU translation will complete the address
> translation of inbound traffic.
> 
> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
> [agraf: fix double variable assignment w/o read]
> Signed-off-by: Alexander Graf <agraf@suse.de>

Reviewed-by: Andreas Färber <afaerber@suse.de>

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

  reply	other threads:[~2012-12-14 13:49 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 01/40] pseries: Fix incorrect initialization of interrupt controller Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 02/40] pseries: Use #define for XICS base irq number Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 03/40] pseries: Return the token when we register an RTAS call Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 04/40] pseries: Allow RTAS tokens without a qemu handler Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 05/40] pseries: Add tracepoints to the XICS interrupt controller Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 06/40] pseries: Split xics irq configuration from state information Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 07/40] pseries: Implement PAPR NVRAM Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 08/40] pseries: Update SLOF for NVRAM support Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 09/40] e500: Adding CCSR memory region Alexander Graf
2012-12-14 13:47   ` Andreas Färber
2012-12-14 12:13 ` [Qemu-devel] [PATCH 10/40] Adding BAR0 for e500 PCI controller Alexander Graf
2012-12-14 13:49   ` Andreas Färber [this message]
2012-12-14 12:13 ` [Qemu-devel] [PATCH 11/40] pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNs Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 12/40] openpic: Remove unused code Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 13/40] mpic: Unify numbering scheme Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 14/40] openpic: update to proper memory api Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 15/40] openpic: combine mpic and openpic src handlers Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 16/40] openpic: Convert subregions to memory api Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 17/40] openpic: combine mpic and openpic irq raise functions Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 18/40] openpic: merge mpic and openpic timer handling Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 19/40] openpic: combine openpic and mpic reset functions Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 20/40] openpic: unify memory api subregions Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 21/40] openpic: remove unused type variable Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 22/40] openpic: convert simple reg operations to builtin bitops Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 23/40] openpic: rename openpic_t to OpenPICState Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 24/40] openpic: remove irq_out Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 25/40] openpic: convert to qdev Alexander Graf
2012-12-14 20:32   ` Blue Swirl
2012-12-14 20:42     ` Alexander Graf
2012-12-14 20:50       ` Blue Swirl
2012-12-14 12:13 ` [Qemu-devel] [PATCH 26/40] openpic: make brr1 model specific Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 27/40] openpic: add Shared MSI support Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 28/40] PPC: e500: Add " Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 29/40] PPC: e500: Declare pci bridge as bridge Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 30/40] MSI-X: Fix endianness Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 31/40] openpic: fix minor coding style issues Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 32/40] openpic: Accelerate pending irq search Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 33/40] PPC: E500: PCI: Make first slot qdev settable Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 34/40] PPC: E500: PCI: Make IRQ calculation more generic Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 35/40] PPC: E500: Generate dt pci irq map dynamically Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 36/40] PPC: E500: Move PCI slot information into params Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 37/40] PPC: E500plat: Make a lot of PCI slots available Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 38/40] PPC: e500: pci: Export slot2irq calculation Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 39/40] target-ppc: Don't use hwaddr to represent hardware state Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 40/40] pseries: Increase default NVRAM size Alexander Graf
2012-12-15 10:09 ` [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Blue Swirl

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